1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
7 #ifndef __ECORE_INT_API_H__
8 #define __ECORE_INT_API_H__
10 #ifndef __EXTRACT__LINUX__
11 #define ECORE_SB_IDX 0x0002
14 #define TX_PI(tc) (RX_PI + 1 + tc)
16 #ifndef ECORE_INT_MODE
17 #define ECORE_INT_MODE
26 struct ecore_sb_info {
27 void *sb_virt; /* ptr to "struct status_block_e{4,5}" */
28 u32 sb_size; /* size of "struct status_block_e{4,5}" */
29 __le16 *sb_pi_array; /* ptr to "sb_virt->pi_array" */
30 __le32 *sb_prod_index; /* ptr to "sb_virt->prod_index" */
31 #define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF
34 u32 sb_ack; /* Last given ack */
36 void OSAL_IOMEM *igu_addr;
38 #define ECORE_SB_INFO_INIT 0x1
39 #define ECORE_SB_INFO_SETUP 0x2
41 #ifdef ECORE_CONFIG_DIRECT_HWFN
42 struct ecore_hwfn *p_hwfn;
44 struct ecore_dev *p_dev;
47 struct ecore_sb_info_dbg {
53 struct ecore_sb_cnt_info {
54 /* Original, current, and free SBs for PF */
59 /* Original, current and free SBS for child VFs */
65 static OSAL_INLINE u16 ecore_sb_update_sb_idx(struct ecore_sb_info *sb_info)
70 /* barrier(); status block is written to by the chip */
71 /* FIXME: need some sort of barrier. */
72 prod = OSAL_LE32_TO_CPU(*sb_info->sb_prod_index) &
73 STATUS_BLOCK_PROD_INDEX_MASK;
74 if (sb_info->sb_ack != prod) {
75 sb_info->sb_ack = prod;
79 OSAL_MMIOWB(sb_info->p_dev);
85 * @brief This function creates an update command for interrupts that is
88 * @param sb_info - This is the structure allocated and
89 * initialized per status block. Assumption is
90 * that it was initialized using ecore_sb_init
91 * @param int_cmd - Enable/Disable/Nop
92 * @param upd_flg - whether igu consumer should be
95 * @return OSAL_INLINE void
97 static OSAL_INLINE void ecore_sb_ack(struct ecore_sb_info *sb_info,
98 enum igu_int_cmd int_cmd, u8 upd_flg)
100 struct igu_prod_cons_update igu_ack;
102 OSAL_MEMSET(&igu_ack, 0, sizeof(struct igu_prod_cons_update));
103 igu_ack.sb_id_and_flags =
104 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
105 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
106 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
107 (IGU_SEG_ACCESS_REG << IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
109 #ifdef ECORE_CONFIG_DIRECT_HWFN
110 DIRECT_REG_WR(sb_info->p_hwfn, sb_info->igu_addr,
111 igu_ack.sb_id_and_flags);
113 DIRECT_REG_WR(OSAL_NULL, sb_info->igu_addr, igu_ack.sb_id_and_flags);
115 /* Both segments (interrupts & acks) are written to same place address;
116 * Need to guarantee all commands will be received (in-order) by HW.
118 OSAL_MMIOWB(sb_info->p_dev);
119 OSAL_BARRIER(sb_info->p_dev);
122 #ifdef ECORE_CONFIG_DIRECT_HWFN
123 static OSAL_INLINE void __internal_ram_wr(struct ecore_hwfn *p_hwfn,
124 void OSAL_IOMEM *addr,
127 static OSAL_INLINE void __internal_ram_wr(__rte_unused void *p_hwfn,
128 void OSAL_IOMEM *addr,
134 for (i = 0; i < size / sizeof(*data); i++)
135 DIRECT_REG_WR(p_hwfn, &((u32 OSAL_IOMEM *)addr)[i], data[i]);
138 #ifdef ECORE_CONFIG_DIRECT_HWFN
139 static OSAL_INLINE void __internal_ram_wr_relaxed(struct ecore_hwfn *p_hwfn,
140 void OSAL_IOMEM * addr,
143 static OSAL_INLINE void __internal_ram_wr_relaxed(__rte_unused void *p_hwfn,
144 void OSAL_IOMEM * addr,
150 for (i = 0; i < size / sizeof(*data); i++)
151 DIRECT_REG_WR_RELAXED(p_hwfn, &((u32 OSAL_IOMEM *)addr)[i],
155 #ifdef ECORE_CONFIG_DIRECT_HWFN
156 static OSAL_INLINE void internal_ram_wr(struct ecore_hwfn *p_hwfn,
157 void OSAL_IOMEM * addr,
160 __internal_ram_wr_relaxed(p_hwfn, addr, size, data);
163 static OSAL_INLINE void internal_ram_wr(void OSAL_IOMEM *addr,
166 __internal_ram_wr_relaxed(OSAL_NULL, addr, size, data);
175 enum ecore_coalescing_fsm {
176 ECORE_COAL_RX_STATE_MACHINE,
177 ECORE_COAL_TX_STATE_MACHINE
181 * @brief ecore_int_cau_conf_pi - configure cau for a given
191 void ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
192 struct ecore_ptt *p_ptt,
193 struct ecore_sb_info *p_sb,
195 enum ecore_coalescing_fsm coalescing_fsm,
200 * @brief ecore_int_igu_enable_int - enable device interrupts
204 * @param int_mode - interrupt mode to use
206 void ecore_int_igu_enable_int(struct ecore_hwfn *p_hwfn,
207 struct ecore_ptt *p_ptt,
208 enum ecore_int_mode int_mode);
212 * @brief ecore_int_igu_disable_int - disable device interrupts
217 void ecore_int_igu_disable_int(struct ecore_hwfn *p_hwfn,
218 struct ecore_ptt *p_ptt);
222 * @brief ecore_int_igu_read_sisr_reg - Reads the single isr multiple dpc
229 u64 ecore_int_igu_read_sisr_reg(struct ecore_hwfn *p_hwfn);
231 #define ECORE_SP_SB_ID 0xffff
234 * @brief ecore_int_sb_init - Initializes the sb_info structure.
236 * once the structure is initialized it can be passed to sb related functions.
240 * @param sb_info points to an uninitialized (but
241 * allocated) sb_info structure
242 * @param sb_virt_addr
244 * @param sb_id the sb_id to be used (zero based in driver)
245 * should use ECORE_SP_SB_ID for SP Status block
247 * @return enum _ecore_status_t
249 enum _ecore_status_t ecore_int_sb_init(struct ecore_hwfn *p_hwfn,
250 struct ecore_ptt *p_ptt,
251 struct ecore_sb_info *sb_info,
253 dma_addr_t sb_phy_addr, u16 sb_id);
255 * @brief ecore_int_sb_setup - Setup the sb.
259 * @param sb_info initialized sb_info structure
261 void ecore_int_sb_setup(struct ecore_hwfn *p_hwfn,
262 struct ecore_ptt *p_ptt, struct ecore_sb_info *sb_info);
265 * @brief ecore_int_sb_release - releases the sb_info structure.
267 * once the structure is released, it's memory can be freed
270 * @param sb_info points to an allocated sb_info structure
271 * @param sb_id the sb_id to be used (zero based in driver)
272 * should never be equal to ECORE_SP_SB_ID
275 * @return enum _ecore_status_t
277 enum _ecore_status_t ecore_int_sb_release(struct ecore_hwfn *p_hwfn,
278 struct ecore_sb_info *sb_info,
282 * @brief ecore_int_sp_dpc - To be called when an interrupt is received on the
283 * default status block.
285 * @param p_hwfn - pointer to hwfn
288 void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie);
291 * @brief ecore_int_get_num_sbs - get the number of status
292 * blocks configured for this funciton in the igu.
295 * @param p_sb_cnt_info
299 void ecore_int_get_num_sbs(struct ecore_hwfn *p_hwfn,
300 struct ecore_sb_cnt_info *p_sb_cnt_info);
303 * @brief ecore_int_disable_post_isr_release - performs the cleanup post ISR
304 * release. The API need to be called after releasing all slowpath IRQs
310 void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev);
313 * @brief ecore_int_attn_clr_enable - sets whether the general behavior is
314 * preventing attentions from being reasserted, or following the
315 * attributes of the specific attention.
321 void ecore_int_attn_clr_enable(struct ecore_dev *p_dev, bool clr_enable);
324 * @brief Read debug information regarding a given SB.
328 * @param p_sb - point to Status block for which we want to get info.
329 * @param p_info - pointer to struct to fill with information regarding SB.
331 * @return ECORE_SUCCESS if pointer is filled; failure otherwise.
333 enum _ecore_status_t ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn,
334 struct ecore_ptt *p_ptt,
335 struct ecore_sb_info *p_sb,
336 struct ecore_sb_info_dbg *p_info);
339 * @brief - Move a free Status block between PF and child VF
343 * @param sb_id - The PF fastpath vector to be moved [re-assigned if claiming
344 * from VF, given-up if moving to VF]
345 * @param b_to_vf - PF->VF == true, VF->PF == false
347 * @return ECORE_SUCCESS if SB successfully moved.
350 ecore_int_igu_relocate_sb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
351 u16 sb_id, bool b_to_vf);
354 * @brief - Doorbell Recovery handler.
355 * Run DB_REAL_DEAL doorbell recovery in case of PF overflow
356 * (and flush DORQ if needed), otherwise run DB_REC_ONCE.
361 enum _ecore_status_t ecore_db_rec_handler(struct ecore_hwfn *p_hwfn,
362 struct ecore_ptt *p_ptt);