2 * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written consent.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGE.
40 #if __BYTE_ORDER == __LITTLE_ENDIAN
44 #ifndef __LITTLE_ENDIAN
45 #define __LITTLE_ENDIAN
49 #else /* _BIG_ENDIAN */
57 #undef __LITTLE_ENDIAN
60 #include "ecore_mfw_req.h"
61 #include "ecore_fw_defs.h"
62 #include "ecore_hsi.h"
63 #include "ecore_reg.h"
66 typedef phys_addr_t ecore_dma_addr_t; /* expected to be 64 bit wide */
67 typedef volatile int ecore_atomic_t;
70 #define ETH_ALEN ETHER_ADDR_LEN /* 6 */
72 #define ECORE_SWCID_SHIFT 17
73 #define ECORE_SWCID_MASK ((0x1 << ECORE_SWCID_SHIFT) - 1)
75 #define ECORE_MC_HASH_SIZE 8
76 #define ECORE_MC_HASH_OFFSET(sc, i) \
77 (BAR_TSTRORM_INTMEM + \
78 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(FUNC_ID(sc)) + i*4)
80 #define ECORE_MAX_MULTICAST 64
81 #define ECORE_MAX_EMUL_MULTI 1
83 #define IRO sc->iro_array
85 typedef rte_spinlock_t ECORE_MUTEX;
86 #define ECORE_MUTEX_INIT(_mutex) rte_spinlock_init(_mutex)
87 #define ECORE_MUTEX_LOCK(_mutex) rte_spinlock_lock(_mutex)
88 #define ECORE_MUTEX_UNLOCK(_mutex) rte_spinlock_unlock(_mutex)
90 typedef rte_spinlock_t ECORE_MUTEX_SPIN;
91 #define ECORE_SPIN_LOCK_INIT(_spin, _sc) rte_spinlock_init(_spin)
92 #define ECORE_SPIN_LOCK_BH(_spin) rte_spinlock_lock(_spin) /* bh = bottom-half */
93 #define ECORE_SPIN_UNLOCK_BH(_spin) rte_spinlock_unlock(_spin) /* bh = bottom-half */
95 #define ECORE_SMP_MB_AFTER_CLEAR_BIT() mb()
96 #define ECORE_SMP_MB_BEFORE_CLEAR_BIT() mb()
97 #define ECORE_SMP_MB() mb()
98 #define ECORE_SMP_RMB() rmb()
99 #define ECORE_SMP_WMB() wmb()
100 #define ECORE_MMIOWB() wmb()
102 #define ECORE_SET_BIT_NA(bit, var) (*var |= (1 << bit))
103 #define ECORE_CLEAR_BIT_NA(bit, var) (*var &= ~(1 << bit))
105 #define ECORE_TEST_BIT(bit, var) bnx2x_test_bit(bit, var)
106 #define ECORE_SET_BIT(bit, var) bnx2x_set_bit(bit, var)
107 #define ECORE_CLEAR_BIT(bit, var) bnx2x_clear_bit(bit, var)
108 #define ECORE_TEST_AND_CLEAR_BIT(bit, var) bnx2x_test_and_clear_bit(bit, var)
110 #define atomic_load_acq_int (int)*
111 #define atomic_store_rel_int(a, v) (*a = v)
112 #define atomic_cmpset_acq_int(a, o, n) ((*a = (o & (n)) | (n)) ^ o)
114 #define atomic_load_acq_long (long)*
115 #define atomic_store_rel_long(a, v) (*a = v)
116 #define atomic_set_acq_long(a, v) (*a |= v)
117 #define atomic_clear_acq_long(a, v) (*a &= ~v)
118 #define atomic_cmpset_acq_long(a, o, n) ((*a = (o & (n)) | (n)) ^ o)
119 #define atomic_subtract_acq_long(a, v) (*a -= v)
120 #define atomic_add_acq_long(a, v) (*a += v)
122 #define ECORE_ATOMIC_READ(a) atomic_load_acq_int((volatile int *)a)
123 #define ECORE_ATOMIC_SET(a, v) atomic_store_rel_int((volatile int *)a, v)
124 #define ECORE_ATOMIC_CMPXCHG(a, o, n) bnx2x_cmpxchg((volatile int *)a, o, n)
126 #define ECORE_RET_PENDING(pending_bit, pending) \
127 (ECORE_TEST_BIT(pending_bit, pending) ? ECORE_PENDING : ECORE_SUCCESS)
129 #define ECORE_SET_FLAG(value, mask, flag) \
131 (value) &= ~(mask); \
132 (value) |= ((flag) << (mask##_SHIFT)); \
135 #define ECORE_GET_FLAG(value, mask) \
136 (((value) &= (mask)) >> (mask##_SHIFT))
138 #define ECORE_MIGHT_SLEEP()
140 #define ECORE_FCOE_CID(sc) ((sc)->fp[FCOE_IDX(sc)].cl_id)
142 #define ECORE_MEMCMP(_a, _b, _s) memcmp(_a, _b, _s)
143 #define ECORE_MEMCPY(_a, _b, _s) (void)rte_memcpy(_a, _b, _s)
144 #define ECORE_MEMSET(_a, _c, _s) memset(_a, _c, _s)
146 #define ECORE_CPU_TO_LE16(x) htole16(x)
147 #define ECORE_CPU_TO_LE32(x) htole32(x)
149 #define ECORE_WAIT(_s, _t) DELAY(1000)
150 #define ECORE_MSLEEP(_t) DELAY((_t) * 1000)
152 #define ECORE_LIKELY(x) likely(x)
153 #define ECORE_UNLIKELY(x) unlikely(x)
155 #define ECORE_ZALLOC(_size, _flags, _sc) \
156 rte_zmalloc("", _size, RTE_CACHE_LINE_SIZE)
158 #define ECORE_CALLOC(_len, _size, _flags, _sc) \
159 rte_calloc("", _len, _size, RTE_CACHE_LINE_SIZE)
161 #define ECORE_FREE(_s, _buf, _size) \
164 #define SC_ILT(sc) ((sc)->ilt)
165 #define ILOG2(x) bnx2x_ilog2(x)
167 #define ECORE_ILT_ZALLOC(x, y, size, str) \
169 x = rte_malloc("", sizeof(struct bnx2x_dma), RTE_CACHE_LINE_SIZE); \
171 if (bnx2x_dma_alloc((struct bnx2x_softc *)sc, \
172 size, (struct bnx2x_dma *)x, \
173 str, RTE_CACHE_LINE_SIZE) != 0) { \
178 *y = ((struct bnx2x_dma *)x)->paddr; \
183 #define ECORE_ILT_FREE(x, y, size) \
192 #define ECORE_IS_VALID_ETHER_ADDR(_mac) TRUE
194 #define ECORE_IS_MF_SD_MODE IS_MF_SD_MODE
195 #define ECORE_IS_MF_SI_MODE IS_MF_SI_MODE
196 #define ECORE_IS_MF_AFEX_MODE IS_MF_AFEX_MODE
198 #define ECORE_SET_CTX_VALIDATION bnx2x_set_ctx_validation
200 #define ECORE_UPDATE_COALESCE_SB_INDEX bnx2x_update_coalesce_sb_index
202 #define ECORE_ALIGN(x, a) ((((x) + (a) - 1) / (a)) * (a))
204 #define ECORE_REG_WR_DMAE_LEN REG_WR_DMAE_LEN
206 #define ECORE_PATH_ID SC_PATH
207 #define ECORE_PORT_ID SC_PORT
208 #define ECORE_FUNC_ID SC_FUNC
209 #define ECORE_ABS_FUNC_ID SC_ABS_FUNC
211 #define CRCPOLY_LE 0xedb88320
212 uint32_t ecore_calc_crc32(uint32_t crc, uint8_t const *p,
213 uint32_t len, uint32_t magic);
215 uint8_t ecore_calc_crc8(uint32_t data, uint8_t crc);
218 static inline uint32_t
219 ECORE_CRC32_LE(uint32_t seed, uint8_t *mac, uint32_t len)
221 return ecore_calc_crc32(seed, mac, len, CRCPOLY_LE);
224 #define ecore_sp_post(_sc, _a, _b, _c, _d) \
225 bnx2x_sp_post(_sc, _a, _b, U64_HI(_c), U64_LO(_c), _d)
227 #define ECORE_DBG_BREAK_IF(exp) \
229 if (unlikely(exp)) { \
230 rte_panic("ECORE"); \
234 #define ECORE_BUG() \
236 rte_panic("BUG (%s:%d)", __FILE__, __LINE__); \
239 #define ECORE_BUG_ON(exp) \
242 rte_panic("BUG_ON (%s:%d)", __FILE__, __LINE__); \
247 #define ECORE_MSG(m, ...) \
248 PMD_DRV_LOG(DEBUG, m, ##__VA_ARGS__)
250 typedef struct _ecore_list_entry_t
252 struct _ecore_list_entry_t *next, *prev;
253 } ecore_list_entry_t;
255 typedef struct ecore_list_t
257 ecore_list_entry_t *head, *tail;
261 /* initialize the list */
262 #define ECORE_LIST_INIT(_list) \
264 (_list)->head = NULL; \
265 (_list)->tail = NULL; \
269 /* return TRUE if the element is the last on the list */
270 #define ECORE_LIST_IS_LAST(_elem, _list) \
271 (_elem == (_list)->tail)
273 /* return TRUE if the list is empty */
274 #define ECORE_LIST_IS_EMPTY(_list) \
277 /* return the first element */
278 #define ECORE_LIST_FIRST_ENTRY(_list, cast, _link) \
279 (cast *)((_list)->head)
281 /* return the next element */
282 #define ECORE_LIST_NEXT(_elem, _link, cast) \
283 (cast *)((&((_elem)->_link))->next)
285 /* push an element on the head of the list */
286 #define ECORE_LIST_PUSH_HEAD(_elem, _list) \
288 (_elem)->prev = (ecore_list_entry_t *)0; \
289 (_elem)->next = (_list)->head; \
290 if ((_list)->tail == (ecore_list_entry_t *)0) { \
291 (_list)->tail = (_elem); \
293 (_list)->head->prev = (_elem); \
295 (_list)->head = (_elem); \
299 /* push an element on the tail of the list */
300 #define ECORE_LIST_PUSH_TAIL(_elem, _list) \
302 (_elem)->next = (ecore_list_entry_t *)0; \
303 (_elem)->prev = (_list)->tail; \
304 if ((_list)->tail) { \
305 (_list)->tail->next = (_elem); \
307 (_list)->head = (_elem); \
309 (_list)->tail = (_elem); \
313 /* push list1 on the head of list2 and return with list1 as empty */
314 #define ECORE_LIST_SPLICE_INIT(_list1, _list2) \
316 (_list1)->tail->next = (_list2)->head; \
317 if ((_list2)->head) { \
318 (_list2)->head->prev = (_list1)->tail; \
320 (_list2)->tail = (_list1)->tail; \
322 (_list2)->head = (_list1)->head; \
323 (_list2)->cnt += (_list1)->cnt; \
324 (_list1)->head = NULL; \
325 (_list1)->tail = NULL; \
329 /* remove an element from the list */
330 #define ECORE_LIST_REMOVE_ENTRY(_elem, _list) \
332 if ((_list)->head == (_elem)) { \
333 if ((_list)->head) { \
334 (_list)->head = (_list)->head->next; \
335 if ((_list)->head) { \
336 (_list)->head->prev = (ecore_list_entry_t *)0; \
338 (_list)->tail = (ecore_list_entry_t *)0; \
342 } else if ((_list)->tail == (_elem)) { \
343 if ((_list)->tail) { \
344 (_list)->tail = (_list)->tail->prev; \
345 if ((_list)->tail) { \
346 (_list)->tail->next = (ecore_list_entry_t *)0; \
348 (_list)->head = (ecore_list_entry_t *)0; \
353 (_elem)->prev->next = (_elem)->next; \
354 (_elem)->next->prev = (_elem)->prev; \
360 #define ECORE_LIST_FOR_EACH_ENTRY(pos, _list, _link, cast) \
361 for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _link); \
363 pos = ECORE_LIST_NEXT(pos, _link, cast))
365 /* walk the list (safely) */
366 #define ECORE_LIST_FOR_EACH_ENTRY_SAFE(pos, n, _list, _link, cast) \
367 for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _lint), \
368 n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL; \
371 n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL)
374 /* Manipulate a bit vector defined as an array of uint64_t */
376 /* Number of bits in one sge_mask array element */
377 #define BIT_VEC64_ELEM_SZ 64
378 #define BIT_VEC64_ELEM_SHIFT 6
379 #define BIT_VEC64_ELEM_MASK ((uint64_t)BIT_VEC64_ELEM_SZ - 1)
381 #define __BIT_VEC64_SET_BIT(el, bit) \
383 el = ((el) | ((uint64_t)0x1 << (bit))); \
386 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
388 el = ((el) & (~((uint64_t)0x1 << (bit)))); \
391 #define BIT_VEC64_SET_BIT(vec64, idx) \
392 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
393 (idx) & BIT_VEC64_ELEM_MASK)
395 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
396 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
397 (idx) & BIT_VEC64_ELEM_MASK)
399 #define BIT_VEC64_TEST_BIT(vec64, idx) \
400 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
401 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
404 * Creates a bitmask of all ones in less significant bits.
405 * idx - index of the most significant bit in the created mask
407 #define BIT_VEC64_ONES_MASK(idx) \
408 (((uint64_t)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
409 #define BIT_VEC64_ELEM_ONE_MASK ((uint64_t)(~0))
411 /* fill in a MAC address the way the FW likes it */
413 ecore_set_fw_mac_addr(uint16_t *fw_hi,
418 ((uint8_t *)fw_hi)[0] = mac[1];
419 ((uint8_t *)fw_hi)[1] = mac[0];
420 ((uint8_t *)fw_mid)[0] = mac[3];
421 ((uint8_t *)fw_mid)[1] = mac[2];
422 ((uint8_t *)fw_lo)[0] = mac[5];
423 ((uint8_t *)fw_lo)[1] = mac[4];
427 enum ecore_status_t {
435 /* PENDING is not an error and should be positive */
450 /* Bits representing general command's configuration */
454 /* Wait until all pending commands complete */
456 /* Don't send a ramrod, only update a registry */
458 /* Configure HW according to the current object state */
460 /* Execute the next command now */
462 /* Don't add a new command and continue execution of posponed
463 * commands. If not set a new command will be added to the
464 * pending commands list.
467 /* If there is another pending ramrod, wait until it finishes and
468 * re-try to submit this one. This flag can be set only in sleepable
469 * context, and should not be set from the context that completes the
470 * ramrods as deadlock will occur.
478 ECORE_OBJ_TYPE_RX_TX,
481 /* Public slow path states */
483 ECORE_FILTER_MAC_PENDING,
484 ECORE_FILTER_VLAN_PENDING,
485 ECORE_FILTER_VLAN_MAC_PENDING,
486 ECORE_FILTER_RX_MODE_PENDING,
487 ECORE_FILTER_RX_MODE_SCHED,
488 ECORE_FILTER_ISCSI_ETH_START_SCHED,
489 ECORE_FILTER_ISCSI_ETH_STOP_SCHED,
490 ECORE_FILTER_FCOE_ETH_START_SCHED,
491 ECORE_FILTER_FCOE_ETH_STOP_SCHED,
492 ECORE_FILTER_MCAST_PENDING,
493 ECORE_FILTER_MCAST_SCHED,
494 ECORE_FILTER_RSS_CONF_PENDING,
495 ECORE_AFEX_FCOE_Q_UPDATE_PENDING,
496 ECORE_AFEX_PENDING_VIFSET_MCP_ACK
499 struct ecore_raw_obj {
506 /* Ramrod data buffer params */
508 ecore_dma_addr_t rdata_mapping;
510 /* Ramrod state params */
511 int state; /* "ramrod is pending" state bit */
512 unsigned long *pstate; /* pointer to state buffer */
514 ecore_obj_type obj_type;
516 int (*wait_comp)(struct bnx2x_softc *sc,
517 struct ecore_raw_obj *o);
519 int (*check_pending)(struct ecore_raw_obj *o);
520 void (*clear_pending)(struct ecore_raw_obj *o);
521 void (*set_pending)(struct ecore_raw_obj *o);
524 /************************* VLAN-MAC commands related parameters ***************/
525 struct ecore_mac_ramrod_data {
526 uint8_t mac[ETH_ALEN];
527 uint8_t is_inner_mac;
530 struct ecore_vlan_ramrod_data {
534 struct ecore_vlan_mac_ramrod_data {
535 uint8_t mac[ETH_ALEN];
536 uint8_t is_inner_mac;
540 union ecore_classification_ramrod_data {
541 struct ecore_mac_ramrod_data mac;
542 struct ecore_vlan_ramrod_data vlan;
543 struct ecore_vlan_mac_ramrod_data vlan_mac;
546 /* VLAN_MAC commands */
547 enum ecore_vlan_mac_cmd {
553 struct ecore_vlan_mac_data {
554 /* Requested command: ECORE_VLAN_MAC_XX */
555 enum ecore_vlan_mac_cmd cmd;
556 /* used to contain the data related vlan_mac_flags bits from
559 unsigned long vlan_mac_flags;
561 /* Needed for MOVE command */
562 struct ecore_vlan_mac_obj *target_obj;
564 union ecore_classification_ramrod_data u;
567 /*************************** Exe Queue obj ************************************/
568 union ecore_exe_queue_cmd_data {
569 struct ecore_vlan_mac_data vlan_mac;
575 struct ecore_exeq_elem {
576 ecore_list_entry_t link;
578 /* Length of this element in the exe_chunk. */
581 union ecore_exe_queue_cmd_data cmd_data;
584 union ecore_qable_obj;
586 union ecore_exeq_comp_elem {
587 union event_ring_elem *elem;
590 struct ecore_exe_queue_obj;
592 typedef int (*exe_q_validate)(struct bnx2x_softc *sc,
593 union ecore_qable_obj *o,
594 struct ecore_exeq_elem *elem);
596 typedef int (*exe_q_remove)(struct bnx2x_softc *sc,
597 union ecore_qable_obj *o,
598 struct ecore_exeq_elem *elem);
600 /* Return positive if entry was optimized, 0 - if not, negative
601 * in case of an error.
603 typedef int (*exe_q_optimize)(struct bnx2x_softc *sc,
604 union ecore_qable_obj *o,
605 struct ecore_exeq_elem *elem);
606 typedef int (*exe_q_execute)(struct bnx2x_softc *sc,
607 union ecore_qable_obj *o,
608 ecore_list_t *exe_chunk,
609 unsigned long *ramrod_flags);
610 typedef struct ecore_exeq_elem *
611 (*exe_q_get)(struct ecore_exe_queue_obj *o,
612 struct ecore_exeq_elem *elem);
614 struct ecore_exe_queue_obj {
615 /* Commands pending for an execution. */
616 ecore_list_t exe_queue;
618 /* Commands pending for an completion. */
619 ecore_list_t pending_comp;
621 ECORE_MUTEX_SPIN lock;
623 /* Maximum length of commands' list for one execution */
626 union ecore_qable_obj *owner;
628 /****** Virtual functions ******/
630 * Called before commands execution for commands that are really
631 * going to be executed (after 'optimize').
633 * Must run under exe_queue->lock
635 exe_q_validate validate;
638 * Called before removing pending commands, cleaning allocated
639 * resources (e.g., credits from validate)
644 * This will try to cancel the current pending commands list
645 * considering the new command.
647 * Returns the number of optimized commands or a negative error code
649 * Must run under exe_queue->lock
651 exe_q_optimize optimize;
654 * Run the next commands chunk (owner specific).
656 exe_q_execute execute;
659 * Return the exe_queue element containing the specific command
660 * if any. Otherwise return NULL.
664 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/
666 * Element in the VLAN_MAC registry list having all current configured
669 struct ecore_vlan_mac_registry_elem {
670 ecore_list_entry_t link;
672 /* Used to store the cam offset used for the mac/vlan/vlan-mac.
673 * Relevant for 57711 only. VLANs and MACs share the
674 * same CAM for these chips.
678 /* Needed for DEL and RESTORE flows */
679 unsigned long vlan_mac_flags;
681 union ecore_classification_ramrod_data u;
684 /* Bits representing VLAN_MAC commands specific flags */
690 ECORE_DONT_CONSUME_CAM_CREDIT,
691 ECORE_DONT_CONSUME_CAM_CREDIT_DEST,
694 struct ecore_vlan_mac_ramrod_params {
695 /* Object to run the command from */
696 struct ecore_vlan_mac_obj *vlan_mac_obj;
698 /* General command flags: COMP_WAIT, etc. */
699 unsigned long ramrod_flags;
701 /* Command specific configuration request */
702 struct ecore_vlan_mac_data user_req;
705 struct ecore_vlan_mac_obj {
706 struct ecore_raw_obj raw;
708 /* Bookkeeping list: will prevent the addition of already existing
712 /* Implement a simple reader/writer lock on the head list.
713 * all these fields should only be accessed under the exe_queue lock
715 uint8_t head_reader; /* Num. of readers accessing head list */
716 int head_exe_request; /* Pending execution request. */
717 unsigned long saved_ramrod_flags; /* Ramrods of pending execution */
719 /* Execution queue interface instance */
720 struct ecore_exe_queue_obj exe_queue;
722 /* MACs credit pool */
723 struct ecore_credit_pool_obj *macs_pool;
725 /* VLANs credit pool */
726 struct ecore_credit_pool_obj *vlans_pool;
728 /* RAMROD command to be used */
731 /* copy first n elements onto preallocated buffer
733 * @param n number of elements to get
734 * @param buf buffer preallocated by caller into which elements
735 * will be copied. Note elements are 4-byte aligned
736 * so buffer size must be able to accommodate the
739 * @return number of copied bytes
742 int (*get_n_elements)(struct bnx2x_softc *sc,
743 struct ecore_vlan_mac_obj *o, int n, uint8_t *base,
744 uint8_t stride, uint8_t size);
747 * Checks if ADD-ramrod with the given params may be performed.
749 * @return zero if the element may be added
752 int (*check_add)(struct bnx2x_softc *sc,
753 struct ecore_vlan_mac_obj *o,
754 union ecore_classification_ramrod_data *data);
757 * Checks if DEL-ramrod with the given params may be performed.
759 * @return TRUE if the element may be deleted
761 struct ecore_vlan_mac_registry_elem *
762 (*check_del)(struct bnx2x_softc *sc,
763 struct ecore_vlan_mac_obj *o,
764 union ecore_classification_ramrod_data *data);
767 * Checks if DEL-ramrod with the given params may be performed.
769 * @return TRUE if the element may be deleted
771 int (*check_move)(struct bnx2x_softc *sc,
772 struct ecore_vlan_mac_obj *src_o,
773 struct ecore_vlan_mac_obj *dst_o,
774 union ecore_classification_ramrod_data *data);
777 * Update the relevant credit object(s) (consume/return
780 int (*get_credit)(struct ecore_vlan_mac_obj *o);
781 int (*put_credit)(struct ecore_vlan_mac_obj *o);
782 int (*get_cam_offset)(struct ecore_vlan_mac_obj *o, int *offset);
783 int (*put_cam_offset)(struct ecore_vlan_mac_obj *o, int offset);
786 * Configures one rule in the ramrod data buffer.
788 void (*set_one_rule)(struct bnx2x_softc *sc,
789 struct ecore_vlan_mac_obj *o,
790 struct ecore_exeq_elem *elem, int rule_idx,
794 * Delete all configured elements having the given
795 * vlan_mac_flags specification. Assumes no pending for
796 * execution commands. Will schedule all all currently
797 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags
798 * specification for deletion and will use the given
799 * ramrod_flags for the last DEL operation.
803 * @param ramrod_flags RAMROD_XX flags
805 * @return 0 if the last operation has completed successfully
806 * and there are no more elements left, positive value
807 * if there are pending for completion commands,
808 * negative value in case of failure.
810 int (*delete_all)(struct bnx2x_softc *sc,
811 struct ecore_vlan_mac_obj *o,
812 unsigned long *vlan_mac_flags,
813 unsigned long *ramrod_flags);
816 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously
817 * configured elements list.
820 * @param p Command parameters (RAMROD_COMP_WAIT bit in
821 * ramrod_flags is only taken into an account)
822 * @param ppos a pointer to the cookie that should be given back in the
823 * next call to make function handle the next element. If
824 * *ppos is set to NULL it will restart the iterator.
825 * If returned *ppos == NULL this means that the last
826 * element has been handled.
830 int (*restore)(struct bnx2x_softc *sc,
831 struct ecore_vlan_mac_ramrod_params *p,
832 struct ecore_vlan_mac_registry_elem **ppos);
835 * Should be called on a completion arrival.
839 * @param cqe Completion element we are handling
840 * @param ramrod_flags if RAMROD_CONT is set the next bulk of
841 * pending commands will be executed.
842 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE
843 * may also be set if needed.
845 * @return 0 if there are neither pending nor waiting for
846 * completion commands. Positive value if there are
847 * pending for execution or for completion commands.
848 * Negative value in case of an error (including an
851 int (*complete)(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *o,
852 union event_ring_elem *cqe,
853 unsigned long *ramrod_flags);
856 * Wait for completion of all commands. Don't schedule new ones,
857 * just wait. It assumes that the completion code will schedule
860 int (*wait)(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *o);
864 ECORE_LLH_CAM_ISCSI_ETH_LINE = 0,
865 ECORE_LLH_CAM_ETH_LINE,
866 ECORE_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2
869 /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */
871 /* RX_MODE ramrod special flags: set in rx_mode_flags field in
872 * a ecore_rx_mode_ramrod_params.
875 ECORE_RX_MODE_FCOE_ETH,
876 ECORE_RX_MODE_ISCSI_ETH,
880 ECORE_ACCEPT_UNICAST,
881 ECORE_ACCEPT_MULTICAST,
882 ECORE_ACCEPT_ALL_UNICAST,
883 ECORE_ACCEPT_ALL_MULTICAST,
884 ECORE_ACCEPT_BROADCAST,
885 ECORE_ACCEPT_UNMATCHED,
886 ECORE_ACCEPT_ANY_VLAN
889 struct ecore_rx_mode_ramrod_params {
890 struct ecore_rx_mode_obj *rx_mode_obj;
891 unsigned long *pstate;
896 unsigned long ramrod_flags;
897 unsigned long rx_mode_flags;
899 /* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to
900 * a tstorm_eth_mac_filter_config (e1x).
903 ecore_dma_addr_t rdata_mapping;
905 /* Rx mode settings */
906 unsigned long rx_accept_flags;
908 /* internal switching settings */
909 unsigned long tx_accept_flags;
912 struct ecore_rx_mode_obj {
913 int (*config_rx_mode)(struct bnx2x_softc *sc,
914 struct ecore_rx_mode_ramrod_params *p);
916 int (*wait_comp)(struct bnx2x_softc *sc,
917 struct ecore_rx_mode_ramrod_params *p);
920 /********************** Set multicast group ***********************************/
922 struct ecore_mcast_list_elem {
923 ecore_list_entry_t link;
927 union ecore_mcast_config_data {
929 uint8_t bin; /* used in a RESTORE flow */
932 struct ecore_mcast_ramrod_params {
933 struct ecore_mcast_obj *mcast_obj;
935 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */
936 unsigned long ramrod_flags;
938 ecore_list_t mcast_list; /* list of struct ecore_mcast_list_elem */
942 enum ecore_mcast_cmd {
944 ECORE_MCAST_CMD_CONT,
946 ECORE_MCAST_CMD_RESTORE,
949 struct ecore_mcast_obj {
950 struct ecore_raw_obj raw;
954 #define ECORE_MCAST_BINS_NUM 256
955 #define ECORE_MCAST_VEC_SZ (ECORE_MCAST_BINS_NUM / 64)
956 uint64_t vec[ECORE_MCAST_VEC_SZ];
958 /** Number of BINs to clear. Should be updated
959 * immediately when a command arrives in order to
960 * properly create DEL commands.
971 /* Pending commands */
972 ecore_list_t pending_cmds_head;
974 /* A state that is set in raw.pstate, when there are pending commands */
977 /* Maximal number of mcast MACs configured in one command */
980 /* Total number of currently pending MACs to configure: both
981 * in the pending commands list and in the current command.
983 int total_pending_num;
988 * @param cmd command to execute (ECORE_MCAST_CMD_X, see above)
990 int (*config_mcast)(struct bnx2x_softc *sc,
991 struct ecore_mcast_ramrod_params *p,
992 enum ecore_mcast_cmd cmd);
995 * Fills the ramrod data during the RESTORE flow.
999 * @param start_idx Registry index to start from
1000 * @param rdata_idx Index in the ramrod data to start from
1002 * @return -1 if we handled the whole registry or index of the last
1003 * handled registry element.
1005 int (*hdl_restore)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o,
1006 int start_bin, int *rdata_idx);
1008 int (*enqueue_cmd)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o,
1009 struct ecore_mcast_ramrod_params *p,
1010 enum ecore_mcast_cmd cmd);
1012 void (*set_one_rule)(struct bnx2x_softc *sc,
1013 struct ecore_mcast_obj *o, int idx,
1014 union ecore_mcast_config_data *cfg_data,
1015 enum ecore_mcast_cmd cmd);
1017 /** Checks if there are more mcast MACs to be set or a previous
1018 * command is still pending.
1020 int (*check_pending)(struct ecore_mcast_obj *o);
1023 * Set/Clear/Check SCHEDULED state of the object
1025 void (*set_sched)(struct ecore_mcast_obj *o);
1026 void (*clear_sched)(struct ecore_mcast_obj *o);
1027 int (*check_sched)(struct ecore_mcast_obj *o);
1029 /* Wait until all pending commands complete */
1030 int (*wait_comp)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o);
1033 * Handle the internal object counters needed for proper
1034 * commands handling. Checks that the provided parameters are
1037 int (*validate)(struct bnx2x_softc *sc,
1038 struct ecore_mcast_ramrod_params *p,
1039 enum ecore_mcast_cmd cmd);
1042 * Restore the values of internal counters in case of a failure.
1044 void (*revert)(struct bnx2x_softc *sc,
1045 struct ecore_mcast_ramrod_params *p,
1048 int (*get_registry_size)(struct ecore_mcast_obj *o);
1049 void (*set_registry_size)(struct ecore_mcast_obj *o, int n);
1052 /*************************** Credit handling **********************************/
1053 struct ecore_credit_pool_obj {
1055 /* Current amount of credit in the pool */
1056 ecore_atomic_t credit;
1058 /* Maximum allowed credit. put() will check against it. */
1061 /* Allocate a pool table statically.
1063 * Currently the maximum allowed size is MAX_MAC_CREDIT_E2(272)
1065 * The set bit in the table will mean that the entry is available.
1067 #define ECORE_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64)
1068 uint64_t pool_mirror[ECORE_POOL_VEC_SIZE];
1070 /* Base pool offset (initialized differently */
1071 int base_pool_offset;
1074 * Get the next free pool entry.
1076 * @return TRUE if there was a free entry in the pool
1078 int (*get_entry)(struct ecore_credit_pool_obj *o, int *entry);
1081 * Return the entry back to the pool.
1083 * @return TRUE if entry is legal and has been successfully
1084 * returned to the pool.
1086 int (*put_entry)(struct ecore_credit_pool_obj *o, int entry);
1089 * Get the requested amount of credit from the pool.
1091 * @param cnt Amount of requested credit
1092 * @return TRUE if the operation is successful
1094 int (*get)(struct ecore_credit_pool_obj *o, int cnt);
1097 * Returns the credit to the pool.
1099 * @param cnt Amount of credit to return
1100 * @return TRUE if the operation is successful
1102 int (*put)(struct ecore_credit_pool_obj *o, int cnt);
1105 * Reads the current amount of credit.
1107 int (*check)(struct ecore_credit_pool_obj *o);
1110 /*************************** RSS configuration ********************************/
1112 /* RSS_MODE bits are mutually exclusive */
1113 ECORE_RSS_MODE_DISABLED,
1114 ECORE_RSS_MODE_REGULAR,
1116 ECORE_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */
1125 ECORE_RSS_TUNNELING,
1128 struct ecore_config_rss_params {
1129 struct ecore_rss_config_obj *rss_obj;
1131 /* may have RAMROD_COMP_WAIT set only */
1132 unsigned long ramrod_flags;
1134 /* ECORE_RSS_X bits */
1135 unsigned long rss_flags;
1137 /* Number hash bits to take into an account */
1138 uint8_t rss_result_mask;
1140 /* Indirection table */
1141 uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
1143 /* RSS hash values */
1144 uint32_t rss_key[10];
1146 /* valid only iff ECORE_RSS_UPDATE_TOE is set */
1147 uint16_t toe_rss_bitmap;
1149 /* valid iff ECORE_RSS_TUNNELING is set */
1150 uint16_t tunnel_value;
1151 uint16_t tunnel_mask;
1154 struct ecore_rss_config_obj {
1155 struct ecore_raw_obj raw;
1157 /* RSS engine to use */
1160 /* Last configured indirection table */
1161 uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
1163 /* flags for enabling 4-tupple hash on UDP */
1167 int (*config_rss)(struct bnx2x_softc *sc,
1168 struct ecore_config_rss_params *p);
1171 /*********************** Queue state update ***********************************/
1173 /* UPDATE command options */
1175 ECORE_Q_UPDATE_IN_VLAN_REM,
1176 ECORE_Q_UPDATE_IN_VLAN_REM_CHNG,
1177 ECORE_Q_UPDATE_OUT_VLAN_REM,
1178 ECORE_Q_UPDATE_OUT_VLAN_REM_CHNG,
1179 ECORE_Q_UPDATE_ANTI_SPOOF,
1180 ECORE_Q_UPDATE_ANTI_SPOOF_CHNG,
1181 ECORE_Q_UPDATE_ACTIVATE,
1182 ECORE_Q_UPDATE_ACTIVATE_CHNG,
1183 ECORE_Q_UPDATE_DEF_VLAN_EN,
1184 ECORE_Q_UPDATE_DEF_VLAN_EN_CHNG,
1185 ECORE_Q_UPDATE_SILENT_VLAN_REM_CHNG,
1186 ECORE_Q_UPDATE_SILENT_VLAN_REM,
1187 ECORE_Q_UPDATE_TX_SWITCHING_CHNG,
1188 ECORE_Q_UPDATE_TX_SWITCHING,
1191 /* Allowed Queue states */
1192 enum ecore_q_state {
1193 ECORE_Q_STATE_RESET,
1194 ECORE_Q_STATE_INITIALIZED,
1195 ECORE_Q_STATE_ACTIVE,
1196 ECORE_Q_STATE_MULTI_COS,
1197 ECORE_Q_STATE_MCOS_TERMINATED,
1198 ECORE_Q_STATE_INACTIVE,
1199 ECORE_Q_STATE_STOPPED,
1200 ECORE_Q_STATE_TERMINATED,
1201 ECORE_Q_STATE_FLRED,
1205 /* Allowed Queue states */
1206 enum ecore_q_logical_state {
1207 ECORE_Q_LOGICAL_STATE_ACTIVE,
1208 ECORE_Q_LOGICAL_STATE_STOPPED,
1211 /* Allowed commands */
1212 enum ecore_queue_cmd {
1215 ECORE_Q_CMD_SETUP_TX_ONLY,
1216 ECORE_Q_CMD_DEACTIVATE,
1217 ECORE_Q_CMD_ACTIVATE,
1219 ECORE_Q_CMD_UPDATE_TPA,
1221 ECORE_Q_CMD_CFC_DEL,
1222 ECORE_Q_CMD_TERMINATE,
1227 /* queue SETUP + INIT flags */
1230 ECORE_Q_FLG_TPA_IPV6,
1231 ECORE_Q_FLG_TPA_GRO,
1233 ECORE_Q_FLG_ZERO_STATS,
1243 ECORE_Q_FLG_LEADING_RSS,
1245 ECORE_Q_FLG_DEF_VLAN,
1246 ECORE_Q_FLG_TX_SWITCH,
1248 ECORE_Q_FLG_ANTI_SPOOF,
1249 ECORE_Q_FLG_SILENT_VLAN_REM,
1250 ECORE_Q_FLG_FORCE_DEFAULT_PRI,
1251 ECORE_Q_FLG_REFUSE_OUTBAND_VLAN,
1252 ECORE_Q_FLG_PCSUM_ON_PKT,
1253 ECORE_Q_FLG_TUN_INC_INNER_IP_ID
1256 /* Queue type options: queue type may be a combination of below. */
1259 ECORE_Q_TYPE_HAS_RX,
1260 ECORE_Q_TYPE_HAS_TX,
1263 #define ECORE_PRIMARY_CID_INDEX 0
1264 #define ECORE_MULTI_TX_COS_E1X 3 /* QM only */
1265 #define ECORE_MULTI_TX_COS_E2_E3A0 2
1266 #define ECORE_MULTI_TX_COS_E3B0 3
1267 #define ECORE_MULTI_TX_COS 3 /* Maximum possible */
1268 #define MAC_PAD (ECORE_ALIGN(ETH_ALEN, sizeof(uint32_t)) - ETH_ALEN)
1270 struct ecore_queue_init_params {
1272 unsigned long flags;
1275 uint8_t sb_cq_index;
1279 unsigned long flags;
1282 uint8_t sb_cq_index;
1285 /* CID context in the host memory */
1286 struct eth_context *cxts[ECORE_MULTI_TX_COS];
1288 /* maximum number of cos supported by hardware */
1292 struct ecore_queue_terminate_params {
1293 /* index within the tx_only cids of this queue object */
1297 struct ecore_queue_cfc_del_params {
1298 /* index within the tx_only cids of this queue object */
1302 struct ecore_queue_update_params {
1303 unsigned long update_flags; /* ECORE_Q_UPDATE_XX bits */
1305 uint16_t silent_removal_value;
1306 uint16_t silent_removal_mask;
1307 /* index within the tx_only cids of this queue object */
1311 struct rxq_pause_params {
1316 uint16_t sge_th_lo; /* valid iff ECORE_Q_FLG_TPA */
1317 uint16_t sge_th_hi; /* valid iff ECORE_Q_FLG_TPA */
1322 struct ecore_general_setup_params {
1323 /* valid iff ECORE_Q_FLG_STATS */
1331 struct ecore_rxq_setup_params {
1333 ecore_dma_addr_t dscr_map;
1334 ecore_dma_addr_t rcq_map;
1335 ecore_dma_addr_t rcq_np_map;
1337 uint16_t drop_flags;
1340 uint8_t cl_qzone_id;
1342 /* valid iff ECORE_Q_FLG_TPA */
1343 uint16_t tpa_agg_sz;
1344 uint8_t max_tpa_queues;
1345 uint8_t rss_engine_id;
1347 /* valid iff ECORE_Q_FLG_MCAST */
1348 uint8_t mcast_engine_id;
1350 uint8_t cache_line_log;
1352 uint8_t sb_cq_index;
1354 /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */
1355 uint16_t silent_removal_value;
1356 uint16_t silent_removal_mask;
1359 struct ecore_txq_setup_params {
1361 ecore_dma_addr_t dscr_map;
1364 uint8_t sb_cq_index;
1365 uint8_t cos; /* valid iff ECORE_Q_FLG_COS */
1366 uint16_t traffic_type;
1367 /* equals to the leading rss client id, used for TX classification*/
1368 uint8_t tss_leading_cl_id;
1370 /* valid iff ECORE_Q_FLG_DEF_VLAN */
1371 uint16_t default_vlan;
1374 struct ecore_queue_setup_params {
1375 struct ecore_general_setup_params gen_params;
1376 struct ecore_txq_setup_params txq_params;
1377 struct ecore_rxq_setup_params rxq_params;
1378 struct rxq_pause_params pause_params;
1379 unsigned long flags;
1382 struct ecore_queue_setup_tx_only_params {
1383 struct ecore_general_setup_params gen_params;
1384 struct ecore_txq_setup_params txq_params;
1385 unsigned long flags;
1386 /* index within the tx_only cids of this queue object */
1390 struct ecore_queue_state_params {
1391 struct ecore_queue_sp_obj *q_obj;
1393 /* Current command */
1394 enum ecore_queue_cmd cmd;
1396 /* may have RAMROD_COMP_WAIT set only */
1397 unsigned long ramrod_flags;
1399 /* Params according to the current command */
1401 struct ecore_queue_update_params update;
1402 struct ecore_queue_setup_params setup;
1403 struct ecore_queue_init_params init;
1404 struct ecore_queue_setup_tx_only_params tx_only;
1405 struct ecore_queue_terminate_params terminate;
1406 struct ecore_queue_cfc_del_params cfc_del;
1410 struct ecore_viflist_params {
1412 uint8_t func_bit_map_res;
1415 struct ecore_queue_sp_obj {
1416 uint32_t cids[ECORE_MULTI_TX_COS];
1420 /* number of traffic classes supported by queue.
1421 * The primary connection of the queue supports the first traffic
1422 * class. Any further traffic class is supported by a tx-only
1425 * Therefore max_cos is also a number of valid entries in the cids
1429 uint8_t num_tx_only, next_tx_only;
1431 enum ecore_q_state state, next_state;
1433 /* bits from enum ecore_q_type */
1436 /* ECORE_Q_CMD_XX bits. This object implements "one
1437 * pending" paradigm but for debug and tracing purposes it's
1438 * more convenient to have different bits for different
1441 unsigned long pending;
1443 /* Buffer to use as a ramrod data and its mapping */
1445 ecore_dma_addr_t rdata_mapping;
1448 * Performs one state change according to the given parameters.
1450 * @return 0 in case of success and negative value otherwise.
1452 int (*send_cmd)(struct bnx2x_softc *sc,
1453 struct ecore_queue_state_params *params);
1456 * Sets the pending bit according to the requested transition.
1458 int (*set_pending)(struct ecore_queue_sp_obj *o,
1459 struct ecore_queue_state_params *params);
1462 * Checks that the requested state transition is legal.
1464 int (*check_transition)(struct bnx2x_softc *sc,
1465 struct ecore_queue_sp_obj *o,
1466 struct ecore_queue_state_params *params);
1469 * Completes the pending command.
1471 int (*complete_cmd)(struct bnx2x_softc *sc,
1472 struct ecore_queue_sp_obj *o,
1473 enum ecore_queue_cmd);
1475 int (*wait_comp)(struct bnx2x_softc *sc,
1476 struct ecore_queue_sp_obj *o,
1477 enum ecore_queue_cmd cmd);
1480 /********************** Function state update *********************************/
1481 /* Allowed Function states */
1482 enum ecore_func_state {
1483 ECORE_F_STATE_RESET,
1484 ECORE_F_STATE_INITIALIZED,
1485 ECORE_F_STATE_STARTED,
1486 ECORE_F_STATE_TX_STOPPED,
1490 /* Allowed Function commands */
1491 enum ecore_func_cmd {
1492 ECORE_F_CMD_HW_INIT,
1495 ECORE_F_CMD_HW_RESET,
1496 ECORE_F_CMD_AFEX_UPDATE,
1497 ECORE_F_CMD_AFEX_VIFLISTS,
1498 ECORE_F_CMD_TX_STOP,
1499 ECORE_F_CMD_TX_START,
1500 ECORE_F_CMD_SWITCH_UPDATE,
1504 struct ecore_func_hw_init_params {
1505 /* A load phase returned by MCP.
1508 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
1509 * FW_MSG_CODE_DRV_LOAD_COMMON
1510 * FW_MSG_CODE_DRV_LOAD_PORT
1511 * FW_MSG_CODE_DRV_LOAD_FUNCTION
1513 uint32_t load_phase;
1516 struct ecore_func_hw_reset_params {
1517 /* A load phase returned by MCP.
1520 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
1521 * FW_MSG_CODE_DRV_LOAD_COMMON
1522 * FW_MSG_CODE_DRV_LOAD_PORT
1523 * FW_MSG_CODE_DRV_LOAD_FUNCTION
1525 uint32_t reset_phase;
1528 struct ecore_func_start_params {
1529 /* Multi Function mode:
1531 * - Switch Dependent
1532 * - Switch Independent
1536 /* Switch Dependent mode outer VLAN tag */
1537 uint16_t sd_vlan_tag;
1539 /* Function cos mode */
1540 uint8_t network_cos_mode;
1542 /* NVGRE classification enablement */
1543 uint8_t nvgre_clss_en;
1545 /* NO_GRE_TUNNEL/NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */
1546 uint8_t gre_tunnel_mode;
1548 /* GRE_OUTER_HEADERS_RSS/GRE_INNER_HEADERS_RSS/NVGRE_KEY_ENTROPY_RSS */
1549 uint8_t gre_tunnel_rss;
1553 struct ecore_func_switch_update_params {
1557 struct ecore_func_afex_update_params {
1559 uint16_t afex_default_vlan;
1560 uint8_t allowed_priorities;
1563 struct ecore_func_afex_viflists_params {
1564 uint16_t vif_list_index;
1565 uint8_t func_bit_map;
1566 uint8_t afex_vif_list_command;
1567 uint8_t func_to_clear;
1569 struct ecore_func_tx_start_params {
1570 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
1571 uint8_t dcb_enabled;
1572 uint8_t dcb_version;
1573 uint8_t dont_add_pri_0;
1576 struct ecore_func_state_params {
1577 struct ecore_func_sp_obj *f_obj;
1579 /* Current command */
1580 enum ecore_func_cmd cmd;
1582 /* may have RAMROD_COMP_WAIT set only */
1583 unsigned long ramrod_flags;
1585 /* Params according to the current command */
1587 struct ecore_func_hw_init_params hw_init;
1588 struct ecore_func_hw_reset_params hw_reset;
1589 struct ecore_func_start_params start;
1590 struct ecore_func_switch_update_params switch_update;
1591 struct ecore_func_afex_update_params afex_update;
1592 struct ecore_func_afex_viflists_params afex_viflists;
1593 struct ecore_func_tx_start_params tx_start;
1597 struct ecore_func_sp_drv_ops {
1598 /* Init tool + runtime initialization:
1600 * - Common (per Path)
1604 int (*init_hw_cmn_chip)(struct bnx2x_softc *sc);
1605 int (*init_hw_cmn)(struct bnx2x_softc *sc);
1606 int (*init_hw_port)(struct bnx2x_softc *sc);
1607 int (*init_hw_func)(struct bnx2x_softc *sc);
1609 /* Reset Function HW: Common, Port, Function phases. */
1610 void (*reset_hw_cmn)(struct bnx2x_softc *sc);
1611 void (*reset_hw_port)(struct bnx2x_softc *sc);
1612 void (*reset_hw_func)(struct bnx2x_softc *sc);
1614 /* Prepare/Release FW resources */
1615 int (*init_fw)(struct bnx2x_softc *sc);
1616 void (*release_fw)(struct bnx2x_softc *sc);
1619 struct ecore_func_sp_obj {
1620 enum ecore_func_state state, next_state;
1622 /* ECORE_FUNC_CMD_XX bits. This object implements "one
1623 * pending" paradigm but for debug and tracing purposes it's
1624 * more convenient to have different bits for different
1627 unsigned long pending;
1629 /* Buffer to use as a ramrod data and its mapping */
1631 ecore_dma_addr_t rdata_mapping;
1633 /* Buffer to use as a afex ramrod data and its mapping.
1634 * This can't be same rdata as above because afex ramrod requests
1635 * can arrive to the object in parallel to other ramrod requests.
1638 ecore_dma_addr_t afex_rdata_mapping;
1640 /* this mutex validates that when pending flag is taken, the next
1641 * ramrod to be sent will be the one set the pending bit
1643 ECORE_MUTEX one_pending_mutex;
1645 /* Driver interface */
1646 struct ecore_func_sp_drv_ops *drv;
1649 * Performs one state change according to the given parameters.
1651 * @return 0 in case of success and negative value otherwise.
1653 int (*send_cmd)(struct bnx2x_softc *sc,
1654 struct ecore_func_state_params *params);
1657 * Checks that the requested state transition is legal.
1659 int (*check_transition)(struct bnx2x_softc *sc,
1660 struct ecore_func_sp_obj *o,
1661 struct ecore_func_state_params *params);
1664 * Completes the pending command.
1666 int (*complete_cmd)(struct bnx2x_softc *sc,
1667 struct ecore_func_sp_obj *o,
1668 enum ecore_func_cmd cmd);
1670 int (*wait_comp)(struct bnx2x_softc *sc, struct ecore_func_sp_obj *o,
1671 enum ecore_func_cmd cmd);
1674 /********************** Interfaces ********************************************/
1675 /* Queueable objects set */
1676 union ecore_qable_obj {
1677 struct ecore_vlan_mac_obj vlan_mac;
1679 /************** Function state update *********/
1680 void ecore_init_func_obj(struct bnx2x_softc *sc,
1681 struct ecore_func_sp_obj *obj,
1682 void *rdata, ecore_dma_addr_t rdata_mapping,
1683 void *afex_rdata, ecore_dma_addr_t afex_rdata_mapping,
1684 struct ecore_func_sp_drv_ops *drv_iface);
1686 int ecore_func_state_change(struct bnx2x_softc *sc,
1687 struct ecore_func_state_params *params);
1689 enum ecore_func_state ecore_func_get_state(struct bnx2x_softc *sc,
1690 struct ecore_func_sp_obj *o);
1691 /******************* Queue State **************/
1692 void ecore_init_queue_obj(struct bnx2x_softc *sc,
1693 struct ecore_queue_sp_obj *obj, uint8_t cl_id, uint32_t *cids,
1694 uint8_t cid_cnt, uint8_t func_id, void *rdata,
1695 ecore_dma_addr_t rdata_mapping, unsigned long type);
1697 int ecore_queue_state_change(struct bnx2x_softc *sc,
1698 struct ecore_queue_state_params *params);
1700 /********************* VLAN-MAC ****************/
1701 void ecore_init_mac_obj(struct bnx2x_softc *sc,
1702 struct ecore_vlan_mac_obj *mac_obj,
1703 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata,
1704 ecore_dma_addr_t rdata_mapping, int state,
1705 unsigned long *pstate, ecore_obj_type type,
1706 struct ecore_credit_pool_obj *macs_pool);
1708 void ecore_vlan_mac_h_read_unlock(struct bnx2x_softc *sc,
1709 struct ecore_vlan_mac_obj *o);
1710 int ecore_vlan_mac_h_write_lock(struct bnx2x_softc *sc,
1711 struct ecore_vlan_mac_obj *o);
1712 void ecore_vlan_mac_h_write_unlock(struct bnx2x_softc *sc,
1713 struct ecore_vlan_mac_obj *o);
1714 int ecore_config_vlan_mac(struct bnx2x_softc *sc,
1715 struct ecore_vlan_mac_ramrod_params *p);
1717 int ecore_vlan_mac_move(struct bnx2x_softc *sc,
1718 struct ecore_vlan_mac_ramrod_params *p,
1719 struct ecore_vlan_mac_obj *dest_o);
1721 /********************* RX MODE ****************/
1723 void ecore_init_rx_mode_obj(struct bnx2x_softc *sc,
1724 struct ecore_rx_mode_obj *o);
1727 * ecore_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters.
1729 * @p: Command parameters
1731 * Return: 0 - if operation was successful and there is no pending completions,
1732 * positive number - if there are pending completions,
1733 * negative - if there were errors
1735 int ecore_config_rx_mode(struct bnx2x_softc *sc,
1736 struct ecore_rx_mode_ramrod_params *p);
1738 /****************** MULTICASTS ****************/
1740 void ecore_init_mcast_obj(struct bnx2x_softc *sc,
1741 struct ecore_mcast_obj *mcast_obj,
1742 uint8_t mcast_cl_id, uint32_t mcast_cid, uint8_t func_id,
1743 uint8_t engine_id, void *rdata, ecore_dma_addr_t rdata_mapping,
1744 int state, unsigned long *pstate,
1745 ecore_obj_type type);
1748 * ecore_config_mcast - Configure multicast MACs list.
1750 * @cmd: command to execute: BNX2X_MCAST_CMD_X
1752 * May configure a new list
1753 * provided in p->mcast_list (ECORE_MCAST_CMD_ADD), clean up
1754 * (ECORE_MCAST_CMD_DEL) or restore (ECORE_MCAST_CMD_RESTORE) a current
1755 * configuration, continue to execute the pending commands
1756 * (ECORE_MCAST_CMD_CONT).
1758 * If previous command is still pending or if number of MACs to
1759 * configure is more that maximum number of MACs in one command,
1760 * the current command will be enqueued to the tail of the
1761 * pending commands list.
1763 * Return: 0 is operation was successfull and there are no pending completions,
1764 * negative if there were errors, positive if there are pending
1767 int ecore_config_mcast(struct bnx2x_softc *sc,
1768 struct ecore_mcast_ramrod_params *p,
1769 enum ecore_mcast_cmd cmd);
1771 /****************** CREDIT POOL ****************/
1772 void ecore_init_mac_credit_pool(struct bnx2x_softc *sc,
1773 struct ecore_credit_pool_obj *p, uint8_t func_id,
1775 void ecore_init_vlan_credit_pool(struct bnx2x_softc *sc,
1776 struct ecore_credit_pool_obj *p, uint8_t func_id,
1779 /****************** RSS CONFIGURATION ****************/
1780 void ecore_init_rss_config_obj(struct ecore_rss_config_obj *rss_obj,
1781 uint8_t cl_id, uint32_t cid, uint8_t func_id, uint8_t engine_id,
1782 void *rdata, ecore_dma_addr_t rdata_mapping,
1783 int state, unsigned long *pstate,
1784 ecore_obj_type type);
1787 * ecore_config_rss - Updates RSS configuration according to provided parameters
1789 * Return: 0 in case of success
1791 int ecore_config_rss(struct bnx2x_softc *sc,
1792 struct ecore_config_rss_params *p);
1795 #endif /* ECORE_SP_H */