1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
10 #include "ecore_status.h"
11 #include "ecore_chain.h"
12 #include "ecore_spq.h"
13 #include "ecore_init_fw_funcs.h"
14 #include "ecore_cxt.h"
15 #include "ecore_sp_commands.h"
16 #include "ecore_gtt_reg_addr.h"
17 #include "ecore_iro.h"
19 #include "ecore_int.h"
21 #include "ecore_dcbx.h"
22 #include "ecore_sriov.h"
25 enum _ecore_status_t ecore_sp_init_request(struct ecore_hwfn *p_hwfn,
26 struct ecore_spq_entry **pp_ent,
29 struct ecore_sp_init_data *p_data)
31 u32 opaque_cid = p_data->opaque_fid << 16 | p_data->cid;
32 struct ecore_spq_entry *p_ent = OSAL_NULL;
33 enum _ecore_status_t rc;
38 /* Get an SPQ entry */
39 rc = ecore_spq_get_entry(p_hwfn, pp_ent);
40 if (rc != ECORE_SUCCESS)
43 /* Fill the SPQ entry */
45 p_ent->elem.hdr.cid = OSAL_CPU_TO_LE32(opaque_cid);
46 p_ent->elem.hdr.cmd_id = cmd;
47 p_ent->elem.hdr.protocol_id = protocol;
48 p_ent->priority = ECORE_SPQ_PRIORITY_NORMAL;
49 p_ent->comp_mode = p_data->comp_mode;
50 p_ent->comp_done.done = 0;
52 switch (p_ent->comp_mode) {
53 case ECORE_SPQ_MODE_EBLOCK:
54 p_ent->comp_cb.cookie = &p_ent->comp_done;
57 case ECORE_SPQ_MODE_BLOCK:
58 if (!p_data->p_comp_data)
61 p_ent->comp_cb.cookie = p_data->p_comp_data->cookie;
64 case ECORE_SPQ_MODE_CB:
65 if (!p_data->p_comp_data)
66 p_ent->comp_cb.function = OSAL_NULL;
68 p_ent->comp_cb = *p_data->p_comp_data;
72 DP_NOTICE(p_hwfn, true, "Unknown SPQE completion mode %d\n",
77 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
78 "Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n",
79 opaque_cid, cmd, protocol,
80 (unsigned long)&p_ent->ramrod,
81 D_TRINE(p_ent->comp_mode, ECORE_SPQ_MODE_EBLOCK,
82 ECORE_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK",
85 OSAL_MEMSET(&p_ent->ramrod, 0, sizeof(p_ent->ramrod));
90 static enum tunnel_clss ecore_tunn_clss_to_fw_clss(u8 type)
93 case ECORE_TUNN_CLSS_MAC_VLAN:
94 return TUNNEL_CLSS_MAC_VLAN;
95 case ECORE_TUNN_CLSS_MAC_VNI:
96 return TUNNEL_CLSS_MAC_VNI;
97 case ECORE_TUNN_CLSS_INNER_MAC_VLAN:
98 return TUNNEL_CLSS_INNER_MAC_VLAN;
99 case ECORE_TUNN_CLSS_INNER_MAC_VNI:
100 return TUNNEL_CLSS_INNER_MAC_VNI;
101 case ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE:
102 return TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE;
104 return TUNNEL_CLSS_MAC_VLAN;
109 ecore_set_pf_update_tunn_mode(struct ecore_tunnel_info *p_tun,
110 struct ecore_tunnel_info *p_src,
113 if (p_src->vxlan.b_update_mode || b_pf_start)
114 p_tun->vxlan.b_mode_enabled = p_src->vxlan.b_mode_enabled;
116 if (p_src->l2_gre.b_update_mode || b_pf_start)
117 p_tun->l2_gre.b_mode_enabled = p_src->l2_gre.b_mode_enabled;
119 if (p_src->ip_gre.b_update_mode || b_pf_start)
120 p_tun->ip_gre.b_mode_enabled = p_src->ip_gre.b_mode_enabled;
122 if (p_src->l2_geneve.b_update_mode || b_pf_start)
123 p_tun->l2_geneve.b_mode_enabled =
124 p_src->l2_geneve.b_mode_enabled;
126 if (p_src->ip_geneve.b_update_mode || b_pf_start)
127 p_tun->ip_geneve.b_mode_enabled =
128 p_src->ip_geneve.b_mode_enabled;
131 static void ecore_set_tunn_cls_info(struct ecore_tunnel_info *p_tun,
132 struct ecore_tunnel_info *p_src)
134 enum tunnel_clss type;
136 p_tun->b_update_rx_cls = p_src->b_update_rx_cls;
137 p_tun->b_update_tx_cls = p_src->b_update_tx_cls;
139 /* @DPDK - typecast tunnul class */
140 type = ecore_tunn_clss_to_fw_clss(p_src->vxlan.tun_cls);
141 p_tun->vxlan.tun_cls = (enum ecore_tunn_clss)type;
142 type = ecore_tunn_clss_to_fw_clss(p_src->l2_gre.tun_cls);
143 p_tun->l2_gre.tun_cls = (enum ecore_tunn_clss)type;
144 type = ecore_tunn_clss_to_fw_clss(p_src->ip_gre.tun_cls);
145 p_tun->ip_gre.tun_cls = (enum ecore_tunn_clss)type;
146 type = ecore_tunn_clss_to_fw_clss(p_src->l2_geneve.tun_cls);
147 p_tun->l2_geneve.tun_cls = (enum ecore_tunn_clss)type;
148 type = ecore_tunn_clss_to_fw_clss(p_src->ip_geneve.tun_cls);
149 p_tun->ip_geneve.tun_cls = (enum ecore_tunn_clss)type;
152 static void ecore_set_tunn_ports(struct ecore_tunnel_info *p_tun,
153 struct ecore_tunnel_info *p_src)
155 p_tun->geneve_port.b_update_port = p_src->geneve_port.b_update_port;
156 p_tun->vxlan_port.b_update_port = p_src->vxlan_port.b_update_port;
158 if (p_src->geneve_port.b_update_port)
159 p_tun->geneve_port.port = p_src->geneve_port.port;
161 if (p_src->vxlan_port.b_update_port)
162 p_tun->vxlan_port.port = p_src->vxlan_port.port;
166 __ecore_set_ramrod_tunnel_param(u8 *p_tunn_cls,
167 struct ecore_tunn_update_type *tun_type)
169 *p_tunn_cls = tun_type->tun_cls;
173 ecore_set_ramrod_tunnel_param(u8 *p_tunn_cls,
174 struct ecore_tunn_update_type *tun_type,
175 u8 *p_update_port, __le16 *p_port,
176 struct ecore_tunn_update_udp_port *p_udp_port)
178 __ecore_set_ramrod_tunnel_param(p_tunn_cls, tun_type);
179 if (p_udp_port->b_update_port) {
181 *p_port = OSAL_CPU_TO_LE16(p_udp_port->port);
186 ecore_tunn_set_pf_update_params(struct ecore_hwfn *p_hwfn,
187 struct ecore_tunnel_info *p_src,
188 struct pf_update_tunnel_config *p_tunn_cfg)
190 struct ecore_tunnel_info *p_tun = &p_hwfn->p_dev->tunnel;
192 ecore_set_pf_update_tunn_mode(p_tun, p_src, false);
193 ecore_set_tunn_cls_info(p_tun, p_src);
194 ecore_set_tunn_ports(p_tun, p_src);
196 ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan,
198 &p_tunn_cfg->set_vxlan_udp_port_flg,
199 &p_tunn_cfg->vxlan_udp_port,
202 ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve,
204 &p_tunn_cfg->set_geneve_udp_port_flg,
205 &p_tunn_cfg->geneve_udp_port,
206 &p_tun->geneve_port);
208 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve,
211 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre,
214 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre,
217 p_tunn_cfg->update_rx_pf_clss = p_tun->b_update_rx_cls;
220 static void ecore_set_hw_tunn_mode(struct ecore_hwfn *p_hwfn,
221 struct ecore_ptt *p_ptt,
222 struct ecore_tunnel_info *p_tun)
224 ecore_set_gre_enable(p_hwfn, p_ptt, p_tun->l2_gre.b_mode_enabled,
225 p_tun->ip_gre.b_mode_enabled);
226 ecore_set_vxlan_enable(p_hwfn, p_ptt, p_tun->vxlan.b_mode_enabled);
228 ecore_set_geneve_enable(p_hwfn, p_ptt, p_tun->l2_geneve.b_mode_enabled,
229 p_tun->ip_geneve.b_mode_enabled);
232 static void ecore_set_hw_tunn_mode_port(struct ecore_hwfn *p_hwfn,
233 struct ecore_ptt *p_ptt,
234 struct ecore_tunnel_info *p_tunn)
236 if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
237 DP_NOTICE(p_hwfn, true,
238 "A0 chip: tunnel hw config is not supported\n");
242 if (p_tunn->vxlan_port.b_update_port)
243 ecore_set_vxlan_dest_port(p_hwfn, p_ptt,
244 p_tunn->vxlan_port.port);
246 if (p_tunn->geneve_port.b_update_port)
247 ecore_set_geneve_dest_port(p_hwfn, p_ptt,
248 p_tunn->geneve_port.port);
250 ecore_set_hw_tunn_mode(p_hwfn, p_ptt, p_tunn);
254 ecore_tunn_set_pf_start_params(struct ecore_hwfn *p_hwfn,
255 struct ecore_tunnel_info *p_src,
256 struct pf_start_tunnel_config *p_tunn_cfg)
258 struct ecore_tunnel_info *p_tun = &p_hwfn->p_dev->tunnel;
260 if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
261 DP_NOTICE(p_hwfn, true,
262 "A0 chip: tunnel pf start config is not supported\n");
269 ecore_set_pf_update_tunn_mode(p_tun, p_src, true);
270 ecore_set_tunn_cls_info(p_tun, p_src);
271 ecore_set_tunn_ports(p_tun, p_src);
273 ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan,
275 &p_tunn_cfg->set_vxlan_udp_port_flg,
276 &p_tunn_cfg->vxlan_udp_port,
279 ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve,
281 &p_tunn_cfg->set_geneve_udp_port_flg,
282 &p_tunn_cfg->geneve_udp_port,
283 &p_tun->geneve_port);
285 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve,
288 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre,
291 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre,
295 #define ETH_P_8021Q 0x8100
296 #define ETH_P_8021AD 0x88A8 /* 802.1ad Service VLAN */
298 enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,
299 struct ecore_ptt *p_ptt,
300 struct ecore_tunnel_info *p_tunn,
301 bool allow_npar_tx_switch)
303 struct pf_start_ramrod_data *p_ramrod = OSAL_NULL;
304 u16 sb = ecore_int_get_sp_sb_id(p_hwfn);
305 u8 sb_index = p_hwfn->p_eq->eq_sb_index;
306 struct ecore_spq_entry *p_ent = OSAL_NULL;
307 struct ecore_sp_init_data init_data;
308 enum _ecore_status_t rc = ECORE_NOTIMPL;
312 /* update initial eq producer */
313 ecore_eq_prod_update(p_hwfn,
314 ecore_chain_get_prod_idx(&p_hwfn->p_eq->chain));
316 /* Initialize the SPQ entry for the ramrod */
317 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
318 init_data.cid = ecore_spq_get_cid(p_hwfn);
319 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
320 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
322 rc = ecore_sp_init_request(p_hwfn, &p_ent,
323 COMMON_RAMROD_PF_START,
324 PROTOCOLID_COMMON, &init_data);
325 if (rc != ECORE_SUCCESS)
328 /* Fill the ramrod data */
329 p_ramrod = &p_ent->ramrod.pf_start;
330 p_ramrod->event_ring_sb_id = OSAL_CPU_TO_LE16(sb);
331 p_ramrod->event_ring_sb_index = sb_index;
332 p_ramrod->path_id = ECORE_PATH_ID(p_hwfn);
334 /* For easier debugging */
335 p_ramrod->dont_log_ramrods = 0;
336 p_ramrod->log_type_mask = OSAL_CPU_TO_LE16(0x8f);
338 if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits))
339 p_ramrod->mf_mode = MF_OVLAN;
341 p_ramrod->mf_mode = MF_NPAR;
343 p_ramrod->outer_tag_config.outer_tag.tci =
344 OSAL_CPU_TO_LE16(p_hwfn->hw_info.ovlan);
345 if (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING, &p_hwfn->p_dev->mf_bits)) {
346 p_ramrod->outer_tag_config.outer_tag.tpid = ETH_P_8021Q;
347 } else if (OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING,
348 &p_hwfn->p_dev->mf_bits)) {
349 p_ramrod->outer_tag_config.outer_tag.tpid = ETH_P_8021AD;
350 p_ramrod->outer_tag_config.enable_stag_pri_change = 1;
353 p_ramrod->outer_tag_config.pri_map_valid = 1;
354 for (i = 0; i < ECORE_MAX_PFC_PRIORITIES; i++)
355 p_ramrod->outer_tag_config.inner_to_outer_pri_map[i] = i;
357 /* enable_stag_pri_change should be set if port is in BD mode or,
358 * UFP with Host Control mode.
360 if (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits)) {
361 if (p_hwfn->ufp_info.pri_type == ECORE_UFP_PRI_OS)
362 p_ramrod->outer_tag_config.enable_stag_pri_change = 1;
364 p_ramrod->outer_tag_config.enable_stag_pri_change = 0;
366 p_ramrod->outer_tag_config.outer_tag.tci |=
367 OSAL_CPU_TO_LE16(((u16)p_hwfn->ufp_info.tc << 13));
370 /* Place EQ address in RAMROD */
371 DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr,
372 p_hwfn->p_eq->chain.pbl_sp.p_phys_table);
373 page_cnt = (u8)ecore_chain_get_page_cnt(&p_hwfn->p_eq->chain);
374 p_ramrod->event_ring_num_pages = page_cnt;
375 DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr,
376 p_hwfn->p_consq->chain.pbl_sp.p_phys_table);
378 ecore_tunn_set_pf_start_params(p_hwfn, p_tunn,
379 &p_ramrod->tunnel_config);
381 if (OSAL_TEST_BIT(ECORE_MF_INTER_PF_SWITCH,
382 &p_hwfn->p_dev->mf_bits))
383 p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch;
385 switch (p_hwfn->hw_info.personality) {
387 p_ramrod->personality = PERSONALITY_ETH;
390 DP_NOTICE(p_hwfn, true, "Unknown personality %d\n",
391 p_hwfn->hw_info.personality);
392 p_ramrod->personality = PERSONALITY_ETH;
395 if (p_hwfn->p_dev->p_iov_info) {
396 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
398 p_ramrod->base_vf_id = (u8)p_iov->first_vf_in_pf;
399 p_ramrod->num_vfs = (u8)p_iov->total_vfs;
401 /* @@@TBD - update also the "ROCE_VER_KEY" entries when the FW RoCE HSI
402 * version is available.
404 p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR;
405 p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR;
407 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
408 "Setting event_ring_sb [id %04x index %02x], outer_tag.tpid [%d], outer_tag.tci [%d]\n",
409 sb, sb_index, p_ramrod->outer_tag_config.outer_tag.tpid,
410 p_ramrod->outer_tag_config.outer_tag.tci);
412 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
415 ecore_set_hw_tunn_mode_port(p_hwfn, p_ptt,
416 &p_hwfn->p_dev->tunnel);
421 enum _ecore_status_t ecore_sp_pf_update_dcbx(struct ecore_hwfn *p_hwfn)
423 struct ecore_spq_entry *p_ent = OSAL_NULL;
424 struct ecore_sp_init_data init_data;
425 enum _ecore_status_t rc = ECORE_NOTIMPL;
428 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
429 init_data.cid = ecore_spq_get_cid(p_hwfn);
430 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
431 init_data.comp_mode = ECORE_SPQ_MODE_CB;
433 rc = ecore_sp_init_request(p_hwfn, &p_ent,
434 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
436 if (rc != ECORE_SUCCESS)
439 ecore_dcbx_set_pf_update_params(&p_hwfn->p_dcbx_info->results,
440 &p_ent->ramrod.pf_update);
442 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
445 enum _ecore_status_t ecore_sp_pf_update_ufp(struct ecore_hwfn *p_hwfn)
447 struct ecore_spq_entry *p_ent = OSAL_NULL;
448 struct ecore_sp_init_data init_data;
449 enum _ecore_status_t rc = ECORE_NOTIMPL;
452 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
453 init_data.cid = ecore_spq_get_cid(p_hwfn);
454 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
455 init_data.comp_mode = ECORE_SPQ_MODE_CB;
457 rc = ecore_sp_init_request(p_hwfn, &p_ent,
458 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
460 if (rc != ECORE_SUCCESS)
463 p_ent->ramrod.pf_update.update_enable_stag_pri_change = true;
464 if (p_hwfn->ufp_info.pri_type == ECORE_UFP_PRI_OS)
465 p_ent->ramrod.pf_update.enable_stag_pri_change = 1;
467 p_ent->ramrod.pf_update.enable_stag_pri_change = 0;
469 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
473 /* QM rate limiter resolution is 1.6Mbps */
474 #define QM_RL_RESOLUTION(mb_val) ((mb_val) * 10 / 16)
476 /* FW uses 1/64k to express gd */
477 #define FW_GD_RESOLUTION(gd) (64 * 1024 / (gd))
479 u16 ecore_sp_rl_mb_to_qm(u32 mb_val)
481 return (u16)OSAL_MIN_T(u32, (u16)(~0U), QM_RL_RESOLUTION(mb_val));
484 u16 ecore_sp_rl_gd_denom(u32 gd)
486 return gd ? (u16)OSAL_MIN_T(u32, (u16)(~0U), FW_GD_RESOLUTION(gd)) : 0;
489 enum _ecore_status_t ecore_sp_rl_update(struct ecore_hwfn *p_hwfn,
490 struct ecore_rl_update_params *params)
492 struct ecore_spq_entry *p_ent = OSAL_NULL;
493 enum _ecore_status_t rc = ECORE_NOTIMPL;
494 struct rl_update_ramrod_data *rl_update;
495 struct ecore_sp_init_data init_data;
498 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
499 init_data.cid = ecore_spq_get_cid(p_hwfn);
500 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
501 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
503 rc = ecore_sp_init_request(p_hwfn, &p_ent,
504 COMMON_RAMROD_RL_UPDATE, PROTOCOLID_COMMON,
506 if (rc != ECORE_SUCCESS)
509 rl_update = &p_ent->ramrod.rl_update;
511 rl_update->qcn_update_param_flg = params->qcn_update_param_flg;
512 rl_update->dcqcn_update_param_flg = params->dcqcn_update_param_flg;
513 rl_update->rl_init_flg = params->rl_init_flg;
514 rl_update->rl_start_flg = params->rl_start_flg;
515 rl_update->rl_stop_flg = params->rl_stop_flg;
516 rl_update->rl_id_first = params->rl_id_first;
517 rl_update->rl_id_last = params->rl_id_last;
518 rl_update->rl_dc_qcn_flg = params->rl_dc_qcn_flg;
519 rl_update->dcqcn_reset_alpha_on_idle =
520 params->dcqcn_reset_alpha_on_idle;
521 rl_update->rl_bc_stage_th = params->rl_bc_stage_th;
522 rl_update->rl_timer_stage_th = params->rl_timer_stage_th;
523 rl_update->rl_bc_rate = OSAL_CPU_TO_LE32(params->rl_bc_rate);
524 rl_update->rl_max_rate =
525 OSAL_CPU_TO_LE16(ecore_sp_rl_mb_to_qm(params->rl_max_rate));
527 OSAL_CPU_TO_LE16(ecore_sp_rl_mb_to_qm(params->rl_r_ai));
528 rl_update->rl_r_hai =
529 OSAL_CPU_TO_LE16(ecore_sp_rl_mb_to_qm(params->rl_r_hai));
531 OSAL_CPU_TO_LE16(ecore_sp_rl_gd_denom(params->dcqcn_gd));
532 rl_update->dcqcn_k_us = OSAL_CPU_TO_LE32(params->dcqcn_k_us);
533 rl_update->dcqcn_timeuot_us =
534 OSAL_CPU_TO_LE32(params->dcqcn_timeuot_us);
535 rl_update->qcn_timeuot_us = OSAL_CPU_TO_LE32(params->qcn_timeuot_us);
537 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "rl_params: qcn_update_param_flg %x, dcqcn_update_param_flg %x, rl_init_flg %x, rl_start_flg %x, rl_stop_flg %x, rl_id_first %x, rl_id_last %x, rl_dc_qcn_flg %x,dcqcn_reset_alpha_on_idle %x, rl_bc_stage_th %x, rl_timer_stage_th %x, rl_bc_rate %x, rl_max_rate %x, rl_r_ai %x, rl_r_hai %x, dcqcn_g %x, dcqcn_k_us %x, dcqcn_timeuot_us %x, qcn_timeuot_us %x\n",
538 rl_update->qcn_update_param_flg,
539 rl_update->dcqcn_update_param_flg,
540 rl_update->rl_init_flg, rl_update->rl_start_flg,
541 rl_update->rl_stop_flg, rl_update->rl_id_first,
542 rl_update->rl_id_last, rl_update->rl_dc_qcn_flg,
543 rl_update->dcqcn_reset_alpha_on_idle,
544 rl_update->rl_bc_stage_th, rl_update->rl_timer_stage_th,
545 rl_update->rl_bc_rate, rl_update->rl_max_rate,
546 rl_update->rl_r_ai, rl_update->rl_r_hai,
547 rl_update->dcqcn_g, rl_update->dcqcn_k_us,
548 rl_update->dcqcn_timeuot_us, rl_update->qcn_timeuot_us);
550 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
553 /* Set pf update ramrod command params */
555 ecore_sp_pf_update_tunn_cfg(struct ecore_hwfn *p_hwfn,
556 struct ecore_ptt *p_ptt,
557 struct ecore_tunnel_info *p_tunn,
558 enum spq_mode comp_mode,
559 struct ecore_spq_comp_cb *p_comp_data)
561 struct ecore_spq_entry *p_ent = OSAL_NULL;
562 struct ecore_sp_init_data init_data;
563 enum _ecore_status_t rc = ECORE_NOTIMPL;
565 if (IS_VF(p_hwfn->p_dev))
566 return ecore_vf_pf_tunnel_param_update(p_hwfn, p_tunn);
568 if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
569 DP_NOTICE(p_hwfn, true,
570 "A0 chip: tunnel pf update config is not supported\n");
578 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
579 init_data.cid = ecore_spq_get_cid(p_hwfn);
580 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
581 init_data.comp_mode = comp_mode;
582 init_data.p_comp_data = p_comp_data;
584 rc = ecore_sp_init_request(p_hwfn, &p_ent,
585 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
587 if (rc != ECORE_SUCCESS)
590 ecore_tunn_set_pf_update_params(p_hwfn, p_tunn,
591 &p_ent->ramrod.pf_update.tunnel_config);
593 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
594 if (rc != ECORE_SUCCESS)
597 ecore_set_hw_tunn_mode_port(p_hwfn, p_ptt, &p_hwfn->p_dev->tunnel);
602 enum _ecore_status_t ecore_sp_pf_stop(struct ecore_hwfn *p_hwfn)
604 struct ecore_spq_entry *p_ent = OSAL_NULL;
605 struct ecore_sp_init_data init_data;
606 enum _ecore_status_t rc = ECORE_NOTIMPL;
609 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
610 init_data.cid = ecore_spq_get_cid(p_hwfn);
611 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
612 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
614 rc = ecore_sp_init_request(p_hwfn, &p_ent,
615 COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON,
617 if (rc != ECORE_SUCCESS)
620 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
623 enum _ecore_status_t ecore_sp_heartbeat_ramrod(struct ecore_hwfn *p_hwfn)
625 struct ecore_spq_entry *p_ent = OSAL_NULL;
626 struct ecore_sp_init_data init_data;
627 enum _ecore_status_t rc;
630 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
631 init_data.cid = ecore_spq_get_cid(p_hwfn);
632 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
633 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
635 rc = ecore_sp_init_request(p_hwfn, &p_ent,
636 COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON,
638 if (rc != ECORE_SUCCESS)
641 if (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits))
642 p_ent->ramrod.pf_update.mf_vlan |=
643 OSAL_CPU_TO_LE16(((u16)p_hwfn->ufp_info.tc << 13));
645 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
648 enum _ecore_status_t ecore_sp_pf_update_stag(struct ecore_hwfn *p_hwfn)
650 struct ecore_spq_entry *p_ent = OSAL_NULL;
651 struct ecore_sp_init_data init_data;
652 enum _ecore_status_t rc = ECORE_NOTIMPL;
655 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
656 init_data.cid = ecore_spq_get_cid(p_hwfn);
657 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
658 init_data.comp_mode = ECORE_SPQ_MODE_CB;
660 rc = ecore_sp_init_request(p_hwfn, &p_ent,
661 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
663 if (rc != ECORE_SUCCESS)
666 p_ent->ramrod.pf_update.update_mf_vlan_flag = true;
667 p_ent->ramrod.pf_update.mf_vlan =
668 OSAL_CPU_TO_LE16(p_hwfn->hw_info.ovlan);
670 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);