1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2012-2019 Solarflare Communications Inc.
9 #if EFSYS_OPT_MON_STATS
16 * Non-interrupting event queue requires interrrupting event queue to
17 * refer to for wake-up events even if wake ups are never used.
18 * It could be even non-allocated event queue.
20 #define EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX (0)
22 static __checkReturn boolean_t
25 __in efx_qword_t *eqp,
26 __in const efx_ev_callbacks_t *eecp,
29 static __checkReturn boolean_t
32 __in efx_qword_t *eqp,
33 __in const efx_ev_callbacks_t *eecp,
36 static __checkReturn boolean_t
39 __in efx_qword_t *eqp,
40 __in const efx_ev_callbacks_t *eecp,
43 static __checkReturn boolean_t
46 __in efx_qword_t *eqp,
47 __in const efx_ev_callbacks_t *eecp,
51 static __checkReturn efx_rc_t
54 __in uint32_t instance,
56 __in uint32_t timer_ns)
59 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_EVQ_TMR_IN_LEN,
60 MC_CMD_SET_EVQ_TMR_OUT_LEN);
63 req.emr_cmd = MC_CMD_SET_EVQ_TMR;
64 req.emr_in_buf = payload;
65 req.emr_in_length = MC_CMD_SET_EVQ_TMR_IN_LEN;
66 req.emr_out_buf = payload;
67 req.emr_out_length = MC_CMD_SET_EVQ_TMR_OUT_LEN;
69 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_INSTANCE, instance);
70 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, timer_ns);
71 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, timer_ns);
72 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_MODE, mode);
74 efx_mcdi_execute(enp, &req);
76 if (req.emr_rc != 0) {
81 if (req.emr_out_length_used < MC_CMD_SET_EVQ_TMR_OUT_LEN) {
91 EFSYS_PROBE1(fail1, efx_rc_t, rc);
97 __checkReturn efx_rc_t
101 _NOTE(ARGUNUSED(enp))
109 _NOTE(ARGUNUSED(enp))
112 __checkReturn efx_rc_t
115 __in unsigned int index,
116 __in efsys_mem_t *esmp,
123 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
126 boolean_t low_latency;
128 _NOTE(ARGUNUSED(id)) /* buftbl id managed by MC */
130 EFSYS_ASSERT((flags & EFX_EVQ_FLAGS_EXTENDED_WIDTH) == 0);
133 * NO_CONT_EV mode is only requested from the firmware when creating
134 * receive queues, but here it needs to be specified at event queue
135 * creation, as the event handler needs to know which format is in use.
137 * If EFX_EVQ_FLAGS_NO_CONT_EV is specified, all receive queues for this
138 * event queue will be created in NO_CONT_EV mode.
140 * See SF-109306-TC 5.11 "Events for RXQs in NO_CONT_EV mode".
142 if (flags & EFX_EVQ_FLAGS_NO_CONT_EV) {
143 if (enp->en_nic_cfg.enc_no_cont_ev_mode_supported == B_FALSE) {
149 /* Set up the handler table */
150 eep->ee_rx = ef10_ev_rx;
151 eep->ee_tx = ef10_ev_tx;
152 eep->ee_driver = ef10_ev_driver;
153 eep->ee_drv_gen = ef10_ev_drv_gen;
154 eep->ee_mcdi = ef10_ev_mcdi;
156 /* Set up the event queue */
157 /* INIT_EVQ expects function-relative vector number */
158 if ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
159 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT) {
161 } else if (index == EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX) {
163 flags = (flags & ~EFX_EVQ_FLAGS_NOTIFY_MASK) |
164 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT;
166 irq = EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX;
170 * Interrupts may be raised for events immediately after the queue is
171 * created. See bug58606.
175 * On Huntington we need to specify the settings to use.
176 * If event queue type in flags is auto, we favour throughput
177 * if the adapter is running virtualization supporting firmware
178 * (i.e. the full featured firmware variant)
179 * and latency otherwise. The Ethernet Virtual Bridging
180 * capability is used to make this decision. (Note though that
181 * the low latency firmware variant is also best for
182 * throughput and corresponding type should be specified
185 * If FW supports EvQ types (e.g. on Medford and Medford2) the
186 * type which is specified in flags is passed to FW to make the
187 * decision and low_latency hint is ignored.
189 low_latency = encp->enc_datapath_cap_evb ? 0 : 1;
190 rc = efx_mcdi_init_evq(enp, index, esmp, ndescs, irq, us, flags,
200 EFSYS_PROBE1(fail1, efx_rc_t, rc);
209 efx_nic_t *enp = eep->ee_enp;
211 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
213 (void) efx_mcdi_fini_evq(enp, eep->ee_index);
216 __checkReturn efx_rc_t
219 __in unsigned int count)
221 efx_nic_t *enp = eep->ee_enp;
225 rptr = count & eep->ee_mask;
227 if (enp->en_nic_cfg.enc_bug35388_workaround) {
228 EFX_STATIC_ASSERT(EF10_EVQ_MINNEVS >
229 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
230 EFX_STATIC_ASSERT(EF10_EVQ_MAXNEVS <
231 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
233 EFX_POPULATE_DWORD_2(dword,
234 ERF_DD_EVQ_IND_RPTR_FLAGS,
235 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
237 (rptr >> ERF_DD_EVQ_IND_RPTR_WIDTH));
238 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
241 EFX_POPULATE_DWORD_2(dword,
242 ERF_DD_EVQ_IND_RPTR_FLAGS,
243 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
245 rptr & ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
246 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
249 EFX_POPULATE_DWORD_1(dword, ERF_DZ_EVQ_RPTR, rptr);
250 EFX_BAR_VI_WRITED(enp, ER_DZ_EVQ_RPTR_REG, eep->ee_index,
257 static __checkReturn efx_rc_t
258 efx_mcdi_driver_event(
261 __in efx_qword_t data)
264 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_DRIVER_EVENT_IN_LEN,
265 MC_CMD_DRIVER_EVENT_OUT_LEN);
268 req.emr_cmd = MC_CMD_DRIVER_EVENT;
269 req.emr_in_buf = payload;
270 req.emr_in_length = MC_CMD_DRIVER_EVENT_IN_LEN;
271 req.emr_out_buf = payload;
272 req.emr_out_length = MC_CMD_DRIVER_EVENT_OUT_LEN;
274 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_EVQ, evq);
276 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_LO,
277 EFX_QWORD_FIELD(data, EFX_DWORD_0));
278 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_HI,
279 EFX_QWORD_FIELD(data, EFX_DWORD_1));
281 efx_mcdi_execute(enp, &req);
283 if (req.emr_rc != 0) {
291 EFSYS_PROBE1(fail1, efx_rc_t, rc);
301 efx_nic_t *enp = eep->ee_enp;
304 EFX_POPULATE_QWORD_3(event,
305 ESF_DZ_DRV_CODE, ESE_DZ_EV_CODE_DRV_GEN_EV,
306 ESF_DZ_DRV_SUB_CODE, 0,
307 ESF_DZ_DRV_SUB_DATA_DW0, (uint32_t)data);
309 (void) efx_mcdi_driver_event(enp, eep->ee_index, event);
312 __checkReturn efx_rc_t
315 __in unsigned int us)
317 efx_nic_t *enp = eep->ee_enp;
318 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
323 /* Check that hardware and MCDI use the same timer MODE values */
324 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_DIS ==
325 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS);
326 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_IMMED_START ==
327 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START);
328 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_TRIG_START ==
329 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START);
330 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_INT_HLDOFF ==
331 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF);
333 if (us > encp->enc_evq_timer_max_us) {
338 /* If the value is zero then disable the timer */
340 mode = FFE_CZ_TIMER_MODE_DIS;
342 mode = FFE_CZ_TIMER_MODE_INT_HLDOFF;
345 if (encp->enc_bug61265_workaround) {
346 uint32_t ns = us * 1000;
348 rc = efx_mcdi_set_evq_tmr(enp, eep->ee_index, mode, ns);
354 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
357 if (encp->enc_bug35388_workaround) {
358 EFX_POPULATE_DWORD_3(dword,
359 ERF_DD_EVQ_IND_TIMER_FLAGS,
360 EFE_DD_EVQ_IND_TIMER_FLAGS,
361 ERF_DD_EVQ_IND_TIMER_MODE, mode,
362 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
363 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT,
364 eep->ee_index, &dword, 0);
367 * NOTE: The TMR_REL field introduced in Medford2 is
368 * ignored on earlier EF10 controllers. See bug66418
369 * comment 9 for details.
371 EFX_POPULATE_DWORD_3(dword,
372 ERF_DZ_TC_TIMER_MODE, mode,
373 ERF_DZ_TC_TIMER_VAL, ticks,
374 ERF_FZ_TC_TMR_REL_VAL, ticks);
375 EFX_BAR_VI_WRITED(enp, ER_DZ_EVQ_TMR_REG,
376 eep->ee_index, &dword, 0);
387 EFSYS_PROBE1(fail1, efx_rc_t, rc);
395 ef10_ev_qstats_update(
397 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
401 for (id = 0; id < EV_NQSTATS; id++) {
402 efsys_stat_t *essp = &stat[id];
404 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
405 eep->ee_stat[id] = 0;
408 #endif /* EFSYS_OPT_QSTATS */
410 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
412 static __checkReturn boolean_t
413 ef10_ev_rx_packed_stream(
415 __in efx_qword_t *eqp,
416 __in const efx_ev_callbacks_t *eecp,
420 uint32_t pkt_count_lbits;
422 boolean_t should_abort;
423 efx_evq_rxq_state_t *eersp;
424 unsigned int pkt_count;
425 unsigned int current_id;
426 boolean_t new_buffer;
428 pkt_count_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
429 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
430 new_buffer = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_EV_ROTATE);
434 eersp = &eep->ee_rxq_state[label];
437 * RX_DSC_PTR_LBITS has least significant bits of the global
438 * (not per-buffer) packet counter. It is guaranteed that
439 * maximum number of completed packets fits in lbits-mask.
440 * So, modulo lbits-mask arithmetic should be used to calculate
441 * packet counter increment.
443 pkt_count = (pkt_count_lbits - eersp->eers_rx_stream_npackets) &
444 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
445 eersp->eers_rx_stream_npackets += pkt_count;
448 flags |= EFX_PKT_PACKED_STREAM_NEW_BUFFER;
449 #if EFSYS_OPT_RX_PACKED_STREAM
451 * If both packed stream and equal stride super-buffer
452 * modes are compiled in, in theory credits should be
453 * be maintained for packed stream only, but right now
454 * these modes are not distinguished in the event queue
455 * Rx queue state and it is OK to increment the counter
456 * regardless (it might be event cheaper than branching
457 * since neighbour structure member are updated as well).
459 eersp->eers_rx_packed_stream_credits++;
461 eersp->eers_rx_read_ptr++;
463 current_id = eersp->eers_rx_read_ptr & eersp->eers_rx_mask;
465 /* Check for errors that invalidate checksum and L3/L4 fields */
466 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TRUNC_ERR) != 0) {
467 /* RX frame truncated */
468 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
469 flags |= EFX_DISCARD;
472 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
473 /* Bad Ethernet frame CRC */
474 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
475 flags |= EFX_DISCARD;
479 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
480 EFX_EV_QSTAT_INCR(eep, EV_RX_PARSE_INCOMPLETE);
481 flags |= EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE;
485 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR))
486 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
488 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR))
489 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
492 /* If we're not discarding the packet then it is ok */
493 if (~flags & EFX_DISCARD)
494 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
496 EFSYS_ASSERT(eecp->eec_rx_ps != NULL);
497 should_abort = eecp->eec_rx_ps(arg, label, current_id, pkt_count,
500 return (should_abort);
503 #endif /* EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER */
505 static __checkReturn boolean_t
508 __in efx_qword_t *eqp,
509 __in const efx_ev_callbacks_t *eecp,
512 efx_nic_t *enp = eep->ee_enp;
516 uint32_t eth_tag_class;
519 uint32_t next_read_lbits;
522 boolean_t should_abort;
523 efx_evq_rxq_state_t *eersp;
524 unsigned int desc_count;
525 unsigned int last_used_id;
527 EFX_EV_QSTAT_INCR(eep, EV_RX);
529 /* Discard events after RXQ/TXQ errors, or hardware not available */
530 if (enp->en_reset_flags &
531 (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR | EFX_RESET_HW_UNAVAIL))
534 /* Basic packet information */
535 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
536 eersp = &eep->ee_rxq_state[label];
538 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
540 * Packed stream events are very different,
541 * so handle them separately
543 if (eersp->eers_rx_packed_stream)
544 return (ef10_ev_rx_packed_stream(eep, eqp, eecp, arg));
547 size = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_BYTES);
548 cont = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CONT);
549 next_read_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
550 eth_tag_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ETH_TAG_CLASS);
551 mac_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_MAC_CLASS);
552 l3_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L3_CLASS);
555 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is only
556 * 2 bits wide on Medford2. Check it is safe to use the Medford2 field
557 * and values for all EF10 controllers.
559 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN == ESF_DE_RX_L4_CLASS_LBN);
560 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
561 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
562 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN == ESE_DE_L4_CLASS_UNKNOWN);
564 l4_class = EFX_QWORD_FIELD(*eqp, ESF_FZ_RX_L4_CLASS);
566 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DROP_EVENT) != 0) {
567 /* Drop this event */
574 * This may be part of a scattered frame, or it may be a
575 * truncated frame if scatter is disabled on this RXQ.
576 * Overlength frames can be received if e.g. a VF is configured
577 * for 1500 MTU but connected to a port set to 9000 MTU
579 * FIXME: There is not yet any driver that supports scatter on
580 * Huntington. Scatter support is required for OSX.
582 flags |= EFX_PKT_CONT;
585 if (mac_class == ESE_DZ_MAC_CLASS_UCAST)
586 flags |= EFX_PKT_UNICAST;
589 * Increment the count of descriptors read.
591 * In NO_CONT_EV mode, RX_DSC_PTR_LBITS is actually a packet count, but
592 * when scatter is disabled, there is only one descriptor per packet and
593 * so it can be treated the same.
595 * TODO: Support scatter in NO_CONT_EV mode.
597 desc_count = (next_read_lbits - eersp->eers_rx_read_ptr) &
598 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
599 eersp->eers_rx_read_ptr += desc_count;
601 /* Calculate the index of the last descriptor consumed */
602 last_used_id = (eersp->eers_rx_read_ptr - 1) & eersp->eers_rx_mask;
604 if (eep->ee_flags & EFX_EVQ_FLAGS_NO_CONT_EV) {
606 EFX_EV_QSTAT_INCR(eep, EV_RX_BATCH);
608 /* Always read the length from the prefix in NO_CONT_EV mode. */
609 flags |= EFX_PKT_PREFIX_LEN;
612 * Check for an aborted scatter, signalled by the ABORT bit in
613 * NO_CONT_EV mode. The ABORT bit was not used before NO_CONT_EV
614 * mode was added as it was broken in Huntington silicon.
616 if (EFX_QWORD_FIELD(*eqp, ESF_EZ_RX_ABORT) != 0) {
617 flags |= EFX_DISCARD;
620 } else if (desc_count > 1) {
622 * FIXME: add error checking to make sure this a batched event.
623 * This could also be an aborted scatter, see Bug36629.
625 EFX_EV_QSTAT_INCR(eep, EV_RX_BATCH);
626 flags |= EFX_PKT_PREFIX_LEN;
629 /* Check for errors that invalidate checksum and L3/L4 fields */
630 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TRUNC_ERR) != 0) {
631 /* RX frame truncated */
632 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
633 flags |= EFX_DISCARD;
636 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
637 /* Bad Ethernet frame CRC */
638 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
639 flags |= EFX_DISCARD;
642 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
644 * Hardware parse failed, due to malformed headers
645 * or headers that are too long for the parser.
646 * Headers and checksums must be validated by the host.
648 EFX_EV_QSTAT_INCR(eep, EV_RX_PARSE_INCOMPLETE);
652 if ((eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN1) ||
653 (eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN2)) {
654 flags |= EFX_PKT_VLAN_TAGGED;
658 case ESE_DZ_L3_CLASS_IP4:
659 case ESE_DZ_L3_CLASS_IP4_FRAG:
660 flags |= EFX_PKT_IPV4;
661 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR)) {
662 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
664 flags |= EFX_CKSUM_IPV4;
668 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is
669 * only 2 bits wide on Medford2. Check it is safe to use the
670 * Medford2 field and values for all EF10 controllers.
672 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
673 ESF_DE_RX_L4_CLASS_LBN);
674 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
675 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
676 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
677 ESE_DE_L4_CLASS_UNKNOWN);
679 if (l4_class == ESE_FZ_L4_CLASS_TCP) {
680 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
681 flags |= EFX_PKT_TCP;
682 } else if (l4_class == ESE_FZ_L4_CLASS_UDP) {
683 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
684 flags |= EFX_PKT_UDP;
686 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
690 case ESE_DZ_L3_CLASS_IP6:
691 case ESE_DZ_L3_CLASS_IP6_FRAG:
692 flags |= EFX_PKT_IPV6;
695 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is
696 * only 2 bits wide on Medford2. Check it is safe to use the
697 * Medford2 field and values for all EF10 controllers.
699 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
700 ESF_DE_RX_L4_CLASS_LBN);
701 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
702 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
703 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
704 ESE_DE_L4_CLASS_UNKNOWN);
706 if (l4_class == ESE_FZ_L4_CLASS_TCP) {
707 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
708 flags |= EFX_PKT_TCP;
709 } else if (l4_class == ESE_FZ_L4_CLASS_UDP) {
710 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
711 flags |= EFX_PKT_UDP;
713 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
718 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
722 if (flags & (EFX_PKT_TCP | EFX_PKT_UDP)) {
723 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
724 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
726 flags |= EFX_CKSUM_TCPUDP;
731 /* If we're not discarding the packet then it is ok */
732 if (~flags & EFX_DISCARD)
733 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
735 EFSYS_ASSERT(eecp->eec_rx != NULL);
736 should_abort = eecp->eec_rx(arg, label, last_used_id, size, flags);
738 return (should_abort);
741 static __checkReturn boolean_t
744 __in efx_qword_t *eqp,
745 __in const efx_ev_callbacks_t *eecp,
748 efx_nic_t *enp = eep->ee_enp;
751 boolean_t should_abort;
753 EFX_EV_QSTAT_INCR(eep, EV_TX);
755 /* Discard events after RXQ/TXQ errors, or hardware not available */
756 if (enp->en_reset_flags &
757 (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR | EFX_RESET_HW_UNAVAIL))
760 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DROP_EVENT) != 0) {
761 /* Drop this event */
765 /* Per-packet TX completion (was per-descriptor for Falcon/Siena) */
766 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DESCR_INDX);
767 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_QLABEL);
769 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
771 EFSYS_ASSERT(eecp->eec_tx != NULL);
772 should_abort = eecp->eec_tx(arg, label, id);
774 return (should_abort);
777 static __checkReturn boolean_t
780 __in efx_qword_t *eqp,
781 __in const efx_ev_callbacks_t *eecp,
785 boolean_t should_abort;
787 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
788 should_abort = B_FALSE;
790 code = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_CODE);
792 case ESE_DZ_DRV_TIMER_EV: {
795 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_TMR_ID);
797 EFSYS_ASSERT(eecp->eec_timer != NULL);
798 should_abort = eecp->eec_timer(arg, id);
802 case ESE_DZ_DRV_WAKE_UP_EV: {
805 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_EVQ_ID);
807 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
808 should_abort = eecp->eec_wake_up(arg, id);
812 case ESE_DZ_DRV_START_UP_EV:
813 EFSYS_ASSERT(eecp->eec_initialized != NULL);
814 should_abort = eecp->eec_initialized(arg);
818 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
819 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
820 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
824 return (should_abort);
827 static __checkReturn boolean_t
830 __in efx_qword_t *eqp,
831 __in const efx_ev_callbacks_t *eecp,
835 boolean_t should_abort;
837 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
838 should_abort = B_FALSE;
840 data = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_DATA_DW0);
841 if (data >= ((uint32_t)1 << 16)) {
842 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
843 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
844 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
849 EFSYS_ASSERT(eecp->eec_software != NULL);
850 should_abort = eecp->eec_software(arg, (uint16_t)data);
852 return (should_abort);
855 #endif /* EFX_OPTS_EF10() */
857 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
859 __checkReturn boolean_t
862 __in efx_qword_t *eqp,
863 __in const efx_ev_callbacks_t *eecp,
866 efx_nic_t *enp = eep->ee_enp;
868 boolean_t should_abort = B_FALSE;
870 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
872 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
874 case MCDI_EVENT_CODE_BADSSERT:
875 efx_mcdi_ev_death(enp, EINTR);
878 case MCDI_EVENT_CODE_CMDDONE:
880 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
881 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
882 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
885 #if EFSYS_OPT_MCDI_PROXY_AUTH
886 case MCDI_EVENT_CODE_PROXY_RESPONSE:
888 * This event notifies a function that an authorization request
889 * has been processed. If the request was authorized then the
890 * function can now re-send the original MCDI request.
891 * See SF-113652-SW "SR-IOV Proxied Network Access Control".
893 efx_mcdi_ev_proxy_response(enp,
894 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_HANDLE),
895 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_RC));
897 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
899 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
900 case MCDI_EVENT_CODE_PROXY_REQUEST:
901 efx_mcdi_ev_proxy_request(enp,
902 MCDI_EV_FIELD(eqp, PROXY_REQUEST_BUFF_INDEX));
904 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
906 case MCDI_EVENT_CODE_LINKCHANGE: {
907 efx_link_mode_t link_mode;
909 ef10_phy_link_ev(enp, eqp, &link_mode);
910 should_abort = eecp->eec_link_change(arg, link_mode);
914 case MCDI_EVENT_CODE_SENSOREVT: {
915 #if EFSYS_OPT_MON_STATS
917 efx_mon_stat_value_t value;
920 /* Decode monitor stat for MCDI sensor (if supported) */
921 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0) {
922 /* Report monitor stat change */
923 should_abort = eecp->eec_monitor(arg, id, value);
924 } else if (rc == ENOTSUP) {
925 should_abort = eecp->eec_exception(arg,
926 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
927 MCDI_EV_FIELD(eqp, DATA));
929 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
935 case MCDI_EVENT_CODE_SCHEDERR:
936 /* Informational only */
939 case MCDI_EVENT_CODE_REBOOT:
940 /* Falcon/Siena only (should not been seen with Huntington). */
941 efx_mcdi_ev_death(enp, EIO);
944 case MCDI_EVENT_CODE_MC_REBOOT:
945 /* MC_REBOOT event is used for Huntington (EF10) and later. */
946 efx_mcdi_ev_death(enp, EIO);
949 case MCDI_EVENT_CODE_MAC_STATS_DMA:
950 #if EFSYS_OPT_MAC_STATS
951 if (eecp->eec_mac_stats != NULL) {
952 eecp->eec_mac_stats(arg,
953 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
958 case MCDI_EVENT_CODE_FWALERT: {
959 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
961 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
962 should_abort = eecp->eec_exception(arg,
963 EFX_EXCEPTION_FWALERT_SRAM,
964 MCDI_EV_FIELD(eqp, FWALERT_DATA));
966 should_abort = eecp->eec_exception(arg,
967 EFX_EXCEPTION_UNKNOWN_FWALERT,
968 MCDI_EV_FIELD(eqp, DATA));
972 case MCDI_EVENT_CODE_TX_ERR: {
974 * After a TXQ error is detected, firmware sends a TX_ERR event.
975 * This may be followed by TX completions (which we discard),
976 * and then finally by a TX_FLUSH event. Firmware destroys the
977 * TXQ automatically after sending the TX_FLUSH event.
979 enp->en_reset_flags |= EFX_RESET_TXQ_ERR;
981 EFSYS_PROBE2(tx_descq_err,
982 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
983 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
985 /* Inform the driver that a reset is required. */
986 eecp->eec_exception(arg, EFX_EXCEPTION_TX_ERROR,
987 MCDI_EV_FIELD(eqp, TX_ERR_DATA));
991 case MCDI_EVENT_CODE_TX_FLUSH: {
992 uint32_t txq_index = MCDI_EV_FIELD(eqp, TX_FLUSH_TXQ);
995 * EF10 firmware sends two TX_FLUSH events: one to the txq's
996 * event queue, and one to evq 0 (with TX_FLUSH_TO_DRIVER set).
997 * We want to wait for all completions, so ignore the events
998 * with TX_FLUSH_TO_DRIVER.
1000 if (MCDI_EV_FIELD(eqp, TX_FLUSH_TO_DRIVER) != 0) {
1001 should_abort = B_FALSE;
1005 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
1007 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
1009 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
1010 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
1014 case MCDI_EVENT_CODE_RX_ERR: {
1016 * After an RXQ error is detected, firmware sends an RX_ERR
1017 * event. This may be followed by RX events (which we discard),
1018 * and then finally by an RX_FLUSH event. Firmware destroys the
1019 * RXQ automatically after sending the RX_FLUSH event.
1021 enp->en_reset_flags |= EFX_RESET_RXQ_ERR;
1023 EFSYS_PROBE2(rx_descq_err,
1024 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1025 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1027 /* Inform the driver that a reset is required. */
1028 eecp->eec_exception(arg, EFX_EXCEPTION_RX_ERROR,
1029 MCDI_EV_FIELD(eqp, RX_ERR_DATA));
1033 case MCDI_EVENT_CODE_RX_FLUSH: {
1034 uint32_t rxq_index = MCDI_EV_FIELD(eqp, RX_FLUSH_RXQ);
1037 * EF10 firmware sends two RX_FLUSH events: one to the rxq's
1038 * event queue, and one to evq 0 (with RX_FLUSH_TO_DRIVER set).
1039 * We want to wait for all completions, so ignore the events
1040 * with RX_FLUSH_TO_DRIVER.
1042 if (MCDI_EV_FIELD(eqp, RX_FLUSH_TO_DRIVER) != 0) {
1043 should_abort = B_FALSE;
1047 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
1049 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
1051 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
1052 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
1057 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1058 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1059 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1063 return (should_abort);
1066 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
1071 ef10_ev_rxlabel_init(
1072 __in efx_evq_t *eep,
1073 __in efx_rxq_t *erp,
1074 __in unsigned int label,
1075 __in efx_rxq_type_t type)
1077 efx_evq_rxq_state_t *eersp;
1078 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1079 boolean_t packed_stream = (type == EFX_RXQ_TYPE_PACKED_STREAM);
1080 boolean_t es_super_buffer = (type == EFX_RXQ_TYPE_ES_SUPER_BUFFER);
1083 _NOTE(ARGUNUSED(type))
1084 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1085 eersp = &eep->ee_rxq_state[label];
1087 EFSYS_ASSERT3U(eersp->eers_rx_mask, ==, 0);
1089 #if EFSYS_OPT_RX_PACKED_STREAM
1091 * For packed stream modes, the very first event will
1092 * have a new buffer flag set, so it will be incremented,
1093 * yielding the correct pointer. That results in a simpler
1094 * code than trying to detect start-of-the-world condition
1095 * in the event handler.
1097 eersp->eers_rx_read_ptr = packed_stream ? ~0 : 0;
1099 eersp->eers_rx_read_ptr = 0;
1101 eersp->eers_rx_mask = erp->er_mask;
1102 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1103 eersp->eers_rx_stream_npackets = 0;
1104 eersp->eers_rx_packed_stream = packed_stream || es_super_buffer;
1106 #if EFSYS_OPT_RX_PACKED_STREAM
1107 if (packed_stream) {
1108 eersp->eers_rx_packed_stream_credits = (eep->ee_mask + 1) /
1109 EFX_DIV_ROUND_UP(EFX_RX_PACKED_STREAM_MEM_PER_CREDIT,
1110 EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE);
1111 EFSYS_ASSERT3U(eersp->eers_rx_packed_stream_credits, !=, 0);
1113 * A single credit is allocated to the queue when it is started.
1114 * It is immediately spent by the first packet which has NEW
1115 * BUFFER flag set, though, but still we shall take into
1116 * account, as to not wrap around the maximum number of credits
1119 eersp->eers_rx_packed_stream_credits--;
1120 EFSYS_ASSERT3U(eersp->eers_rx_packed_stream_credits, <=,
1121 EFX_RX_PACKED_STREAM_MAX_CREDITS);
1127 ef10_ev_rxlabel_fini(
1128 __in efx_evq_t *eep,
1129 __in unsigned int label)
1131 efx_evq_rxq_state_t *eersp;
1133 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1134 eersp = &eep->ee_rxq_state[label];
1136 EFSYS_ASSERT3U(eersp->eers_rx_mask, !=, 0);
1138 eersp->eers_rx_read_ptr = 0;
1139 eersp->eers_rx_mask = 0;
1140 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1141 eersp->eers_rx_stream_npackets = 0;
1142 eersp->eers_rx_packed_stream = B_FALSE;
1144 #if EFSYS_OPT_RX_PACKED_STREAM
1145 eersp->eers_rx_packed_stream_credits = 0;
1149 #endif /* EFX_OPTS_EF10() */