1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
8 * This is NOT the original source file. Do NOT edit it.
9 * To update the tlv layout, please edit the copy in
10 * the sfregistry repo and then, in that repo,
11 * "make tlv_headers" or "make export" to
12 * regenerate and export all types of headers.
15 /* These structures define the layouts for the TLV items stored in static and
16 * dynamic configuration partitions in NVRAM for EF10 (Huntington etc.).
18 * They contain the same sort of information that was kept in the
19 * siena_mc_static_config_hdr_t and siena_mc_dynamic_config_hdr_t structures
20 * (defined in <ci/mgmt/mc_flash_layout.h> and <ci/mgmt/mc_dynamic_cfg.h>) for
23 * These are used directly by the MC and should also be usable directly on host
24 * systems which are little-endian and do not do strange things with structure
25 * padding. (Big-endian host systems will require some byte-swapping.)
29 * Please refer to SF-108797-SW for a general overview of the TLV partition
34 * The current tag IDs have a general structure: with the exception of the
35 * special values defined in the document, they are of the form 0xLTTTNNNN,
38 * - L is a location, indicating where this tag is expected to be found:
39 * 0: static configuration
40 * 1: dynamic configuration
41 * 2: firmware internal use
42 * 3: license partition
43 * 4: tsa configuration
46 * - TTT is a type, which is just a unique value. The same type value
47 * might appear in both locations, indicating a relationship between
48 * the items (e.g. static and dynamic VPD below).
50 * - NNNN is an index of some form. Some item types are per-port, some
51 * are per-PF, some are per-partition-type.
55 * As with the previous Siena structures, each structure here is laid out
56 * carefully: values are aligned to their natural boundary, with explicit
57 * padding fields added where necessary. (No, technically this does not
58 * absolutely guarantee portability. But, in practice, compilers are generally
59 * sensible enough not to introduce completely pointless padding, and it works
64 #ifndef CI_MGMT_TLV_LAYOUT_H
65 #define CI_MGMT_TLV_LAYOUT_H
68 /* ----------------------------------------------------------------------------
69 * General structure (defined by SF-108797-SW)
70 * ----------------------------------------------------------------------------
76 * (Note that this is *not* followed by length or value fields: anything after
77 * the tag itself is irrelevant.)
80 #define TLV_TAG_END (0xEEEEEEEE)
83 /* Other special reserved tag values.
86 #define TLV_TAG_SKIP (0x00000000)
87 #define TLV_TAG_INVALID (0xFFFFFFFF)
92 * Marks the start of a TLV layout within a partition that may/may-not be
93 * a TLV partition. i.e. if a portion of data (at any offset) within a
94 * partition is expected to be in TLV format, then the first tag in this
95 * layout is expected to be TLV_TAG_START.
97 * This tag is not used in TLV layouts where the entire partition is TLV.
98 * Please continue using TLV_TAG_PARTITION_HEADER to indicate the start
99 * of TLV layout in such cases.
102 #define TLV_TAG_START (0xEF10BA5E)
107 /* Length of the TLV structure following this tag - includes length of all tags
108 * within the TLV layout starting with this TLV_TAG_START.
109 * Includes TLV_TAG_END. Does not include TLV_TAG_START
111 uint32_t tlv_layout_len;
114 /* TLV partition header.
116 * In a TLV partition, this must be the first item in the sequence, at offset
120 #define TLV_TAG_PARTITION_HEADER (0xEF10DA7A)
122 struct tlv_partition_header {
126 /* 0 indicates the default segment (always located at offset 0), while other values
127 * are for RFID-selectable presets that should immediately follow the default segment.
128 * The default segment may also have preset > 0, which means that it is a preset
129 * selected through an RFID command and copied by FW to the location at offset 0. */
132 uint32_t total_length;
136 /* TLV partition trailer.
138 * In a TLV partition, this must be the last item in the sequence, immediately
139 * preceding the TLV_TAG_END word.
142 #define TLV_TAG_PARTITION_TRAILER (0xEF101A57)
144 struct tlv_partition_trailer {
152 /* Appendable TLV partition header.
154 * In an appendable TLV partition, this must be the first item in the sequence,
155 * at offset 0. (Note that, unlike the configuration partitions, there is no
156 * trailer before the TLV_TAG_END word.)
159 #define TLV_TAG_APPENDABLE_PARTITION_HEADER (0xEF10ADA7)
161 struct tlv_appendable_partition_header {
169 /* ----------------------------------------------------------------------------
170 * Configuration items
171 * ----------------------------------------------------------------------------
175 /* NIC global capabilities.
178 #define TLV_TAG_GLOBAL_CAPABILITIES (0x00010000)
180 struct tlv_global_capabilities {
187 /* Siena-style per-port MAC address allocation.
189 * There are <count> addresses, starting at <base_address> and incrementing
190 * by adding <stride> to the low-order byte(s).
192 * (See also TLV_TAG_GLOBAL_MAC for an alternative, specifying a global pool
193 * of contiguous MAC addresses for the firmware to allocate as it sees fit.)
196 #define TLV_TAG_PORT_MAC(port) (0x00020000 + (port))
198 struct tlv_port_mac {
201 uint8_t base_address[6];
210 * This is the portion of VPD which is set at manufacturing time and not
211 * expected to change. It is formatted as a standard PCI VPD block. There are
212 * global and per-pf TLVs for this, the global TLV is new for Medford and is
213 * used in preference to the per-pf TLV.
216 #define TLV_TAG_PF_STATIC_VPD(pf) (0x00030000 + (pf))
218 struct tlv_pf_static_vpd {
224 #define TLV_TAG_GLOBAL_STATIC_VPD (0x001f0000)
226 struct tlv_global_static_vpd {
235 * This is the portion of VPD which may be changed (e.g. by firmware updates).
236 * It is formatted as a standard PCI VPD block. There are global and per-pf TLVs
237 * for this, the global TLV is new for Medford and is used in preference to the
241 #define TLV_TAG_PF_DYNAMIC_VPD(pf) (0x10030000 + (pf))
243 struct tlv_pf_dynamic_vpd {
249 #define TLV_TAG_GLOBAL_DYNAMIC_VPD (0x10200000)
251 struct tlv_global_dynamic_vpd {
258 /* "DBI" PCI config space changes.
260 * This is a set of edits made to the default PCI config space values before
261 * the device is allowed to enumerate. There are global and per-pf TLVs for
262 * this, the global TLV is new for Medford and is used in preference to the
266 #define TLV_TAG_PF_DBI(pf) (0x00040000 + (pf))
273 uint16_t byte_enables;
279 #define TLV_TAG_GLOBAL_DBI (0x00210000)
281 struct tlv_global_dbi {
286 uint16_t byte_enables;
292 /* Partition subtype codes.
294 * A subtype may optionally be stored for each type of partition present in
295 * the NVRAM. For example, this may be used to allow a generic firmware update
296 * utility to select a specific variant of firmware for a specific variant of
299 * The description[] field is an optional string which is returned in the
300 * MC_CMD_NVRAM_METADATA response if present.
303 #define TLV_TAG_PARTITION_SUBTYPE(type) (0x00050000 + (type))
305 struct tlv_partition_subtype {
309 uint8_t description[];
313 /* Partition version codes.
315 * A version may optionally be stored for each type of partition present in
316 * the NVRAM. This provides a standard way of tracking the currently stored
317 * version of each of the various component images.
320 #define TLV_TAG_PARTITION_VERSION(type) (0x10060000 + (type))
322 struct tlv_partition_version {
331 /* Global PCIe configuration */
333 #define TLV_TAG_GLOBAL_PCIE_CONFIG (0x10070000)
335 struct tlv_pcie_config {
338 int16_t max_pf_number; /**< Largest PF RID (lower PFs may be hidden) */
339 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
340 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
341 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
342 #define TLV_MAX_PF_DEFAULT (-1) /* Use FW default for largest PF RID */
343 #define TLV_APER_DEFAULT (0xFFFF) /* Use FW default for a given aperture */
346 /* Per-PF configuration. Note that not all these fields are necessarily useful
347 * as the apertures are constrained by the BIU settings (the one case we do
348 * use is to make BAR2 bigger than the BIU thinks to reserve space), but we can
349 * tidy things up later */
351 #define TLV_TAG_PF_PCIE_CONFIG(pf) (0x10080000 + (pf))
353 struct tlv_per_pf_pcie_config {
357 uint8_t port_allocation;
358 uint16_t vectors_per_pf;
359 uint16_t vectors_per_vf;
360 uint8_t pf_bar0_aperture;
361 uint8_t pf_bar2_aperture;
362 uint8_t vf_bar0_aperture;
364 uint16_t supp_pagesz;
365 uint16_t msix_vec_base;
369 /* Development ONLY. This is a single TLV tag for all the gubbins
370 * that can be set through the MC command-line other than the PCIe
371 * settings. This is a temporary measure. */
372 #define TLV_TAG_TMP_GUBBINS (0x10090000) /* legacy symbol - do not use */
373 #define TLV_TAG_TMP_GUBBINS_HUNT TLV_TAG_TMP_GUBBINS
375 struct tlv_tmp_gubbins {
378 /* Consumed by dpcpu.c */
379 uint64_t tx0_tags; /* Bitmap */
380 uint64_t tx1_tags; /* Bitmap */
381 uint64_t dl_tags; /* Bitmap */
383 #define TLV_DPCPU_TX_STRIPE (1) /* No longer used, has no effect */
384 #define TLV_DPCPU_BIU_TAGS (2) /* Use BIU tag manager */
385 #define TLV_DPCPU_TX0_TAGS (4) /* tx0_tags is valid */
386 #define TLV_DPCPU_TX1_TAGS (8) /* tx1_tags is valid */
387 #define TLV_DPCPU_DL_TAGS (16) /* dl_tags is valid */
388 /* Consumed by features.c */
389 uint32_t dut_features; /* All 1s -> leave alone */
390 int8_t with_rmon; /* 0 -> off, 1 -> on, -1 -> leave alone */
391 /* Consumed by clocks_hunt.c */
392 int8_t clk_mode; /* 0 -> off, 1 -> on, -1 -> leave alone */
393 /* No longer used, superseded by TLV_TAG_DESCRIPTOR_CACHE_CONFIG. */
394 int8_t rx_dc_size; /* -1 -> leave alone */
396 int16_t num_q_allocs;
399 /* Global port configuration
401 * This is now deprecated in favour of a platform-provided default
402 * and dynamic config override via tlv_global_port_options.
404 #define TLV_TAG_GLOBAL_PORT_CONFIG (0x000a0000)
406 struct tlv_global_port_config {
409 uint32_t ports_per_core;
410 uint32_t max_port_speed;
416 * This is intended for user-configurable selection of optional firmware
417 * features and variants.
419 * Initially, this consists only of the satellite CPU firmware variant
420 * selection, but this tag could be extended in the future (using the
421 * tag length to determine whether additional fields are present).
424 #define TLV_TAG_FIRMWARE_OPTIONS (0x100b0000)
426 struct tlv_firmware_options {
429 uint32_t firmware_variant;
430 #define TLV_FIRMWARE_VARIANT_DRIVER_SELECTED (0xffffffff)
432 /* These are the values for overriding the driver's choice; the definitions
433 * are taken from MCDI so that they don't get out of step. Include
434 * <ci/mgmt/mc_driver_pcol.h> or the equivalent from your driver's tree if
435 * you need to use these constants.
437 #define TLV_FIRMWARE_VARIANT_FULL_FEATURED MC_CMD_FW_FULL_FEATURED
438 #define TLV_FIRMWARE_VARIANT_LOW_LATENCY MC_CMD_FW_LOW_LATENCY
439 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM MC_CMD_FW_PACKED_STREAM
440 #define TLV_FIRMWARE_VARIANT_HIGH_TX_RATE MC_CMD_FW_HIGH_TX_RATE
441 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \
442 MC_CMD_FW_PACKED_STREAM_HASH_MODE_1
443 #define TLV_FIRMWARE_VARIANT_RULES_ENGINE MC_CMD_FW_RULES_ENGINE
444 #define TLV_FIRMWARE_VARIANT_DPDK MC_CMD_FW_DPDK
445 #define TLV_FIRMWARE_VARIANT_L3XUDP MC_CMD_FW_L3XUDP
450 * Intended for boards with A0 silicon where the core voltage may
451 * need tweaking. Most likely set once when the pass voltage is
454 #define TLV_TAG_0V9_SETTINGS (0x000c0000)
456 struct tlv_0v9_settings {
459 uint16_t flags; /* Boards with high 0v9 settings may need active cooling */
460 #define TLV_TAG_0V9_REQUIRES_FAN (1)
461 uint16_t target_voltage; /* In millivolts */
462 /* Since the limits are meant to be centred to the target (and must at least
463 * contain it) they need setting as well. */
464 uint16_t warn_low; /* In millivolts */
465 uint16_t warn_high; /* In millivolts */
466 uint16_t panic_low; /* In millivolts */
467 uint16_t panic_high; /* In millivolts */
471 /* Clock configuration */
473 #define TLV_TAG_CLOCK_CONFIG (0x000d0000) /* legacy symbol - do not use */
474 #define TLV_TAG_CLOCK_CONFIG_HUNT TLV_TAG_CLOCK_CONFIG
476 struct tlv_clock_config {
479 uint16_t clk_sys; /* MHz */
480 uint16_t clk_dpcpu; /* MHz */
481 uint16_t clk_icore; /* MHz */
482 uint16_t clk_pcs; /* MHz */
485 #define TLV_TAG_CLOCK_CONFIG_MEDFORD (0x00100000)
487 struct tlv_clock_config_medford {
490 uint16_t clk_sys; /* MHz */
491 uint16_t clk_mc; /* MHz */
492 uint16_t clk_rmon; /* MHz */
493 uint16_t clk_vswitch; /* MHz */
494 uint16_t clk_dpcpu; /* MHz */
495 uint16_t clk_pcs; /* MHz */
499 /* EF10-style global pool of MAC addresses.
501 * There are <count> addresses, starting at <base_address>, which are
502 * contiguous. Firmware is responsible for allocating addresses from this
503 * pool to ports / PFs as appropriate.
506 #define TLV_TAG_GLOBAL_MAC (0x000e0000)
508 struct tlv_global_mac {
511 uint8_t base_address[6];
517 #define TLV_TAG_ATB_0V9_TARGET (0x000f0000) /* legacy symbol - do not use */
518 #define TLV_TAG_ATB_0V9_TARGET_HUNT TLV_TAG_ATB_0V9_TARGET
520 /* The target value for the 0v9 power rail measured on-chip at the
521 * analogue test bus */
522 struct tlv_0v9_atb_target {
529 /* Factory settings for amplitude calibration of the PCIE TX serdes */
530 #define TLV_TAG_TX_PCIE_AMP_CONFIG (0x00220000)
531 struct tlv_pcie_tx_amp_config {
534 uint8_t quad_tx_imp2k[4];
535 uint8_t quad_tx_imp50[4];
536 uint8_t lane_amp[16];
539 /* Enum to select an OEM and enable additional functionality related to this OEM
540 * (e.g. vendor extensions to VPD, NC-SI etc.) */
541 #define TLV_TAG_OEM (0x00230000)
547 #define TLV_OEM_NONE 0
548 #define TLV_OEM_DELL 1
550 /* Global PCIe configuration, second revision. This represents the visible PFs
551 * by a bitmap rather than having the number of the highest visible one. As such
552 * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG
553 * can and it should be used in place of that tag in future (but compatibility with
554 * the old tag will be left in the firmware indefinitely). */
556 #define TLV_TAG_GLOBAL_PCIE_CONFIG_R2 (0x10100000)
558 struct tlv_pcie_config_r2 {
561 uint16_t visible_pfs; /**< Bitmap of visible PFs */
562 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
563 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
564 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
567 /* Dynamic port mode.
569 * Allows selecting alternate port configuration for platforms that support it
570 * (e.g. 1x40G vs 2x10G on Milano, 1x40G vs 4x10G on Medford). This affects the
571 * number of externally visible ports (and, hence, PF to port mapping), so must
572 * be done at boot time.
574 * Port mode naming convention is
576 * [nports_on_cage0]x[port_lane_width]_[nports_on_cage1]x[port_lane_width]
578 * Port lane width determines the capabilities (speeds) of the ports, subject
579 * to architecture capabilities (e.g. 25G support) and switch bandwidth
581 * - single lane ports can do 25G/10G/1G
582 * - dual lane ports can do 50G/25G/10G/1G (with fallback to 1 lane)
583 * - quad lane ports can do 100G/40G/50G/25G/10G/1G (with fallback to 2 or 1 lanes)
585 * This tag supercedes tlv_global_port_config.
588 #define TLV_TAG_GLOBAL_PORT_MODE (0x10110000)
590 struct tlv_global_port_mode {
594 #define TLV_PORT_MODE_DEFAULT (0xffffffff) /* Default for given platform */
596 /* Huntington port modes */
597 #define TLV_PORT_MODE_10G (0)
598 #define TLV_PORT_MODE_40G (1)
599 #define TLV_PORT_MODE_10G_10G (2)
600 #define TLV_PORT_MODE_40G_40G (3)
601 #define TLV_PORT_MODE_10G_10G_10G_10G (4)
602 #define TLV_PORT_MODE_40G_10G_10G (6)
603 #define TLV_PORT_MODE_10G_10G_40G (7)
605 /* Medford (and later) port modes */
606 #define TLV_PORT_MODE_1x1_NA (0) /* Single 10G/25G on mdi0 */
607 #define TLV_PORT_MODE_1x4_NA (1) /* Single 100G/40G on mdi0 */
608 #define TLV_PORT_MODE_NA_1x4 (22) /* Single 100G/40G on mdi1 */
609 #define TLV_PORT_MODE_1x2_NA (10) /* Single 50G on mdi0 */
610 #define TLV_PORT_MODE_NA_1x2 (11) /* Single 50G on mdi1 */
611 #define TLV_PORT_MODE_1x1_1x1 (2) /* Single 10G/25G on mdi0, single 10G/25G on mdi1 */
612 #define TLV_PORT_MODE_1x4_1x4 (3) /* Single 40G on mdi0, single 40G on mdi1 */
613 #define TLV_PORT_MODE_2x1_2x1 (5) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1 */
614 #define TLV_PORT_MODE_4x1_NA (4) /* Quad 10G/25G on mdi0 */
615 #define TLV_PORT_MODE_NA_4x1 (8) /* Quad 10G/25G on mdi1 */
616 #define TLV_PORT_MODE_1x4_2x1 (6) /* Single 40G on mdi0, dual 10G/25G on mdi1 */
617 #define TLV_PORT_MODE_2x1_1x4 (7) /* Dual 10G/25G on mdi0, single 40G on mdi1 */
618 #define TLV_PORT_MODE_1x2_1x2 (12) /* Single 50G on mdi0, single 50G on mdi1 */
619 #define TLV_PORT_MODE_2x2_NA (13) /* Dual 50G on mdi0 */
620 #define TLV_PORT_MODE_NA_2x2 (14) /* Dual 50G on mdi1 */
621 #define TLV_PORT_MODE_1x4_1x2 (15) /* Single 40G on mdi0, single 50G on mdi1 */
622 #define TLV_PORT_MODE_1x2_1x4 (16) /* Single 50G on mdi0, single 40G on mdi1 */
623 #define TLV_PORT_MODE_1x2_2x1 (17) /* Single 50G on mdi0, dual 10G/25G on mdi1 */
624 #define TLV_PORT_MODE_2x1_1x2 (18) /* Dual 10G/25G on mdi0, single 50G on mdi1 */
626 /* Snapper-only Medford2 port modes.
627 * These modes are eftest only, to allow snapper explicit
628 * selection between multi-channel and LLPCS. In production,
629 * this selection is automatic and outside world should not
632 #define TLV_PORT_MODE_2x1_2x1_LL (19) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1, low-latency PCS */
633 #define TLV_PORT_MODE_4x1_NA_LL (20) /* Quad 10G/25G on mdi0, low-latency PCS */
634 #define TLV_PORT_MODE_NA_4x1_LL (21) /* Quad 10G/25G on mdi1, low-latency PCS */
635 #define TLV_PORT_MODE_1x1_NA_LL (23) /* Single 10G/25G on mdi0, low-latency PCS */
636 #define TLV_PORT_MODE_1x1_1x1_LL (24) /* Single 10G/25G on mdi0, single 10G/25G on mdi1, low-latency PCS */
637 #define TLV_PORT_MODE_BUG63720_DO_NOT_USE (9) /* bug63720: Do not use */
638 #define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL
640 /* Deprecated Medford aliases - DO NOT USE IN NEW CODE */
641 #define TLV_PORT_MODE_10G_10G_10G_10G_Q (5)
642 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1 (4)
643 #define TLV_PORT_MODE_10G_10G_10G_10G_Q2 (8)
644 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2 (9)
646 #define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL
649 /* Type of the v-switch created implicitly by the firmware */
651 #define TLV_TAG_VSWITCH_TYPE(port) (0x10120000 + (port))
653 struct tlv_vswitch_type {
656 uint32_t vswitch_type;
657 #define TLV_VSWITCH_TYPE_DEFAULT (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */
658 #define TLV_VSWITCH_TYPE_NONE (0)
659 #define TLV_VSWITCH_TYPE_VLAN (1)
660 #define TLV_VSWITCH_TYPE_VEB (2)
661 #define TLV_VSWITCH_TYPE_VEPA (3)
662 #define TLV_VSWITCH_TYPE_MUX (4)
663 #define TLV_VSWITCH_TYPE_TEST (5)
666 /* A VLAN tag for the v-port created implicitly by the firmware */
668 #define TLV_TAG_VPORT_VLAN_TAG(pf) (0x10130000 + (pf))
670 struct tlv_vport_vlan_tag {
674 #define TLV_VPORT_NO_VLAN_TAG (0xFFFFFFFF) /* Default in the absence of TLV for a given PF */
677 /* Offset to be applied to the 0v9 setting, wherever it came from */
679 #define TLV_TAG_ATB_0V9_OFFSET (0x10140000)
681 struct tlv_0v9_atb_offset {
684 int16_t offset_millivolts;
688 /* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per-port).
689 * The meaning of particular bits is defined in mcdi_ef10.yml under MC_CMD_PRIVILEGE_MASK, see also bug 44583.
690 * TLV_TAG_PRIVILEGE_MASK_ADD specifies bits that should be added (ORed) to firmware default while
691 * TLV_TAG_PRIVILEGE_MASK_REM specifies bits that should be removed (ANDed) from firmware default:
692 * Initial_privilege_mask = (firmware_default_mask | privilege_mask_add) & ~privilege_mask_rem */
694 #define TLV_TAG_PRIVILEGE_MASK (0x10150000) /* legacy symbol - do not use */
696 struct tlv_privilege_mask { /* legacy structure - do not use */
699 uint32_t privilege_mask;
702 #define TLV_TAG_PRIVILEGE_MASK_ADD (0x10150000)
704 struct tlv_privilege_mask_add {
707 uint32_t privilege_mask_add;
710 #define TLV_TAG_PRIVILEGE_MASK_REM (0x10160000)
712 struct tlv_privilege_mask_rem {
715 uint32_t privilege_mask_rem;
718 /* Additional privileges given to all PFs.
719 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
721 #define TLV_TAG_PRIVILEGE_MASK_ADD_ALL_PFS (0x10190000)
723 struct tlv_privilege_mask_add_all_pfs {
726 uint32_t privilege_mask_add;
729 /* Additional privileges given to a selected PF.
730 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
732 #define TLV_TAG_PRIVILEGE_MASK_ADD_SINGLE_PF(pf) (0x101A0000 + (pf))
734 struct tlv_privilege_mask_add_single_pf {
737 uint32_t privilege_mask_add;
740 /* Turning on/off the PFIOV mode.
741 * This tag only takes effect if TLV_TAG_VSWITCH_TYPE is missing or set to DEFAULT. */
743 #define TLV_TAG_PFIOV(port) (0x10170000 + (port))
749 #define TLV_PFIOV_OFF (0) /* Default */
750 #define TLV_PFIOV_ON (1)
753 /* Multicast filter chaining mode selection.
755 * When enabled, multicast packets are delivered to all recipients of all
756 * matching multicast filters, with the exception that IP multicast filters
757 * will steal traffic from MAC multicast filters on a per-function basis.
760 * When disabled, multicast packets will always be delivered only to the
761 * recipients of the highest priority matching multicast filter.
762 * (Legacy behaviour.)
764 * The DEFAULT mode (which is the same as the tag not being present at all)
765 * is equivalent to ENABLED in production builds, and DISABLED in eftest
768 * This option is intended to provide run-time control over this feature
769 * while it is being stabilised and may be withdrawn at some point in the
770 * future; the new behaviour is intended to become the standard behaviour.
773 #define TLV_TAG_MCAST_FILTER_CHAINING (0x10180000)
775 struct tlv_mcast_filter_chaining {
779 #define TLV_MCAST_FILTER_CHAINING_DEFAULT (0xffffffff)
780 #define TLV_MCAST_FILTER_CHAINING_DISABLED (0)
781 #define TLV_MCAST_FILTER_CHAINING_ENABLED (1)
784 /* Pacer rate limit per PF */
785 #define TLV_TAG_RATE_LIMIT(pf) (0x101b0000 + (pf))
787 struct tlv_rate_limit {
793 /* OCSD Enable/Disable
795 * This setting allows OCSD to be disabled. This is a requirement for HP
796 * servers to support PCI passthrough for virtualization.
798 * The DEFAULT mode (which is the same as the tag not being present) is
799 * equivalent to ENABLED.
801 * This option is not used by the MCFW, and is entirely handled by the various
802 * drivers that support OCSD, by reading the setting before they attempt
805 * bit0: OCSD Disabled/Enabled
808 #define TLV_TAG_OCSD (0x101C0000)
814 #define TLV_OCSD_DISABLED 0
815 #define TLV_OCSD_ENABLED 1 /* Default */
818 /* Descriptor cache config.
820 * Sets the sizes of the TX and RX descriptor caches as a power of 2. It also
821 * sets the total number of VIs. When the number of VIs is reduced VIs are taken
822 * away from the highest numbered port first, so a vi_count of 1024 means 1024
823 * VIs on the first port and 0 on the second (on a Torino).
826 #define TLV_TAG_DESCRIPTOR_CACHE_CONFIG (0x101d0000)
828 struct tlv_descriptor_cache_config {
831 uint8_t rx_desc_cache_size;
832 uint8_t tx_desc_cache_size;
835 #define TLV_DESC_CACHE_DEFAULT (0xff)
836 #define TLV_VI_COUNT_DEFAULT (0xffff)
838 /* RX event merging config (read batching).
840 * Sets the global maximum number of events for the merging bins, and the
841 * global timeout configuration for the bins.
844 #define TLV_TAG_RX_EVENT_MERGING_CONFIG (0x101e0000)
846 struct tlv_rx_event_merging_config {
850 #define TLV_RX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
853 #define TLV_RX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff)
854 #define TLV_RX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff)
856 #define TLV_TAG_PCIE_LINK_SETTINGS (0x101f0000)
857 struct tlv_pcie_link_settings {
860 uint16_t gen; /* Target PCIe generation: 1, 2, 3 */
861 uint16_t width; /* Number of lanes */
864 /* TX event merging config.
866 * Sets the global maximum number of events for the merging bins, and the
867 * global timeout configuration for the bins, and the global timeout for
870 #define TLV_TAG_TX_EVENT_MERGING_CONFIG (0x10210000)
871 struct tlv_tx_event_merging_config {
875 #define TLV_TX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
877 uint32_t qempty_timeout_ns; /* Medford only */
879 #define TLV_TX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff)
880 #define TLV_TX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff)
881 #define TLV_TX_EVENT_MERGING_QEMPTY_TIMEOUT_NS_DEFAULT (0xffffffff)
883 #define TLV_TAG_LICENSE (0x30800000)
885 typedef struct tlv_license {
891 /* TSA NIC IP address configuration (DEPRECATED)
893 * Sets the TSA NIC IP address statically via configuration tool or dynamically
894 * via DHCP via snooping based on the mode selection (0=Static, 1=DHCP, 2=Snoop)
896 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
897 * be moved to a private partition during TSA development. It is not used in any
901 #define TLV_TAG_TMP_TSAN_CONFIG (0x10220000) /* DEPRECATED */
903 #define TLV_TSAN_IP_MODE_STATIC (0)
904 #define TLV_TSAN_IP_MODE_DHCP (1)
905 #define TLV_TSAN_IP_MODE_SNOOP (2)
906 typedef struct tlv_tsan_config {
914 uint32_t bind_retry; /* DEPRECATED */
915 uint32_t bind_bkout; /* DEPRECATED */
918 /* TSA Controller IP address configuration (DEPRECATED)
920 * Sets the TSA Controller IP address statically via configuration tool
922 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
923 * be moved to a private partition during TSA development. It is not used in any
927 #define TLV_TAG_TMP_TSAC_CONFIG (0x10230000) /* DEPRECATED */
929 #define TLV_MAX_TSACS (4)
930 typedef struct tlv_tsac_config {
934 uint32_t ip[TLV_MAX_TSACS];
935 uint32_t port[TLV_MAX_TSACS];
938 /* Binding ticket (DEPRECATED)
940 * Sets the TSA NIC binding ticket used for binding process between the TSA NIC
941 * and the TSA Controller
943 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
944 * be moved to a private partition during TSA development. It is not used in any
948 #define TLV_TAG_TMP_BINDING_TICKET (0x10240000) /* DEPRECATED */
950 typedef struct tlv_binding_ticket {
954 } tlv_binding_ticket_t;
956 /* Solarflare private key (DEPRECATED)
958 * Sets the Solareflare private key used for signing during the binding process
960 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
961 * be moved to a private partition during TSA development. It is not used in any
965 #define TLV_TAG_TMP_PIK_SF (0x10250000) /* DEPRECATED */
967 typedef struct tlv_pik_sf {
973 /* CA root certificate (DEPRECATED)
975 * Sets the CA root certificate used for TSA Controller verfication during
976 * TLS connection setup between the TSA NIC and the TSA Controller
978 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
979 * be moved to a private partition during TSA development. It is not used in any
983 #define TLV_TAG_TMP_CA_ROOT_CERT (0x10260000) /* DEPRECATED */
985 typedef struct tlv_ca_root_cert {
989 } tlv_ca_root_cert_t;
991 /* Tx vFIFO Low latency configuration
993 * To keep the desired booting behaviour for the switch, it just requires to
994 * know if the low latency mode is enabled.
997 #define TLV_TAG_TX_VFIFO_ULL_MODE (0x10270000)
998 struct tlv_tx_vfifo_ull_mode {
1002 #define TLV_TX_VFIFO_ULL_MODE_DEFAULT 0
1007 * Medford2 tag for selecting VI window decode (see values below)
1009 #define TLV_TAG_BIU_VI_WINDOW_MODE (0x10280000)
1010 struct tlv_biu_vi_window_mode {
1014 #define TLV_BIU_VI_WINDOW_MODE_8K 0 /* 8k per VI, CTPIO not mapped, medford/hunt compatible */
1015 #define TLV_BIU_VI_WINDOW_MODE_16K 1 /* 16k per VI, CTPIO mapped */
1016 #define TLV_BIU_VI_WINDOW_MODE_64K 2 /* 64k per VI, CTPIO mapped, POWER-friendly */
1021 * Medford2 tag for configuring the FastPD mode (see values below)
1023 #define TLV_TAG_FASTPD_MODE(port) (0x10290000 + (port))
1024 struct tlv_fastpd_mode {
1028 #define TLV_FASTPD_MODE_SOFT_ALL 0 /* All packets to the SoftPD */
1029 #define TLV_FASTPD_MODE_FAST_ALL 1 /* All packets to the FastPD */
1030 #define TLV_FASTPD_MODE_FAST_SUPPORTED 2 /* Supported packet types to the FastPD; everything else to the SoftPD */
1033 /* L3xUDP datapath firmware UDP port configuration
1035 * Sets the list of UDP ports on which the encapsulation will be handled.
1036 * The number of ports in the list is implied by the length of the TLV item.
1038 #define TLV_TAG_L3XUDP_PORTS (0x102a0000)
1039 struct tlv_l3xudp_ports {
1043 #define TLV_TAG_L3XUDP_PORTS_MAX_NUM_PORTS 16
1046 /* Wake on LAN setting
1048 * Enables the Wake On Lan (WoL) functionality on the given port. This will be
1049 * a persistent setting for manageability firmware. Drivers have direct access
1050 * to WoL using MCDI.
1052 #define TLV_TAG_WAKE_ON_LAN(port) (0x102b0000 + (port))
1053 struct tlv_wake_on_lan {
1058 #define TLV_WAKE_ON_LAN_MODE_DISABLED 0
1059 #define TLV_WAKE_ON_LAN_MODE_MAGIC_PACKET 1
1060 #define TLV_WAKE_ON_LAN_MAX_NUM_BYTES 255
1063 #endif /* CI_MGMT_TLV_LAYOUT_H */