1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2006-2018 Solarflare Communications Inc.
10 #include "efx_annote.h"
12 #include "efx_types.h"
13 #include "efx_check.h"
14 #include "efx_phy_ids.h"
20 #define EFX_STATIC_ASSERT(_cond) \
21 ((void)sizeof (char[(_cond) ? 1 : -1]))
23 #define EFX_ARRAY_SIZE(_array) \
24 (sizeof (_array) / sizeof ((_array)[0]))
26 #define EFX_FIELD_OFFSET(_type, _field) \
27 ((size_t)&(((_type *)0)->_field))
29 /* The macro expands divider twice */
30 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 /* Round value up to the nearest power of two. */
33 #define EFX_P2ROUNDUP(_type, _value, _align) \
34 (-(-(_type)(_value) & -(_type)(_align)))
36 /* Align value down to the nearest power of two. */
37 #define EFX_P2ALIGN(_type, _value, _align) \
38 ((_type)(_value) & -(_type)(_align))
40 /* Test if value is power of 2 aligned. */
41 #define EFX_IS_P2ALIGNED(_type, _value, _align) \
42 ((((_type)(_value)) & ((_type)(_align) - 1)) == 0)
46 typedef __success(return == 0) int efx_rc_t;
51 typedef enum efx_family_e {
53 EFX_FAMILY_FALCON, /* Obsolete and not supported */
55 EFX_FAMILY_HUNTINGTON,
61 extern __checkReturn efx_rc_t
65 __out efx_family_t *efp,
66 __out unsigned int *membarp);
69 #define EFX_PCI_VENID_SFC 0x1924
71 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
73 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
74 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
75 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
77 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
78 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
79 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
81 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
82 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
84 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
85 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
86 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
88 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
89 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
90 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
93 #define EFX_MEM_BAR_SIENA 2
95 #define EFX_MEM_BAR_HUNTINGTON_PF 2
96 #define EFX_MEM_BAR_HUNTINGTON_VF 0
98 #define EFX_MEM_BAR_MEDFORD_PF 2
99 #define EFX_MEM_BAR_MEDFORD_VF 0
101 #define EFX_MEM_BAR_MEDFORD2 0
109 EFX_ERR_BUFID_DC_OOB,
122 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
123 extern __checkReturn uint32_t
125 __in uint32_t crc_init,
126 __in_ecount(length) uint8_t const *input,
130 /* Type prototypes */
132 typedef struct efx_rxq_s efx_rxq_t;
136 typedef struct efx_nic_s efx_nic_t;
138 extern __checkReturn efx_rc_t
140 __in efx_family_t family,
141 __in efsys_identifier_t *esip,
142 __in efsys_bar_t *esbp,
143 __in efsys_lock_t *eslp,
144 __deref_out efx_nic_t **enpp);
146 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
147 typedef enum efx_fw_variant_e {
148 EFX_FW_VARIANT_FULL_FEATURED,
149 EFX_FW_VARIANT_LOW_LATENCY,
150 EFX_FW_VARIANT_PACKED_STREAM,
151 EFX_FW_VARIANT_HIGH_TX_RATE,
152 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
153 EFX_FW_VARIANT_RULES_ENGINE,
155 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
158 extern __checkReturn efx_rc_t
161 __in efx_fw_variant_t efv);
163 extern __checkReturn efx_rc_t
165 __in efx_nic_t *enp);
167 extern __checkReturn efx_rc_t
169 __in efx_nic_t *enp);
171 extern __checkReturn boolean_t
172 efx_nic_hw_unavailable(
173 __in efx_nic_t *enp);
176 efx_nic_set_hw_unavailable(
177 __in efx_nic_t *enp);
181 extern __checkReturn efx_rc_t
182 efx_nic_register_test(
183 __in efx_nic_t *enp);
185 #endif /* EFSYS_OPT_DIAG */
189 __in efx_nic_t *enp);
193 __in efx_nic_t *enp);
197 __in efx_nic_t *enp);
199 #define EFX_PCIE_LINK_SPEED_GEN1 1
200 #define EFX_PCIE_LINK_SPEED_GEN2 2
201 #define EFX_PCIE_LINK_SPEED_GEN3 3
203 typedef enum efx_pcie_link_performance_e {
204 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
205 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
206 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
207 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
208 } efx_pcie_link_performance_t;
210 extern __checkReturn efx_rc_t
211 efx_nic_calculate_pcie_link_bandwidth(
212 __in uint32_t pcie_link_width,
213 __in uint32_t pcie_link_gen,
214 __out uint32_t *bandwidth_mbpsp);
216 extern __checkReturn efx_rc_t
217 efx_nic_check_pcie_link_speed(
219 __in uint32_t pcie_link_width,
220 __in uint32_t pcie_link_gen,
221 __out efx_pcie_link_performance_t *resultp);
226 /* EF10 architecture NICs require MCDIv2 commands */
227 #define WITH_MCDI_V2 1
230 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
232 typedef enum efx_mcdi_exception_e {
233 EFX_MCDI_EXCEPTION_MC_REBOOT,
234 EFX_MCDI_EXCEPTION_MC_BADASSERT,
235 } efx_mcdi_exception_t;
237 #if EFSYS_OPT_MCDI_LOGGING
238 typedef enum efx_log_msg_e {
240 EFX_LOG_MCDI_REQUEST,
241 EFX_LOG_MCDI_RESPONSE,
243 #endif /* EFSYS_OPT_MCDI_LOGGING */
245 typedef struct efx_mcdi_transport_s {
247 efsys_mem_t *emt_dma_mem;
248 void (*emt_execute)(void *, efx_mcdi_req_t *);
249 void (*emt_ev_cpl)(void *);
250 void (*emt_exception)(void *, efx_mcdi_exception_t);
251 #if EFSYS_OPT_MCDI_LOGGING
252 void (*emt_logger)(void *, efx_log_msg_t,
253 void *, size_t, void *, size_t);
254 #endif /* EFSYS_OPT_MCDI_LOGGING */
255 #if EFSYS_OPT_MCDI_PROXY_AUTH
256 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
257 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
258 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
259 void (*emt_ev_proxy_request)(void *, uint32_t);
260 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
261 } efx_mcdi_transport_t;
263 extern __checkReturn efx_rc_t
266 __in const efx_mcdi_transport_t *mtp);
268 extern __checkReturn efx_rc_t
270 __in efx_nic_t *enp);
274 __in efx_nic_t *enp);
277 efx_mcdi_get_timeout(
279 __in efx_mcdi_req_t *emrp,
280 __out uint32_t *usec_timeoutp);
283 efx_mcdi_request_start(
285 __in efx_mcdi_req_t *emrp,
286 __in boolean_t ev_cpl);
288 extern __checkReturn boolean_t
289 efx_mcdi_request_poll(
290 __in efx_nic_t *enp);
292 extern __checkReturn boolean_t
293 efx_mcdi_request_abort(
294 __in efx_nic_t *enp);
298 __in efx_nic_t *enp);
300 #endif /* EFSYS_OPT_MCDI */
304 #define EFX_NINTR_SIENA 1024
306 typedef enum efx_intr_type_e {
307 EFX_INTR_INVALID = 0,
313 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
315 extern __checkReturn efx_rc_t
318 __in efx_intr_type_t type,
319 __in_opt efsys_mem_t *esmp);
323 __in efx_nic_t *enp);
327 __in efx_nic_t *enp);
330 efx_intr_disable_unlocked(
331 __in efx_nic_t *enp);
333 #define EFX_INTR_NEVQS 32
335 extern __checkReturn efx_rc_t
338 __in unsigned int level);
341 efx_intr_status_line(
343 __out boolean_t *fatalp,
344 __out uint32_t *maskp);
347 efx_intr_status_message(
349 __in unsigned int message,
350 __out boolean_t *fatalp);
354 __in efx_nic_t *enp);
358 __in efx_nic_t *enp);
362 #if EFSYS_OPT_MAC_STATS
364 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
365 typedef enum efx_mac_stat_e {
368 EFX_MAC_RX_UNICST_PKTS,
369 EFX_MAC_RX_MULTICST_PKTS,
370 EFX_MAC_RX_BRDCST_PKTS,
371 EFX_MAC_RX_PAUSE_PKTS,
372 EFX_MAC_RX_LE_64_PKTS,
373 EFX_MAC_RX_65_TO_127_PKTS,
374 EFX_MAC_RX_128_TO_255_PKTS,
375 EFX_MAC_RX_256_TO_511_PKTS,
376 EFX_MAC_RX_512_TO_1023_PKTS,
377 EFX_MAC_RX_1024_TO_15XX_PKTS,
378 EFX_MAC_RX_GE_15XX_PKTS,
380 EFX_MAC_RX_FCS_ERRORS,
381 EFX_MAC_RX_DROP_EVENTS,
382 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
383 EFX_MAC_RX_SYMBOL_ERRORS,
384 EFX_MAC_RX_ALIGN_ERRORS,
385 EFX_MAC_RX_INTERNAL_ERRORS,
386 EFX_MAC_RX_JABBER_PKTS,
387 EFX_MAC_RX_LANE0_CHAR_ERR,
388 EFX_MAC_RX_LANE1_CHAR_ERR,
389 EFX_MAC_RX_LANE2_CHAR_ERR,
390 EFX_MAC_RX_LANE3_CHAR_ERR,
391 EFX_MAC_RX_LANE0_DISP_ERR,
392 EFX_MAC_RX_LANE1_DISP_ERR,
393 EFX_MAC_RX_LANE2_DISP_ERR,
394 EFX_MAC_RX_LANE3_DISP_ERR,
395 EFX_MAC_RX_MATCH_FAULT,
396 EFX_MAC_RX_NODESC_DROP_CNT,
399 EFX_MAC_TX_UNICST_PKTS,
400 EFX_MAC_TX_MULTICST_PKTS,
401 EFX_MAC_TX_BRDCST_PKTS,
402 EFX_MAC_TX_PAUSE_PKTS,
403 EFX_MAC_TX_LE_64_PKTS,
404 EFX_MAC_TX_65_TO_127_PKTS,
405 EFX_MAC_TX_128_TO_255_PKTS,
406 EFX_MAC_TX_256_TO_511_PKTS,
407 EFX_MAC_TX_512_TO_1023_PKTS,
408 EFX_MAC_TX_1024_TO_15XX_PKTS,
409 EFX_MAC_TX_GE_15XX_PKTS,
411 EFX_MAC_TX_SGL_COL_PKTS,
412 EFX_MAC_TX_MULT_COL_PKTS,
413 EFX_MAC_TX_EX_COL_PKTS,
414 EFX_MAC_TX_LATE_COL_PKTS,
416 EFX_MAC_TX_EX_DEF_PKTS,
417 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
418 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
419 EFX_MAC_PM_TRUNC_VFIFO_FULL,
420 EFX_MAC_PM_DISCARD_VFIFO_FULL,
421 EFX_MAC_PM_TRUNC_QBB,
422 EFX_MAC_PM_DISCARD_QBB,
423 EFX_MAC_PM_DISCARD_MAPPING,
424 EFX_MAC_RXDP_Q_DISABLED_PKTS,
425 EFX_MAC_RXDP_DI_DROPPED_PKTS,
426 EFX_MAC_RXDP_STREAMING_PKTS,
427 EFX_MAC_RXDP_HLB_FETCH,
428 EFX_MAC_RXDP_HLB_WAIT,
429 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
430 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
431 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
432 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
433 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
434 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
435 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
436 EFX_MAC_VADAPTER_RX_BAD_BYTES,
437 EFX_MAC_VADAPTER_RX_OVERFLOW,
438 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
439 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
440 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
441 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
442 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
443 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
444 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
445 EFX_MAC_VADAPTER_TX_BAD_BYTES,
446 EFX_MAC_VADAPTER_TX_OVERFLOW,
447 EFX_MAC_FEC_UNCORRECTED_ERRORS,
448 EFX_MAC_FEC_CORRECTED_ERRORS,
449 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
450 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
451 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
452 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
453 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
454 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
455 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
456 EFX_MAC_CTPIO_OVERFLOW_FAIL,
457 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
458 EFX_MAC_CTPIO_TIMEOUT_FAIL,
459 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
460 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
461 EFX_MAC_CTPIO_INVALID_WR_FAIL,
462 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
463 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
464 EFX_MAC_CTPIO_RUNT_FALLBACK,
465 EFX_MAC_CTPIO_SUCCESS,
466 EFX_MAC_CTPIO_FALLBACK,
467 EFX_MAC_CTPIO_POISON,
469 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
470 EFX_MAC_RXDP_HLB_IDLE,
471 EFX_MAC_RXDP_HLB_TIMEOUT,
475 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
477 #endif /* EFSYS_OPT_MAC_STATS */
479 typedef enum efx_link_mode_e {
480 EFX_LINK_UNKNOWN = 0,
496 #define EFX_MAC_ADDR_LEN 6
498 #define EFX_VNI_OR_VSID_LEN 3
500 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
502 #define EFX_MAC_MULTICAST_LIST_MAX 256
504 #define EFX_MAC_SDU_MAX 9202
506 #define EFX_MAC_PDU_ADJUSTMENT \
510 + /* bug16011 */ 16) \
512 #define EFX_MAC_PDU(_sdu) \
513 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
516 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
517 * the SDU rounded up slightly.
519 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
521 #define EFX_MAC_PDU_MIN 60
522 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
524 extern __checkReturn efx_rc_t
529 extern __checkReturn efx_rc_t
534 extern __checkReturn efx_rc_t
539 extern __checkReturn efx_rc_t
542 __in boolean_t all_unicst,
543 __in boolean_t mulcst,
544 __in boolean_t all_mulcst,
545 __in boolean_t brdcst);
547 extern __checkReturn efx_rc_t
548 efx_mac_multicast_list_set(
550 __in_ecount(6*count) uint8_t const *addrs,
553 extern __checkReturn efx_rc_t
554 efx_mac_filter_default_rxq_set(
557 __in boolean_t using_rss);
560 efx_mac_filter_default_rxq_clear(
561 __in efx_nic_t *enp);
563 extern __checkReturn efx_rc_t
566 __in boolean_t enabled);
568 extern __checkReturn efx_rc_t
571 __out boolean_t *mac_upp);
573 #define EFX_FCNTL_RESPOND 0x00000001
574 #define EFX_FCNTL_GENERATE 0x00000002
576 extern __checkReturn efx_rc_t
579 __in unsigned int fcntl,
580 __in boolean_t autoneg);
585 __out unsigned int *fcntl_wantedp,
586 __out unsigned int *fcntl_linkp);
589 #if EFSYS_OPT_MAC_STATS
593 extern __checkReturn const char *
596 __in unsigned int id);
598 #endif /* EFSYS_OPT_NAMES */
600 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
602 #define EFX_MAC_STATS_MASK_NPAGES \
603 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \
604 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
605 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
608 * Get mask of MAC statistics supported by the hardware.
610 * If mask_size is insufficient to return the mask, EINVAL error is
611 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
612 * (which is sizeof (uint32_t)) is sufficient.
614 extern __checkReturn efx_rc_t
615 efx_mac_stats_get_mask(
617 __out_bcount(mask_size) uint32_t *maskp,
618 __in size_t mask_size);
620 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
621 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
622 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
625 extern __checkReturn efx_rc_t
627 __in efx_nic_t *enp);
630 * Upload mac statistics supported by the hardware into the given buffer.
632 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
633 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
635 * The hardware will only DMA statistics that it understands (of course).
636 * Drivers should not make any assumptions about which statistics are
637 * supported, especially when the statistics are generated by firmware.
639 * Thus, drivers should zero this buffer before use, so that not-understood
640 * statistics read back as zero.
642 extern __checkReturn efx_rc_t
643 efx_mac_stats_upload(
645 __in efsys_mem_t *esmp);
647 extern __checkReturn efx_rc_t
648 efx_mac_stats_periodic(
650 __in efsys_mem_t *esmp,
651 __in uint16_t period_ms,
652 __in boolean_t events);
654 extern __checkReturn efx_rc_t
655 efx_mac_stats_update(
657 __in efsys_mem_t *esmp,
658 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
659 __inout_opt uint32_t *generationp);
661 #endif /* EFSYS_OPT_MAC_STATS */
665 typedef enum efx_mon_type_e {
677 __in efx_nic_t *enp);
679 #endif /* EFSYS_OPT_NAMES */
681 extern __checkReturn efx_rc_t
683 __in efx_nic_t *enp);
685 #if EFSYS_OPT_MON_STATS
687 #define EFX_MON_STATS_PAGE_SIZE 0x100
688 #define EFX_MON_MASK_ELEMENT_SIZE 32
690 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
691 typedef enum efx_mon_stat_e {
692 EFX_MON_STAT_CONTROLLER_TEMP,
693 EFX_MON_STAT_PHY_COMMON_TEMP,
694 EFX_MON_STAT_CONTROLLER_COOLING,
695 EFX_MON_STAT_PHY0_TEMP,
696 EFX_MON_STAT_PHY0_COOLING,
697 EFX_MON_STAT_PHY1_TEMP,
698 EFX_MON_STAT_PHY1_COOLING,
704 EFX_MON_STAT_IN_12V0,
705 EFX_MON_STAT_IN_1V2A,
706 EFX_MON_STAT_IN_VREF,
707 EFX_MON_STAT_OUT_VAOE,
708 EFX_MON_STAT_AOE_TEMP,
709 EFX_MON_STAT_PSU_AOE_TEMP,
710 EFX_MON_STAT_PSU_TEMP,
716 EFX_MON_STAT_IN_VAOE,
717 EFX_MON_STAT_OUT_IAOE,
718 EFX_MON_STAT_IN_IAOE,
719 EFX_MON_STAT_NIC_POWER,
721 EFX_MON_STAT_IN_I0V9,
722 EFX_MON_STAT_IN_I1V2,
723 EFX_MON_STAT_IN_0V9_ADC,
724 EFX_MON_STAT_CONTROLLER_2_TEMP,
725 EFX_MON_STAT_VREG_INTERNAL_TEMP,
726 EFX_MON_STAT_VREG_0V9_TEMP,
727 EFX_MON_STAT_VREG_1V2_TEMP,
728 EFX_MON_STAT_CONTROLLER_VPTAT,
729 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
730 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
731 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
732 EFX_MON_STAT_AMBIENT_TEMP,
733 EFX_MON_STAT_AIRFLOW,
734 EFX_MON_STAT_VDD08D_VSS08D_CSR,
735 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
736 EFX_MON_STAT_HOTPOINT_TEMP,
737 EFX_MON_STAT_PHY_POWER_PORT0,
738 EFX_MON_STAT_PHY_POWER_PORT1,
739 EFX_MON_STAT_MUM_VCC,
740 EFX_MON_STAT_IN_0V9_A,
741 EFX_MON_STAT_IN_I0V9_A,
742 EFX_MON_STAT_VREG_0V9_A_TEMP,
743 EFX_MON_STAT_IN_0V9_B,
744 EFX_MON_STAT_IN_I0V9_B,
745 EFX_MON_STAT_VREG_0V9_B_TEMP,
746 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
747 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
748 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
749 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
750 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
751 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
752 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
753 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
754 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
755 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
756 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
757 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
758 EFX_MON_STAT_SODIMM_VOUT,
759 EFX_MON_STAT_SODIMM_0_TEMP,
760 EFX_MON_STAT_SODIMM_1_TEMP,
761 EFX_MON_STAT_PHY0_VCC,
762 EFX_MON_STAT_PHY1_VCC,
763 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
764 EFX_MON_STAT_BOARD_FRONT_TEMP,
765 EFX_MON_STAT_BOARD_BACK_TEMP,
766 EFX_MON_STAT_IN_I1V8,
767 EFX_MON_STAT_IN_I2V5,
768 EFX_MON_STAT_IN_I3V3,
769 EFX_MON_STAT_IN_I12V0,
771 EFX_MON_STAT_IN_I1V3,
775 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
777 typedef enum efx_mon_stat_state_e {
778 EFX_MON_STAT_STATE_OK = 0,
779 EFX_MON_STAT_STATE_WARNING = 1,
780 EFX_MON_STAT_STATE_FATAL = 2,
781 EFX_MON_STAT_STATE_BROKEN = 3,
782 EFX_MON_STAT_STATE_NO_READING = 4,
783 } efx_mon_stat_state_t;
785 typedef enum efx_mon_stat_unit_e {
786 EFX_MON_STAT_UNIT_UNKNOWN = 0,
787 EFX_MON_STAT_UNIT_BOOL,
788 EFX_MON_STAT_UNIT_TEMP_C,
789 EFX_MON_STAT_UNIT_VOLTAGE_MV,
790 EFX_MON_STAT_UNIT_CURRENT_MA,
791 EFX_MON_STAT_UNIT_POWER_W,
792 EFX_MON_STAT_UNIT_RPM,
794 } efx_mon_stat_unit_t;
796 typedef struct efx_mon_stat_value_s {
798 efx_mon_stat_state_t emsv_state;
799 efx_mon_stat_unit_t emsv_unit;
800 } efx_mon_stat_value_t;
802 typedef struct efx_mon_limit_value_s {
803 uint16_t emlv_warning_min;
804 uint16_t emlv_warning_max;
805 uint16_t emlv_fatal_min;
806 uint16_t emlv_fatal_max;
807 } efx_mon_stat_limits_t;
809 typedef enum efx_mon_stat_portmask_e {
810 EFX_MON_STAT_PORTMAP_NONE = 0,
811 EFX_MON_STAT_PORTMAP_PORT0 = 1,
812 EFX_MON_STAT_PORTMAP_PORT1 = 2,
813 EFX_MON_STAT_PORTMAP_PORT2 = 3,
814 EFX_MON_STAT_PORTMAP_PORT3 = 4,
815 EFX_MON_STAT_PORTMAP_ALL = (-1),
816 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
817 } efx_mon_stat_portmask_t;
824 __in efx_mon_stat_t id);
827 efx_mon_stat_description(
829 __in efx_mon_stat_t id);
831 #endif /* EFSYS_OPT_NAMES */
833 extern __checkReturn boolean_t
834 efx_mon_mcdi_to_efx_stat(
836 __out efx_mon_stat_t *statp);
838 extern __checkReturn boolean_t
839 efx_mon_get_stat_unit(
840 __in efx_mon_stat_t stat,
841 __out efx_mon_stat_unit_t *unitp);
843 extern __checkReturn boolean_t
844 efx_mon_get_stat_portmap(
845 __in efx_mon_stat_t stat,
846 __out efx_mon_stat_portmask_t *maskp);
848 extern __checkReturn efx_rc_t
849 efx_mon_stats_update(
851 __in efsys_mem_t *esmp,
852 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
854 extern __checkReturn efx_rc_t
855 efx_mon_limits_update(
857 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
859 #endif /* EFSYS_OPT_MON_STATS */
863 __in efx_nic_t *enp);
867 extern __checkReturn efx_rc_t
869 __in efx_nic_t *enp);
871 #if EFSYS_OPT_PHY_LED_CONTROL
873 typedef enum efx_phy_led_mode_e {
874 EFX_PHY_LED_DEFAULT = 0,
879 } efx_phy_led_mode_t;
881 extern __checkReturn efx_rc_t
884 __in efx_phy_led_mode_t mode);
886 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
888 extern __checkReturn efx_rc_t
890 __in efx_nic_t *enp);
892 #if EFSYS_OPT_LOOPBACK
894 typedef enum efx_loopback_type_e {
895 EFX_LOOPBACK_OFF = 0,
896 EFX_LOOPBACK_DATA = 1,
897 EFX_LOOPBACK_GMAC = 2,
898 EFX_LOOPBACK_XGMII = 3,
899 EFX_LOOPBACK_XGXS = 4,
900 EFX_LOOPBACK_XAUI = 5,
901 EFX_LOOPBACK_GMII = 6,
902 EFX_LOOPBACK_SGMII = 7,
903 EFX_LOOPBACK_XGBR = 8,
904 EFX_LOOPBACK_XFI = 9,
905 EFX_LOOPBACK_XAUI_FAR = 10,
906 EFX_LOOPBACK_GMII_FAR = 11,
907 EFX_LOOPBACK_SGMII_FAR = 12,
908 EFX_LOOPBACK_XFI_FAR = 13,
909 EFX_LOOPBACK_GPHY = 14,
910 EFX_LOOPBACK_PHY_XS = 15,
911 EFX_LOOPBACK_PCS = 16,
912 EFX_LOOPBACK_PMA_PMD = 17,
913 EFX_LOOPBACK_XPORT = 18,
914 EFX_LOOPBACK_XGMII_WS = 19,
915 EFX_LOOPBACK_XAUI_WS = 20,
916 EFX_LOOPBACK_XAUI_WS_FAR = 21,
917 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
918 EFX_LOOPBACK_GMII_WS = 23,
919 EFX_LOOPBACK_XFI_WS = 24,
920 EFX_LOOPBACK_XFI_WS_FAR = 25,
921 EFX_LOOPBACK_PHYXS_WS = 26,
922 EFX_LOOPBACK_PMA_INT = 27,
923 EFX_LOOPBACK_SD_NEAR = 28,
924 EFX_LOOPBACK_SD_FAR = 29,
925 EFX_LOOPBACK_PMA_INT_WS = 30,
926 EFX_LOOPBACK_SD_FEP2_WS = 31,
927 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
928 EFX_LOOPBACK_SD_FEP_WS = 33,
929 EFX_LOOPBACK_SD_FES_WS = 34,
930 EFX_LOOPBACK_AOE_INT_NEAR = 35,
931 EFX_LOOPBACK_DATA_WS = 36,
932 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
934 } efx_loopback_type_t;
936 typedef enum efx_loopback_kind_e {
937 EFX_LOOPBACK_KIND_OFF = 0,
938 EFX_LOOPBACK_KIND_ALL,
939 EFX_LOOPBACK_KIND_MAC,
940 EFX_LOOPBACK_KIND_PHY,
942 } efx_loopback_kind_t;
946 __in efx_loopback_kind_t loopback_kind,
947 __out efx_qword_t *maskp);
949 extern __checkReturn efx_rc_t
950 efx_port_loopback_set(
952 __in efx_link_mode_t link_mode,
953 __in efx_loopback_type_t type);
957 extern __checkReturn const char *
958 efx_loopback_type_name(
960 __in efx_loopback_type_t type);
962 #endif /* EFSYS_OPT_NAMES */
964 #endif /* EFSYS_OPT_LOOPBACK */
966 extern __checkReturn efx_rc_t
969 __out_opt efx_link_mode_t *link_modep);
973 __in efx_nic_t *enp);
975 typedef enum efx_phy_cap_type_e {
976 EFX_PHY_CAP_INVALID = 0,
983 EFX_PHY_CAP_10000FDX,
987 EFX_PHY_CAP_40000FDX,
989 EFX_PHY_CAP_100000FDX,
990 EFX_PHY_CAP_25000FDX,
991 EFX_PHY_CAP_50000FDX,
992 EFX_PHY_CAP_BASER_FEC,
993 EFX_PHY_CAP_BASER_FEC_REQUESTED,
995 EFX_PHY_CAP_RS_FEC_REQUESTED,
996 EFX_PHY_CAP_25G_BASER_FEC,
997 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
999 } efx_phy_cap_type_t;
1002 #define EFX_PHY_CAP_CURRENT 0x00000000
1003 #define EFX_PHY_CAP_DEFAULT 0x00000001
1004 #define EFX_PHY_CAP_PERM 0x00000002
1007 efx_phy_adv_cap_get(
1008 __in efx_nic_t *enp,
1010 __out uint32_t *maskp);
1012 extern __checkReturn efx_rc_t
1013 efx_phy_adv_cap_set(
1014 __in efx_nic_t *enp,
1015 __in uint32_t mask);
1019 __in efx_nic_t *enp,
1020 __out uint32_t *maskp);
1022 extern __checkReturn efx_rc_t
1024 __in efx_nic_t *enp,
1025 __out uint32_t *ouip);
1027 typedef enum efx_phy_media_type_e {
1028 EFX_PHY_MEDIA_INVALID = 0,
1033 EFX_PHY_MEDIA_SFP_PLUS,
1034 EFX_PHY_MEDIA_BASE_T,
1035 EFX_PHY_MEDIA_QSFP_PLUS,
1036 EFX_PHY_MEDIA_NTYPES
1037 } efx_phy_media_type_t;
1040 * Get the type of medium currently used. If the board has ports for
1041 * modules, a module is present, and we recognise the media type of
1042 * the module, then this will be the media type of the module.
1043 * Otherwise it will be the media type of the port.
1046 efx_phy_media_type_get(
1047 __in efx_nic_t *enp,
1048 __out efx_phy_media_type_t *typep);
1051 * 2-wire device address of the base information in accordance with SFF-8472
1052 * Diagnostic Monitoring Interface for Optical Transceivers section
1053 * 4 Memory Organization.
1055 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0
1058 * 2-wire device address of the digital diagnostics monitoring interface
1059 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical
1060 * Transceivers section 4 Memory Organization.
1062 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2
1065 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436
1066 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and
1069 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0
1072 * Maximum accessible data offset for PHY module information.
1074 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100
1077 extern __checkReturn efx_rc_t
1078 efx_phy_module_get_info(
1079 __in efx_nic_t *enp,
1080 __in uint8_t dev_addr,
1083 __out_bcount(len) uint8_t *data);
1085 #if EFSYS_OPT_PHY_STATS
1087 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1088 typedef enum efx_phy_stat_e {
1090 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1091 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1092 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1093 EFX_PHY_STAT_PMA_PMD_REV_A,
1094 EFX_PHY_STAT_PMA_PMD_REV_B,
1095 EFX_PHY_STAT_PMA_PMD_REV_C,
1096 EFX_PHY_STAT_PMA_PMD_REV_D,
1097 EFX_PHY_STAT_PCS_LINK_UP,
1098 EFX_PHY_STAT_PCS_RX_FAULT,
1099 EFX_PHY_STAT_PCS_TX_FAULT,
1100 EFX_PHY_STAT_PCS_BER,
1101 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1102 EFX_PHY_STAT_PHY_XS_LINK_UP,
1103 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1104 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1105 EFX_PHY_STAT_PHY_XS_ALIGN,
1106 EFX_PHY_STAT_PHY_XS_SYNC_A,
1107 EFX_PHY_STAT_PHY_XS_SYNC_B,
1108 EFX_PHY_STAT_PHY_XS_SYNC_C,
1109 EFX_PHY_STAT_PHY_XS_SYNC_D,
1110 EFX_PHY_STAT_AN_LINK_UP,
1111 EFX_PHY_STAT_AN_MASTER,
1112 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1113 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1114 EFX_PHY_STAT_CL22EXT_LINK_UP,
1119 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1120 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1121 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1122 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1123 EFX_PHY_STAT_AN_COMPLETE,
1124 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1125 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1126 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1127 EFX_PHY_STAT_PCS_FW_VERSION_0,
1128 EFX_PHY_STAT_PCS_FW_VERSION_1,
1129 EFX_PHY_STAT_PCS_FW_VERSION_2,
1130 EFX_PHY_STAT_PCS_FW_VERSION_3,
1131 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1132 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1133 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1134 EFX_PHY_STAT_PCS_OP_MODE,
1138 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1144 __in efx_nic_t *enp,
1145 __in efx_phy_stat_t stat);
1147 #endif /* EFSYS_OPT_NAMES */
1149 #define EFX_PHY_STATS_SIZE 0x100
1151 extern __checkReturn efx_rc_t
1152 efx_phy_stats_update(
1153 __in efx_nic_t *enp,
1154 __in efsys_mem_t *esmp,
1155 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1157 #endif /* EFSYS_OPT_PHY_STATS */
1162 typedef enum efx_bist_type_e {
1163 EFX_BIST_TYPE_UNKNOWN,
1164 EFX_BIST_TYPE_PHY_NORMAL,
1165 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1166 EFX_BIST_TYPE_PHY_CABLE_LONG,
1167 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1168 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1169 EFX_BIST_TYPE_REG, /* Test the register memories */
1170 EFX_BIST_TYPE_NTYPES,
1173 typedef enum efx_bist_result_e {
1174 EFX_BIST_RESULT_UNKNOWN,
1175 EFX_BIST_RESULT_RUNNING,
1176 EFX_BIST_RESULT_PASSED,
1177 EFX_BIST_RESULT_FAILED,
1178 } efx_bist_result_t;
1180 typedef enum efx_phy_cable_status_e {
1181 EFX_PHY_CABLE_STATUS_OK,
1182 EFX_PHY_CABLE_STATUS_INVALID,
1183 EFX_PHY_CABLE_STATUS_OPEN,
1184 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1185 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1186 EFX_PHY_CABLE_STATUS_BUSY,
1187 } efx_phy_cable_status_t;
1189 typedef enum efx_bist_value_e {
1190 EFX_BIST_PHY_CABLE_LENGTH_A,
1191 EFX_BIST_PHY_CABLE_LENGTH_B,
1192 EFX_BIST_PHY_CABLE_LENGTH_C,
1193 EFX_BIST_PHY_CABLE_LENGTH_D,
1194 EFX_BIST_PHY_CABLE_STATUS_A,
1195 EFX_BIST_PHY_CABLE_STATUS_B,
1196 EFX_BIST_PHY_CABLE_STATUS_C,
1197 EFX_BIST_PHY_CABLE_STATUS_D,
1198 EFX_BIST_FAULT_CODE,
1200 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1206 EFX_BIST_MEM_EXPECT,
1207 EFX_BIST_MEM_ACTUAL,
1209 EFX_BIST_MEM_ECC_PARITY,
1210 EFX_BIST_MEM_ECC_FATAL,
1214 extern __checkReturn efx_rc_t
1215 efx_bist_enable_offline(
1216 __in efx_nic_t *enp);
1218 extern __checkReturn efx_rc_t
1220 __in efx_nic_t *enp,
1221 __in efx_bist_type_t type);
1223 extern __checkReturn efx_rc_t
1225 __in efx_nic_t *enp,
1226 __in efx_bist_type_t type,
1227 __out efx_bist_result_t *resultp,
1228 __out_opt uint32_t *value_maskp,
1229 __out_ecount_opt(count) unsigned long *valuesp,
1234 __in efx_nic_t *enp,
1235 __in efx_bist_type_t type);
1237 #endif /* EFSYS_OPT_BIST */
1239 #define EFX_FEATURE_IPV6 0x00000001
1240 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1241 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1242 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1243 #define EFX_FEATURE_MCDI 0x00000020
1244 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1245 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1246 #define EFX_FEATURE_TURBO 0x00000100
1247 #define EFX_FEATURE_MCDI_DMA 0x00000200
1248 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1249 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1250 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1251 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1252 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1253 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000
1255 typedef enum efx_tunnel_protocol_e {
1256 EFX_TUNNEL_PROTOCOL_NONE = 0,
1257 EFX_TUNNEL_PROTOCOL_VXLAN,
1258 EFX_TUNNEL_PROTOCOL_GENEVE,
1259 EFX_TUNNEL_PROTOCOL_NVGRE,
1261 } efx_tunnel_protocol_t;
1263 typedef enum efx_vi_window_shift_e {
1264 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1265 EFX_VI_WINDOW_SHIFT_8K = 13,
1266 EFX_VI_WINDOW_SHIFT_16K = 14,
1267 EFX_VI_WINDOW_SHIFT_64K = 16,
1268 } efx_vi_window_shift_t;
1270 typedef struct efx_nic_cfg_s {
1271 uint32_t enc_board_type;
1272 uint32_t enc_phy_type;
1274 char enc_phy_name[21];
1276 char enc_phy_revision[21];
1277 efx_mon_type_t enc_mon_type;
1278 #if EFSYS_OPT_MON_STATS
1279 uint32_t enc_mon_stat_dma_buf_size;
1280 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1282 unsigned int enc_features;
1283 efx_vi_window_shift_t enc_vi_window_shift;
1284 uint8_t enc_mac_addr[6];
1285 uint8_t enc_port; /* PHY port number */
1286 uint32_t enc_intr_vec_base;
1287 uint32_t enc_intr_limit;
1288 uint32_t enc_evq_limit;
1289 uint32_t enc_txq_limit;
1290 uint32_t enc_rxq_limit;
1291 uint32_t enc_evq_max_nevs;
1292 uint32_t enc_evq_min_nevs;
1293 uint32_t enc_rxq_max_ndescs;
1294 uint32_t enc_rxq_min_ndescs;
1295 uint32_t enc_txq_max_ndescs;
1296 uint32_t enc_txq_min_ndescs;
1297 uint32_t enc_buftbl_limit;
1298 uint32_t enc_piobuf_limit;
1299 uint32_t enc_piobuf_size;
1300 uint32_t enc_piobuf_min_alloc_size;
1301 uint32_t enc_evq_timer_quantum_ns;
1302 uint32_t enc_evq_timer_max_us;
1303 uint32_t enc_clk_mult;
1304 uint32_t enc_ev_desc_size;
1305 uint32_t enc_rx_desc_size;
1306 uint32_t enc_tx_desc_size;
1307 uint32_t enc_rx_prefix_size;
1308 uint32_t enc_rx_buf_align_start;
1309 uint32_t enc_rx_buf_align_end;
1310 #if EFSYS_OPT_RX_SCALE
1311 uint32_t enc_rx_scale_max_exclusive_contexts;
1313 * Mask of supported hash algorithms.
1314 * Hash algorithm types are used as the bit indices.
1316 uint32_t enc_rx_scale_hash_alg_mask;
1318 * Indicates whether port numbers can be included to the
1319 * input data for hash computation.
1321 boolean_t enc_rx_scale_l4_hash_supported;
1322 boolean_t enc_rx_scale_additional_modes_supported;
1323 #endif /* EFSYS_OPT_RX_SCALE */
1324 #if EFSYS_OPT_LOOPBACK
1325 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1326 #endif /* EFSYS_OPT_LOOPBACK */
1327 #if EFSYS_OPT_PHY_FLAGS
1328 uint32_t enc_phy_flags_mask;
1329 #endif /* EFSYS_OPT_PHY_FLAGS */
1330 #if EFSYS_OPT_PHY_LED_CONTROL
1331 uint32_t enc_led_mask;
1332 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1333 #if EFSYS_OPT_PHY_STATS
1334 uint64_t enc_phy_stat_mask;
1335 #endif /* EFSYS_OPT_PHY_STATS */
1337 uint8_t enc_mcdi_mdio_channel;
1338 #if EFSYS_OPT_PHY_STATS
1339 uint32_t enc_mcdi_phy_stat_mask;
1340 #endif /* EFSYS_OPT_PHY_STATS */
1341 #if EFSYS_OPT_MON_STATS
1342 uint32_t *enc_mcdi_sensor_maskp;
1343 uint32_t enc_mcdi_sensor_mask_size;
1344 #endif /* EFSYS_OPT_MON_STATS */
1345 #endif /* EFSYS_OPT_MCDI */
1347 uint32_t enc_bist_mask;
1348 #endif /* EFSYS_OPT_BIST */
1352 uint32_t enc_privilege_mask;
1353 #endif /* EFX_OPTS_EF10() */
1354 boolean_t enc_bug26807_workaround;
1355 boolean_t enc_bug35388_workaround;
1356 boolean_t enc_bug41750_workaround;
1357 boolean_t enc_bug61265_workaround;
1358 boolean_t enc_bug61297_workaround;
1359 boolean_t enc_rx_batching_enabled;
1360 /* Maximum number of descriptors completed in an rx event. */
1361 uint32_t enc_rx_batch_max;
1362 /* Number of rx descriptors the hardware requires for a push. */
1363 uint32_t enc_rx_push_align;
1364 /* Maximum amount of data in DMA descriptor */
1365 uint32_t enc_tx_dma_desc_size_max;
1367 * Boundary which DMA descriptor data must not cross or 0 if no
1370 uint32_t enc_tx_dma_desc_boundary;
1372 * Maximum number of bytes into the packet the TCP header can start for
1373 * the hardware to apply TSO packet edits.
1375 uint32_t enc_tx_tso_tcp_header_offset_limit;
1376 boolean_t enc_fw_assisted_tso_enabled;
1377 boolean_t enc_fw_assisted_tso_v2_enabled;
1378 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1379 /* Number of TSO contexts on the NIC (FATSOv2) */
1380 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1381 boolean_t enc_hw_tx_insert_vlan_enabled;
1382 /* Number of PFs on the NIC */
1383 uint32_t enc_hw_pf_count;
1384 /* Datapath firmware vadapter/vport/vswitch support */
1385 boolean_t enc_datapath_cap_evb;
1386 /* Datapath firmware vport reconfigure support */
1387 boolean_t enc_vport_reconfigure_supported;
1388 boolean_t enc_rx_disable_scatter_supported;
1389 boolean_t enc_allow_set_mac_with_installed_filters;
1390 boolean_t enc_enhanced_set_mac_supported;
1391 boolean_t enc_init_evq_v2_supported;
1392 boolean_t enc_no_cont_ev_mode_supported;
1393 boolean_t enc_init_rxq_with_buffer_size;
1394 boolean_t enc_rx_packed_stream_supported;
1395 boolean_t enc_rx_var_packed_stream_supported;
1396 boolean_t enc_rx_es_super_buffer_supported;
1397 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1398 boolean_t enc_pm_and_rxdp_counters;
1399 boolean_t enc_mac_stats_40g_tx_size_bins;
1400 uint32_t enc_tunnel_encapsulations_supported;
1402 * NIC global maximum for unique UDP tunnel ports shared by all
1405 uint32_t enc_tunnel_config_udp_entries_max;
1406 /* External port identifier */
1407 uint8_t enc_external_port;
1408 uint32_t enc_mcdi_max_payload_length;
1409 /* VPD may be per-PF or global */
1410 boolean_t enc_vpd_is_global;
1411 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1412 uint32_t enc_required_pcie_bandwidth_mbps;
1413 uint32_t enc_max_pcie_link_gen;
1414 /* Firmware verifies integrity of NVRAM updates */
1415 boolean_t enc_nvram_update_verify_result_supported;
1416 /* Firmware supports polled NVRAM updates on select partitions */
1417 boolean_t enc_nvram_update_poll_verify_result_supported;
1418 /* Firmware accepts updates via the BUNDLE partition */
1419 boolean_t enc_nvram_bundle_update_supported;
1420 /* Firmware support for extended MAC_STATS buffer */
1421 uint32_t enc_mac_stats_nstats;
1422 boolean_t enc_fec_counters;
1423 boolean_t enc_hlb_counters;
1424 /* Firmware support for "FLAG" and "MARK" filter actions */
1425 boolean_t enc_filter_action_flag_supported;
1426 boolean_t enc_filter_action_mark_supported;
1427 uint32_t enc_filter_action_mark_max;
1428 /* Port assigned to this PCI function */
1429 uint32_t enc_assigned_port;
1432 #define EFX_VPORT_PCI_FUNCTION_IS_PF(configp) \
1433 ((configp)->evc_function == 0xffff)
1435 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1436 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1438 #define EFX_PCI_FUNCTION(_encp) \
1439 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1441 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1443 extern const efx_nic_cfg_t *
1445 __in const efx_nic_t *enp);
1447 /* RxDPCPU firmware id values by which FW variant can be identified */
1448 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1449 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1450 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1451 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1452 #define EFX_RXDP_DPDK_FW_ID 0x6
1454 typedef struct efx_nic_fw_info_s {
1455 /* Basic FW version information */
1456 uint16_t enfi_mc_fw_version[4];
1458 * If datapath capabilities can be detected,
1459 * additional FW information is to be shown
1461 boolean_t enfi_dpcpu_fw_ids_valid;
1462 /* Rx and Tx datapath CPU FW IDs */
1463 uint16_t enfi_rx_dpcpu_fw_id;
1464 uint16_t enfi_tx_dpcpu_fw_id;
1465 } efx_nic_fw_info_t;
1467 extern __checkReturn efx_rc_t
1468 efx_nic_get_fw_version(
1469 __in efx_nic_t *enp,
1470 __out efx_nic_fw_info_t *enfip);
1472 /* Driver resource limits (minimum required/maximum usable). */
1473 typedef struct efx_drv_limits_s {
1474 uint32_t edl_min_evq_count;
1475 uint32_t edl_max_evq_count;
1477 uint32_t edl_min_rxq_count;
1478 uint32_t edl_max_rxq_count;
1480 uint32_t edl_min_txq_count;
1481 uint32_t edl_max_txq_count;
1483 /* PIO blocks (sub-allocated from piobuf) */
1484 uint32_t edl_min_pio_alloc_size;
1485 uint32_t edl_max_pio_alloc_count;
1488 extern __checkReturn efx_rc_t
1489 efx_nic_set_drv_limits(
1490 __inout efx_nic_t *enp,
1491 __in efx_drv_limits_t *edlp);
1494 * Register the OS driver version string for management agents
1495 * (e.g. via NC-SI). The content length is provided (i.e. no
1496 * NUL terminator). Use length 0 to indicate no version string
1497 * should be advertised. It is valid to set the version string
1498 * only before efx_nic_probe() is called.
1500 extern __checkReturn efx_rc_t
1501 efx_nic_set_drv_version(
1502 __inout efx_nic_t *enp,
1503 __in_ecount(length) char const *verp,
1504 __in size_t length);
1506 typedef enum efx_nic_region_e {
1507 EFX_REGION_VI, /* Memory BAR UC mapping */
1508 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1511 extern __checkReturn efx_rc_t
1512 efx_nic_get_bar_region(
1513 __in efx_nic_t *enp,
1514 __in efx_nic_region_t region,
1515 __out uint32_t *offsetp,
1516 __out size_t *sizep);
1518 extern __checkReturn efx_rc_t
1519 efx_nic_get_vi_pool(
1520 __in efx_nic_t *enp,
1521 __out uint32_t *evq_countp,
1522 __out uint32_t *rxq_countp,
1523 __out uint32_t *txq_countp);
1528 typedef enum efx_vpd_tag_e {
1535 typedef uint16_t efx_vpd_keyword_t;
1537 typedef struct efx_vpd_value_s {
1538 efx_vpd_tag_t evv_tag;
1539 efx_vpd_keyword_t evv_keyword;
1541 uint8_t evv_value[0x100];
1545 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1547 extern __checkReturn efx_rc_t
1549 __in efx_nic_t *enp);
1551 extern __checkReturn efx_rc_t
1553 __in efx_nic_t *enp,
1554 __out size_t *sizep);
1556 extern __checkReturn efx_rc_t
1558 __in efx_nic_t *enp,
1559 __out_bcount(size) caddr_t data,
1562 extern __checkReturn efx_rc_t
1564 __in efx_nic_t *enp,
1565 __in_bcount(size) caddr_t data,
1568 extern __checkReturn efx_rc_t
1570 __in efx_nic_t *enp,
1571 __in_bcount(size) caddr_t data,
1574 extern __checkReturn efx_rc_t
1576 __in efx_nic_t *enp,
1577 __in_bcount(size) caddr_t data,
1579 __inout efx_vpd_value_t *evvp);
1581 extern __checkReturn efx_rc_t
1583 __in efx_nic_t *enp,
1584 __inout_bcount(size) caddr_t data,
1586 __in efx_vpd_value_t *evvp);
1588 extern __checkReturn efx_rc_t
1590 __in efx_nic_t *enp,
1591 __inout_bcount(size) caddr_t data,
1593 __out efx_vpd_value_t *evvp,
1594 __inout unsigned int *contp);
1596 extern __checkReturn efx_rc_t
1598 __in efx_nic_t *enp,
1599 __in_bcount(size) caddr_t data,
1604 __in efx_nic_t *enp);
1606 #endif /* EFSYS_OPT_VPD */
1612 typedef enum efx_nvram_type_e {
1613 EFX_NVRAM_INVALID = 0,
1615 EFX_NVRAM_BOOTROM_CFG,
1616 EFX_NVRAM_MC_FIRMWARE,
1617 EFX_NVRAM_MC_GOLDEN,
1623 EFX_NVRAM_FPGA_BACKUP,
1624 EFX_NVRAM_DYNAMIC_CFG,
1627 EFX_NVRAM_MUM_FIRMWARE,
1628 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1629 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1631 EFX_NVRAM_BUNDLE_METADATA,
1635 typedef struct efx_nvram_info_s {
1637 uint32_t eni_partn_size;
1638 uint32_t eni_address;
1639 uint32_t eni_erase_size;
1640 uint32_t eni_write_size;
1643 #define EFX_NVRAM_FLAG_READ_ONLY (1 << 0)
1645 extern __checkReturn efx_rc_t
1647 __in efx_nic_t *enp);
1651 extern __checkReturn efx_rc_t
1653 __in efx_nic_t *enp);
1655 #endif /* EFSYS_OPT_DIAG */
1657 extern __checkReturn efx_rc_t
1659 __in efx_nic_t *enp,
1660 __in efx_nvram_type_t type,
1661 __out size_t *sizep);
1663 extern __checkReturn efx_rc_t
1665 __in efx_nic_t *enp,
1666 __in efx_nvram_type_t type,
1667 __out efx_nvram_info_t *enip);
1669 extern __checkReturn efx_rc_t
1671 __in efx_nic_t *enp,
1672 __in efx_nvram_type_t type,
1673 __out_opt size_t *pref_chunkp);
1675 extern __checkReturn efx_rc_t
1676 efx_nvram_rw_finish(
1677 __in efx_nic_t *enp,
1678 __in efx_nvram_type_t type,
1679 __out_opt uint32_t *verify_resultp);
1681 extern __checkReturn efx_rc_t
1682 efx_nvram_get_version(
1683 __in efx_nic_t *enp,
1684 __in efx_nvram_type_t type,
1685 __out uint32_t *subtypep,
1686 __out_ecount(4) uint16_t version[4]);
1688 extern __checkReturn efx_rc_t
1689 efx_nvram_read_chunk(
1690 __in efx_nic_t *enp,
1691 __in efx_nvram_type_t type,
1692 __in unsigned int offset,
1693 __out_bcount(size) caddr_t data,
1696 extern __checkReturn efx_rc_t
1697 efx_nvram_read_backup(
1698 __in efx_nic_t *enp,
1699 __in efx_nvram_type_t type,
1700 __in unsigned int offset,
1701 __out_bcount(size) caddr_t data,
1704 extern __checkReturn efx_rc_t
1705 efx_nvram_set_version(
1706 __in efx_nic_t *enp,
1707 __in efx_nvram_type_t type,
1708 __in_ecount(4) uint16_t version[4]);
1710 extern __checkReturn efx_rc_t
1712 __in efx_nic_t *enp,
1713 __in efx_nvram_type_t type,
1714 __in_bcount(partn_size) caddr_t partn_data,
1715 __in size_t partn_size);
1717 extern __checkReturn efx_rc_t
1719 __in efx_nic_t *enp,
1720 __in efx_nvram_type_t type);
1722 extern __checkReturn efx_rc_t
1723 efx_nvram_write_chunk(
1724 __in efx_nic_t *enp,
1725 __in efx_nvram_type_t type,
1726 __in unsigned int offset,
1727 __in_bcount(size) caddr_t data,
1732 __in efx_nic_t *enp);
1734 #endif /* EFSYS_OPT_NVRAM */
1736 #if EFSYS_OPT_BOOTCFG
1738 /* Report size and offset of bootcfg sector in NVRAM partition. */
1739 extern __checkReturn efx_rc_t
1740 efx_bootcfg_sector_info(
1741 __in efx_nic_t *enp,
1743 __out_opt uint32_t *sector_countp,
1744 __out size_t *offsetp,
1745 __out size_t *max_sizep);
1748 * Copy bootcfg sector data to a target buffer which may differ in size.
1749 * Optionally corrects format errors in source buffer.
1752 efx_bootcfg_copy_sector(
1753 __in efx_nic_t *enp,
1754 __inout_bcount(sector_length)
1756 __in size_t sector_length,
1757 __out_bcount(data_size) uint8_t *data,
1758 __in size_t data_size,
1759 __in boolean_t handle_format_errors);
1763 __in efx_nic_t *enp,
1764 __out_bcount(size) uint8_t *data,
1769 __in efx_nic_t *enp,
1770 __in_bcount(size) uint8_t *data,
1775 * Processing routines for buffers arranged in the DHCP/BOOTP option format
1776 * (see https://tools.ietf.org/html/rfc1533)
1778 * Summarising the format: the buffer is a sequence of options. All options
1779 * begin with a tag octet, which uniquely identifies the option. Fixed-
1780 * length options without data consist of only a tag octet. Only options PAD
1781 * (0) and END (255) are fixed length. All other options are variable-length
1782 * with a length octet following the tag octet. The value of the length
1783 * octet does not include the two octets specifying the tag and length. The
1784 * length octet is followed by "length" octets of data.
1786 * Option data may be a sequence of sub-options in the same format. The data
1787 * content of the encapsulating option is one or more encapsulated sub-options,
1788 * with no terminating END tag is required.
1790 * To be valid, the top-level sequence of options should be terminated by an
1791 * END tag. The buffer should be padded with the PAD byte.
1793 * When stored to NVRAM, the DHCP option format buffer is preceded by a
1794 * checksum octet. The full buffer (including after the END tag) contributes
1795 * to the checksum, hence the need to fill the buffer to the end with PAD.
1798 #define EFX_DHCP_END ((uint8_t)0xff)
1799 #define EFX_DHCP_PAD ((uint8_t)0)
1801 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \
1802 (uint16_t)(((encapsulator) << 8) | (encapsulated))
1804 extern __checkReturn uint8_t
1806 __in_bcount(size) uint8_t const *data,
1809 extern __checkReturn efx_rc_t
1811 __in_bcount(size) uint8_t const *data,
1813 __out_opt size_t *usedp);
1815 extern __checkReturn efx_rc_t
1817 __in_bcount(buffer_length) uint8_t *bufferp,
1818 __in size_t buffer_length,
1820 __deref_out uint8_t **valuepp,
1821 __out size_t *value_lengthp);
1823 extern __checkReturn efx_rc_t
1825 __in_bcount(buffer_length) uint8_t *bufferp,
1826 __in size_t buffer_length,
1827 __deref_out uint8_t **endpp);
1830 extern __checkReturn efx_rc_t
1831 efx_dhcp_delete_tag(
1832 __inout_bcount(buffer_length) uint8_t *bufferp,
1833 __in size_t buffer_length,
1836 extern __checkReturn efx_rc_t
1838 __inout_bcount(buffer_length) uint8_t *bufferp,
1839 __in size_t buffer_length,
1841 __in_bcount_opt(value_length) uint8_t *valuep,
1842 __in size_t value_length);
1844 extern __checkReturn efx_rc_t
1845 efx_dhcp_update_tag(
1846 __inout_bcount(buffer_length) uint8_t *bufferp,
1847 __in size_t buffer_length,
1849 __in uint8_t *value_locationp,
1850 __in_bcount_opt(value_length) uint8_t *valuep,
1851 __in size_t value_length);
1854 #endif /* EFSYS_OPT_BOOTCFG */
1856 #if EFSYS_OPT_IMAGE_LAYOUT
1858 #include "ef10_signed_image_layout.h"
1861 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1864 * The image header format is extensible. However, older drivers require an
1865 * exact match of image header version and header length when validating and
1866 * writing firmware images.
1868 * To avoid breaking backward compatibility, we use the upper bits of the
1869 * controller version fields to contain an extra version number used for
1870 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
1871 * version). See bug39254 and SF-102785-PS for details.
1873 typedef struct efx_image_header_s {
1875 uint32_t eih_version;
1877 uint32_t eih_subtype;
1878 uint32_t eih_code_size;
1881 uint32_t eih_controller_version_min;
1883 uint16_t eih_controller_version_min_short;
1884 uint8_t eih_extra_version_a;
1885 uint8_t eih_extra_version_b;
1889 uint32_t eih_controller_version_max;
1891 uint16_t eih_controller_version_max_short;
1892 uint8_t eih_extra_version_c;
1893 uint8_t eih_extra_version_d;
1896 uint16_t eih_code_version_a;
1897 uint16_t eih_code_version_b;
1898 uint16_t eih_code_version_c;
1899 uint16_t eih_code_version_d;
1900 } efx_image_header_t;
1902 #define EFX_IMAGE_HEADER_SIZE (40)
1903 #define EFX_IMAGE_HEADER_VERSION (4)
1904 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
1907 typedef struct efx_image_trailer_s {
1909 } efx_image_trailer_t;
1911 #define EFX_IMAGE_TRAILER_SIZE (4)
1913 typedef enum efx_image_format_e {
1914 EFX_IMAGE_FORMAT_NO_IMAGE,
1915 EFX_IMAGE_FORMAT_INVALID,
1916 EFX_IMAGE_FORMAT_UNSIGNED,
1917 EFX_IMAGE_FORMAT_SIGNED,
1918 EFX_IMAGE_FORMAT_SIGNED_PACKAGE
1919 } efx_image_format_t;
1921 typedef struct efx_image_info_s {
1922 efx_image_format_t eii_format;
1923 uint8_t * eii_imagep;
1924 size_t eii_image_size;
1925 efx_image_header_t * eii_headerp;
1928 extern __checkReturn efx_rc_t
1929 efx_check_reflash_image(
1931 __in uint32_t buffer_size,
1932 __out efx_image_info_t *infop);
1934 extern __checkReturn efx_rc_t
1935 efx_build_signed_image_write_buffer(
1936 __out_bcount(buffer_size)
1938 __in uint32_t buffer_size,
1939 __in efx_image_info_t *infop,
1940 __out efx_image_header_t **headerpp);
1942 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
1946 typedef enum efx_pattern_type_t {
1947 EFX_PATTERN_BYTE_INCREMENT = 0,
1948 EFX_PATTERN_ALL_THE_SAME,
1949 EFX_PATTERN_BIT_ALTERNATE,
1950 EFX_PATTERN_BYTE_ALTERNATE,
1951 EFX_PATTERN_BYTE_CHANGING,
1952 EFX_PATTERN_BIT_SWEEP,
1954 } efx_pattern_type_t;
1957 (*efx_sram_pattern_fn_t)(
1959 __in boolean_t negate,
1960 __out efx_qword_t *eqp);
1962 extern __checkReturn efx_rc_t
1964 __in efx_nic_t *enp,
1965 __in efx_pattern_type_t type);
1967 #endif /* EFSYS_OPT_DIAG */
1969 extern __checkReturn efx_rc_t
1970 efx_sram_buf_tbl_set(
1971 __in efx_nic_t *enp,
1973 __in efsys_mem_t *esmp,
1977 efx_sram_buf_tbl_clear(
1978 __in efx_nic_t *enp,
1982 #define EFX_BUF_TBL_SIZE 0x20000
1984 #define EFX_BUF_SIZE 4096
1988 typedef struct efx_evq_s efx_evq_t;
1990 #if EFSYS_OPT_QSTATS
1992 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 0a147ace40844969 */
1993 typedef enum efx_ev_qstat_e {
1999 EV_RX_PAUSE_FRM_ERR,
2000 EV_RX_BUF_OWNER_ID_ERR,
2001 EV_RX_IPV4_HDR_CHKSUM_ERR,
2002 EV_RX_TCP_UDP_CHKSUM_ERR,
2006 EV_RX_MCAST_HASH_MATCH,
2023 EV_DRIVER_SRM_UPD_DONE,
2024 EV_DRIVER_TX_DESCQ_FLS_DONE,
2025 EV_DRIVER_RX_DESCQ_FLS_DONE,
2026 EV_DRIVER_RX_DESCQ_FLS_FAILED,
2027 EV_DRIVER_RX_DSC_ERROR,
2028 EV_DRIVER_TX_DSC_ERROR,
2031 EV_RX_PARSE_INCOMPLETE,
2035 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
2037 #endif /* EFSYS_OPT_QSTATS */
2039 extern __checkReturn efx_rc_t
2041 __in efx_nic_t *enp);
2045 __in efx_nic_t *enp);
2047 extern __checkReturn size_t
2049 __in const efx_nic_t *enp,
2050 __in unsigned int ndescs);
2052 extern __checkReturn unsigned int
2054 __in const efx_nic_t *enp,
2055 __in unsigned int ndescs);
2057 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
2058 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
2059 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
2060 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
2062 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
2063 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
2064 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
2067 * Use the NO_CONT_EV RX event format, which allows the firmware to operate more
2068 * efficiently at high data rates. See SF-109306-TC 5.11 "Events for RXQs in
2071 * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set,
2072 * which is the case when an event queue is set to THROUGHPUT mode.
2074 #define EFX_EVQ_FLAGS_NO_CONT_EV (0x10)
2076 extern __checkReturn efx_rc_t
2078 __in efx_nic_t *enp,
2079 __in unsigned int index,
2080 __in efsys_mem_t *esmp,
2084 __in uint32_t flags,
2085 __deref_out efx_evq_t **eepp);
2089 __in efx_evq_t *eep,
2090 __in uint16_t data);
2092 typedef __checkReturn boolean_t
2093 (*efx_initialized_ev_t)(
2094 __in_opt void *arg);
2096 #define EFX_PKT_UNICAST 0x0004
2097 #define EFX_PKT_START 0x0008
2099 #define EFX_PKT_VLAN_TAGGED 0x0010
2100 #define EFX_CKSUM_TCPUDP 0x0020
2101 #define EFX_CKSUM_IPV4 0x0040
2102 #define EFX_PKT_CONT 0x0080
2104 #define EFX_CHECK_VLAN 0x0100
2105 #define EFX_PKT_TCP 0x0200
2106 #define EFX_PKT_UDP 0x0400
2107 #define EFX_PKT_IPV4 0x0800
2109 #define EFX_PKT_IPV6 0x1000
2110 #define EFX_PKT_PREFIX_LEN 0x2000
2111 #define EFX_ADDR_MISMATCH 0x4000
2112 #define EFX_DISCARD 0x8000
2115 * The following flags are used only for packed stream
2116 * mode. The values for the flags are reused to fit into 16 bit,
2117 * since EFX_PKT_START and EFX_PKT_CONT are never used in
2118 * packed stream mode
2120 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
2121 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
2124 #define EFX_EV_RX_NLABELS 32
2125 #define EFX_EV_TX_NLABELS 32
2127 typedef __checkReturn boolean_t
2130 __in uint32_t label,
2133 __in uint16_t flags);
2135 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2138 * Packed stream mode is documented in SF-112241-TC.
2139 * The general idea is that, instead of putting each incoming
2140 * packet into a separate buffer which is specified in a RX
2141 * descriptor, a large buffer is provided to the hardware and
2142 * packets are put there in a continuous stream.
2143 * The main advantage of such an approach is that RX queue refilling
2144 * happens much less frequently.
2146 * Equal stride packed stream mode is documented in SF-119419-TC.
2147 * The general idea is to utilize advantages of the packed stream,
2148 * but avoid indirection in packets representation.
2149 * The main advantage of such an approach is that RX queue refilling
2150 * happens much less frequently and packets buffers are independent
2151 * from upper layers point of view.
2154 typedef __checkReturn boolean_t
2157 __in uint32_t label,
2159 __in uint32_t pkt_count,
2160 __in uint16_t flags);
2164 typedef __checkReturn boolean_t
2167 __in uint32_t label,
2170 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
2171 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
2172 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
2173 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
2174 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
2175 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
2176 #define EFX_EXCEPTION_RX_ERROR 0x00000007
2177 #define EFX_EXCEPTION_TX_ERROR 0x00000008
2178 #define EFX_EXCEPTION_EV_ERROR 0x00000009
2180 typedef __checkReturn boolean_t
2181 (*efx_exception_ev_t)(
2183 __in uint32_t label,
2184 __in uint32_t data);
2186 typedef __checkReturn boolean_t
2187 (*efx_rxq_flush_done_ev_t)(
2189 __in uint32_t rxq_index);
2191 typedef __checkReturn boolean_t
2192 (*efx_rxq_flush_failed_ev_t)(
2194 __in uint32_t rxq_index);
2196 typedef __checkReturn boolean_t
2197 (*efx_txq_flush_done_ev_t)(
2199 __in uint32_t txq_index);
2201 typedef __checkReturn boolean_t
2202 (*efx_software_ev_t)(
2204 __in uint16_t magic);
2206 typedef __checkReturn boolean_t
2209 __in uint32_t code);
2211 #define EFX_SRAM_CLEAR 0
2212 #define EFX_SRAM_UPDATE 1
2213 #define EFX_SRAM_ILLEGAL_CLEAR 2
2215 typedef __checkReturn boolean_t
2216 (*efx_wake_up_ev_t)(
2218 __in uint32_t label);
2220 typedef __checkReturn boolean_t
2223 __in uint32_t label);
2225 typedef __checkReturn boolean_t
2226 (*efx_link_change_ev_t)(
2228 __in efx_link_mode_t link_mode);
2230 #if EFSYS_OPT_MON_STATS
2232 typedef __checkReturn boolean_t
2233 (*efx_monitor_ev_t)(
2235 __in efx_mon_stat_t id,
2236 __in efx_mon_stat_value_t value);
2238 #endif /* EFSYS_OPT_MON_STATS */
2240 #if EFSYS_OPT_MAC_STATS
2242 typedef __checkReturn boolean_t
2243 (*efx_mac_stats_ev_t)(
2245 __in uint32_t generation);
2247 #endif /* EFSYS_OPT_MAC_STATS */
2249 typedef struct efx_ev_callbacks_s {
2250 efx_initialized_ev_t eec_initialized;
2252 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2253 efx_rx_ps_ev_t eec_rx_ps;
2256 efx_exception_ev_t eec_exception;
2257 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2258 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2259 efx_txq_flush_done_ev_t eec_txq_flush_done;
2260 efx_software_ev_t eec_software;
2261 efx_sram_ev_t eec_sram;
2262 efx_wake_up_ev_t eec_wake_up;
2263 efx_timer_ev_t eec_timer;
2264 efx_link_change_ev_t eec_link_change;
2265 #if EFSYS_OPT_MON_STATS
2266 efx_monitor_ev_t eec_monitor;
2267 #endif /* EFSYS_OPT_MON_STATS */
2268 #if EFSYS_OPT_MAC_STATS
2269 efx_mac_stats_ev_t eec_mac_stats;
2270 #endif /* EFSYS_OPT_MAC_STATS */
2271 } efx_ev_callbacks_t;
2273 extern __checkReturn boolean_t
2275 __in efx_evq_t *eep,
2276 __in unsigned int count);
2278 #if EFSYS_OPT_EV_PREFETCH
2282 __in efx_evq_t *eep,
2283 __in unsigned int count);
2285 #endif /* EFSYS_OPT_EV_PREFETCH */
2289 __in efx_evq_t *eep,
2290 __inout unsigned int *countp,
2291 __in const efx_ev_callbacks_t *eecp,
2292 __in_opt void *arg);
2294 extern __checkReturn efx_rc_t
2295 efx_ev_usecs_to_ticks(
2296 __in efx_nic_t *enp,
2297 __in unsigned int usecs,
2298 __out unsigned int *ticksp);
2300 extern __checkReturn efx_rc_t
2302 __in efx_evq_t *eep,
2303 __in unsigned int us);
2305 extern __checkReturn efx_rc_t
2307 __in efx_evq_t *eep,
2308 __in unsigned int count);
2310 #if EFSYS_OPT_QSTATS
2316 __in efx_nic_t *enp,
2317 __in unsigned int id);
2319 #endif /* EFSYS_OPT_NAMES */
2322 efx_ev_qstats_update(
2323 __in efx_evq_t *eep,
2324 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2326 #endif /* EFSYS_OPT_QSTATS */
2330 __in efx_evq_t *eep);
2334 extern __checkReturn efx_rc_t
2336 __inout efx_nic_t *enp);
2340 __in efx_nic_t *enp);
2342 #if EFSYS_OPT_RX_SCATTER
2343 __checkReturn efx_rc_t
2344 efx_rx_scatter_enable(
2345 __in efx_nic_t *enp,
2346 __in unsigned int buf_size);
2347 #endif /* EFSYS_OPT_RX_SCATTER */
2349 /* Handle to represent use of the default RSS context. */
2350 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2352 #if EFSYS_OPT_RX_SCALE
2354 typedef enum efx_rx_hash_alg_e {
2355 EFX_RX_HASHALG_LFSR = 0,
2356 EFX_RX_HASHALG_TOEPLITZ,
2357 EFX_RX_HASHALG_PACKED_STREAM,
2359 } efx_rx_hash_alg_t;
2362 * Legacy hash type flags.
2364 * They represent standard tuples for distinct traffic classes.
2366 #define EFX_RX_HASH_IPV4 (1U << 0)
2367 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2368 #define EFX_RX_HASH_IPV6 (1U << 2)
2369 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2371 #define EFX_RX_HASH_LEGACY_MASK \
2372 (EFX_RX_HASH_IPV4 | \
2373 EFX_RX_HASH_TCPIPV4 | \
2374 EFX_RX_HASH_IPV6 | \
2375 EFX_RX_HASH_TCPIPV6)
2378 * The type of the argument used by efx_rx_scale_mode_set() to
2379 * provide a means for the client drivers to configure hashing.
2381 * A properly constructed value can either be:
2382 * - a combination of legacy flags
2383 * - a combination of EFX_RX_HASH() flags
2385 typedef uint32_t efx_rx_hash_type_t;
2387 typedef enum efx_rx_hash_support_e {
2388 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2389 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2390 } efx_rx_hash_support_t;
2392 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2393 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2394 #define EFX_MAXRSS 64 /* RX indirection entry range */
2395 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2397 typedef enum efx_rx_scale_context_type_e {
2398 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2399 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2400 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2401 } efx_rx_scale_context_type_t;
2404 * Traffic classes eligible for hash computation.
2406 * Select packet headers used in computing the receive hash.
2407 * This uses the same encoding as the RSS_MODES field of
2408 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2410 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2411 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2412 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2413 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2414 #define EFX_RX_CLASS_IPV4_LBN 16
2415 #define EFX_RX_CLASS_IPV4_WIDTH 4
2416 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2417 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2418 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2419 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2420 #define EFX_RX_CLASS_IPV6_LBN 28
2421 #define EFX_RX_CLASS_IPV6_WIDTH 4
2423 #define EFX_RX_NCLASSES 6
2426 * Ancillary flags used to construct generic hash tuples.
2427 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2429 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2430 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2431 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2432 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2435 * Generic hash tuples.
2437 * They express combinations of packet fields
2438 * which can contribute to the hash value for
2439 * a particular traffic class.
2441 #define EFX_RX_CLASS_HASH_DISABLE 0
2443 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2444 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2446 #define EFX_RX_CLASS_HASH_2TUPLE \
2447 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2448 EFX_RX_CLASS_HASH_DST_ADDR)
2450 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2451 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2452 EFX_RX_CLASS_HASH_SRC_PORT)
2454 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2455 (EFX_RX_CLASS_HASH_DST_ADDR | \
2456 EFX_RX_CLASS_HASH_DST_PORT)
2458 #define EFX_RX_CLASS_HASH_4TUPLE \
2459 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2460 EFX_RX_CLASS_HASH_DST_ADDR | \
2461 EFX_RX_CLASS_HASH_SRC_PORT | \
2462 EFX_RX_CLASS_HASH_DST_PORT)
2464 #define EFX_RX_CLASS_HASH_NTUPLES 7
2467 * Hash flag constructor.
2469 * Resulting flags encode hash tuples for specific traffic classes.
2470 * The client drivers are encouraged to use these flags to form
2471 * a hash type value.
2473 #define EFX_RX_HASH(_class, _tuple) \
2474 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2475 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2478 * The maximum number of EFX_RX_HASH() flags.
2480 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2482 extern __checkReturn efx_rc_t
2483 efx_rx_scale_hash_flags_get(
2484 __in efx_nic_t *enp,
2485 __in efx_rx_hash_alg_t hash_alg,
2486 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
2487 __in unsigned int max_nflags,
2488 __out unsigned int *nflagsp);
2490 extern __checkReturn efx_rc_t
2491 efx_rx_hash_default_support_get(
2492 __in efx_nic_t *enp,
2493 __out efx_rx_hash_support_t *supportp);
2496 extern __checkReturn efx_rc_t
2497 efx_rx_scale_default_support_get(
2498 __in efx_nic_t *enp,
2499 __out efx_rx_scale_context_type_t *typep);
2501 extern __checkReturn efx_rc_t
2502 efx_rx_scale_context_alloc(
2503 __in efx_nic_t *enp,
2504 __in efx_rx_scale_context_type_t type,
2505 __in uint32_t num_queues,
2506 __out uint32_t *rss_contextp);
2508 extern __checkReturn efx_rc_t
2509 efx_rx_scale_context_free(
2510 __in efx_nic_t *enp,
2511 __in uint32_t rss_context);
2513 extern __checkReturn efx_rc_t
2514 efx_rx_scale_mode_set(
2515 __in efx_nic_t *enp,
2516 __in uint32_t rss_context,
2517 __in efx_rx_hash_alg_t alg,
2518 __in efx_rx_hash_type_t type,
2519 __in boolean_t insert);
2521 extern __checkReturn efx_rc_t
2522 efx_rx_scale_tbl_set(
2523 __in efx_nic_t *enp,
2524 __in uint32_t rss_context,
2525 __in_ecount(n) unsigned int *table,
2528 extern __checkReturn efx_rc_t
2529 efx_rx_scale_key_set(
2530 __in efx_nic_t *enp,
2531 __in uint32_t rss_context,
2532 __in_ecount(n) uint8_t *key,
2535 extern __checkReturn uint32_t
2536 efx_pseudo_hdr_hash_get(
2537 __in efx_rxq_t *erp,
2538 __in efx_rx_hash_alg_t func,
2539 __in uint8_t *buffer);
2541 #endif /* EFSYS_OPT_RX_SCALE */
2543 extern __checkReturn efx_rc_t
2544 efx_pseudo_hdr_pkt_length_get(
2545 __in efx_rxq_t *erp,
2546 __in uint8_t *buffer,
2547 __out uint16_t *pkt_lengthp);
2549 extern __checkReturn size_t
2551 __in const efx_nic_t *enp,
2552 __in unsigned int ndescs);
2554 extern __checkReturn unsigned int
2556 __in const efx_nic_t *enp,
2557 __in unsigned int ndescs);
2559 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2561 typedef enum efx_rxq_type_e {
2562 EFX_RXQ_TYPE_DEFAULT,
2563 EFX_RXQ_TYPE_PACKED_STREAM,
2564 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2569 * Dummy flag to be used instead of 0 to make it clear that the argument
2570 * is receive queue flags.
2572 #define EFX_RXQ_FLAG_NONE 0x0
2573 #define EFX_RXQ_FLAG_SCATTER 0x1
2575 * If tunnels are supported and Rx event can provide information about
2576 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2577 * full-feature firmware variant running), outer classes are requested by
2578 * default. However, if the driver supports tunnels, the flag allows to
2579 * request inner classes which are required to be able to interpret inner
2580 * Rx checksum offload results.
2582 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2584 extern __checkReturn efx_rc_t
2586 __in efx_nic_t *enp,
2587 __in unsigned int index,
2588 __in unsigned int label,
2589 __in efx_rxq_type_t type,
2590 __in size_t buf_size,
2591 __in efsys_mem_t *esmp,
2594 __in unsigned int flags,
2595 __in efx_evq_t *eep,
2596 __deref_out efx_rxq_t **erpp);
2598 #if EFSYS_OPT_RX_PACKED_STREAM
2600 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2601 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2602 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2603 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2604 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2606 extern __checkReturn efx_rc_t
2607 efx_rx_qcreate_packed_stream(
2608 __in efx_nic_t *enp,
2609 __in unsigned int index,
2610 __in unsigned int label,
2611 __in uint32_t ps_buf_size,
2612 __in efsys_mem_t *esmp,
2614 __in efx_evq_t *eep,
2615 __deref_out efx_rxq_t **erpp);
2619 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2621 /* Maximum head-of-line block timeout in nanoseconds */
2622 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2624 extern __checkReturn efx_rc_t
2625 efx_rx_qcreate_es_super_buffer(
2626 __in efx_nic_t *enp,
2627 __in unsigned int index,
2628 __in unsigned int label,
2629 __in uint32_t n_bufs_per_desc,
2630 __in uint32_t max_dma_len,
2631 __in uint32_t buf_stride,
2632 __in uint32_t hol_block_timeout,
2633 __in efsys_mem_t *esmp,
2635 __in unsigned int flags,
2636 __in efx_evq_t *eep,
2637 __deref_out efx_rxq_t **erpp);
2641 typedef struct efx_buffer_s {
2642 efsys_dma_addr_t eb_addr;
2647 typedef struct efx_desc_s {
2653 __in efx_rxq_t *erp,
2654 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2656 __in unsigned int ndescs,
2657 __in unsigned int completed,
2658 __in unsigned int added);
2662 __in efx_rxq_t *erp,
2663 __in unsigned int added,
2664 __inout unsigned int *pushedp);
2666 #if EFSYS_OPT_RX_PACKED_STREAM
2669 efx_rx_qpush_ps_credits(
2670 __in efx_rxq_t *erp);
2672 extern __checkReturn uint8_t *
2673 efx_rx_qps_packet_info(
2674 __in efx_rxq_t *erp,
2675 __in uint8_t *buffer,
2676 __in uint32_t buffer_length,
2677 __in uint32_t current_offset,
2678 __out uint16_t *lengthp,
2679 __out uint32_t *next_offsetp,
2680 __out uint32_t *timestamp);
2683 extern __checkReturn efx_rc_t
2685 __in efx_rxq_t *erp);
2689 __in efx_rxq_t *erp);
2693 __in efx_rxq_t *erp);
2697 typedef struct efx_txq_s efx_txq_t;
2699 #if EFSYS_OPT_QSTATS
2701 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2702 typedef enum efx_tx_qstat_e {
2708 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2710 #endif /* EFSYS_OPT_QSTATS */
2712 extern __checkReturn efx_rc_t
2714 __in efx_nic_t *enp);
2718 __in efx_nic_t *enp);
2720 extern __checkReturn size_t
2722 __in const efx_nic_t *enp,
2723 __in unsigned int ndescs);
2725 extern __checkReturn unsigned int
2727 __in const efx_nic_t *enp,
2728 __in unsigned int ndescs);
2730 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2732 #define EFX_TXQ_CKSUM_IPV4 0x0001
2733 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2734 #define EFX_TXQ_FATSOV2 0x0004
2735 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2736 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2738 extern __checkReturn efx_rc_t
2740 __in efx_nic_t *enp,
2741 __in unsigned int index,
2742 __in unsigned int label,
2743 __in efsys_mem_t *esmp,
2746 __in uint16_t flags,
2747 __in efx_evq_t *eep,
2748 __deref_out efx_txq_t **etpp,
2749 __out unsigned int *addedp);
2751 extern __checkReturn efx_rc_t
2753 __in efx_txq_t *etp,
2754 __in_ecount(ndescs) efx_buffer_t *eb,
2755 __in unsigned int ndescs,
2756 __in unsigned int completed,
2757 __inout unsigned int *addedp);
2759 extern __checkReturn efx_rc_t
2761 __in efx_txq_t *etp,
2762 __in unsigned int ns);
2766 __in efx_txq_t *etp,
2767 __in unsigned int added,
2768 __in unsigned int pushed);
2770 extern __checkReturn efx_rc_t
2772 __in efx_txq_t *etp);
2776 __in efx_txq_t *etp);
2778 extern __checkReturn efx_rc_t
2780 __in efx_txq_t *etp);
2783 efx_tx_qpio_disable(
2784 __in efx_txq_t *etp);
2786 extern __checkReturn efx_rc_t
2788 __in efx_txq_t *etp,
2789 __in_ecount(buf_length) uint8_t *buffer,
2790 __in size_t buf_length,
2791 __in size_t pio_buf_offset);
2793 extern __checkReturn efx_rc_t
2795 __in efx_txq_t *etp,
2796 __in size_t pkt_length,
2797 __in unsigned int completed,
2798 __inout unsigned int *addedp);
2800 extern __checkReturn efx_rc_t
2802 __in efx_txq_t *etp,
2803 __in_ecount(n) efx_desc_t *ed,
2804 __in unsigned int n,
2805 __in unsigned int completed,
2806 __inout unsigned int *addedp);
2809 efx_tx_qdesc_dma_create(
2810 __in efx_txq_t *etp,
2811 __in efsys_dma_addr_t addr,
2814 __out efx_desc_t *edp);
2817 efx_tx_qdesc_tso_create(
2818 __in efx_txq_t *etp,
2819 __in uint16_t ipv4_id,
2820 __in uint32_t tcp_seq,
2821 __in uint8_t tcp_flags,
2822 __out efx_desc_t *edp);
2824 /* Number of FATSOv2 option descriptors */
2825 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2827 /* Maximum number of DMA segments per TSO packet (not superframe) */
2828 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2831 efx_tx_qdesc_tso2_create(
2832 __in efx_txq_t *etp,
2833 __in uint16_t ipv4_id,
2834 __in uint16_t outer_ipv4_id,
2835 __in uint32_t tcp_seq,
2836 __in uint16_t tcp_mss,
2837 __out_ecount(count) efx_desc_t *edp,
2841 efx_tx_qdesc_vlantci_create(
2842 __in efx_txq_t *etp,
2844 __out efx_desc_t *edp);
2847 efx_tx_qdesc_checksum_create(
2848 __in efx_txq_t *etp,
2849 __in uint16_t flags,
2850 __out efx_desc_t *edp);
2852 #if EFSYS_OPT_QSTATS
2858 __in efx_nic_t *etp,
2859 __in unsigned int id);
2861 #endif /* EFSYS_OPT_NAMES */
2864 efx_tx_qstats_update(
2865 __in efx_txq_t *etp,
2866 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2868 #endif /* EFSYS_OPT_QSTATS */
2872 __in efx_txq_t *etp);
2877 #if EFSYS_OPT_FILTER
2879 #define EFX_ETHER_TYPE_IPV4 0x0800
2880 #define EFX_ETHER_TYPE_IPV6 0x86DD
2882 #define EFX_IPPROTO_TCP 6
2883 #define EFX_IPPROTO_UDP 17
2884 #define EFX_IPPROTO_GRE 47
2886 /* Use RSS to spread across multiple queues */
2887 #define EFX_FILTER_FLAG_RX_RSS 0x01
2888 /* Enable RX scatter */
2889 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2891 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2892 * May only be set by the filter implementation for each type.
2893 * A removal request will restore the automatic filter in its place.
2895 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2896 /* Filter is for RX */
2897 #define EFX_FILTER_FLAG_RX 0x08
2898 /* Filter is for TX */
2899 #define EFX_FILTER_FLAG_TX 0x10
2900 /* Set match flag on the received packet */
2901 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
2902 /* Set match mark on the received packet */
2903 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
2905 typedef uint8_t efx_filter_flags_t;
2908 * Flags which specify the fields to match on. The values are the same as in the
2909 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2912 /* Match by remote IP host address */
2913 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2914 /* Match by local IP host address */
2915 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2916 /* Match by remote MAC address */
2917 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2918 /* Match by remote TCP/UDP port */
2919 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2920 /* Match by remote TCP/UDP port */
2921 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2922 /* Match by local TCP/UDP port */
2923 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2924 /* Match by Ether-type */
2925 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2926 /* Match by inner VLAN ID */
2927 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2928 /* Match by outer VLAN ID */
2929 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2930 /* Match by IP transport protocol */
2931 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2932 /* Match by VNI or VSID */
2933 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
2934 /* For encapsulated packets, match by inner frame local MAC address */
2935 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
2936 /* For encapsulated packets, match all multicast inner frames */
2937 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2938 /* For encapsulated packets, match all unicast inner frames */
2939 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2941 * Match by encap type, this flag does not correspond to
2942 * the MCDI match flags and any unoccupied value may be used
2944 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
2945 /* Match otherwise-unmatched multicast and broadcast packets */
2946 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2947 /* Match otherwise-unmatched unicast packets */
2948 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2950 typedef uint32_t efx_filter_match_flags_t;
2952 typedef enum efx_filter_priority_s {
2953 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2954 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2955 * address list or hardware
2956 * requirements. This may only be used
2957 * by the filter implementation for
2959 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2960 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2961 * client (e.g. SR-IOV, HyperV VMQ etc.)
2963 } efx_filter_priority_t;
2966 * FIXME: All these fields are assumed to be in little-endian byte order.
2967 * It may be better for some to be big-endian. See bug42804.
2970 typedef struct efx_filter_spec_s {
2971 efx_filter_match_flags_t efs_match_flags;
2972 uint8_t efs_priority;
2973 efx_filter_flags_t efs_flags;
2974 uint16_t efs_dmaq_id;
2975 uint32_t efs_rss_context;
2977 /* Fields below here are hashed for software filter lookup */
2978 uint16_t efs_outer_vid;
2979 uint16_t efs_inner_vid;
2980 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2981 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2982 uint16_t efs_ether_type;
2983 uint8_t efs_ip_proto;
2984 efx_tunnel_protocol_t efs_encap_type;
2985 uint16_t efs_loc_port;
2986 uint16_t efs_rem_port;
2987 efx_oword_t efs_rem_host;
2988 efx_oword_t efs_loc_host;
2989 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
2990 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
2991 } efx_filter_spec_t;
2994 /* Default values for use in filter specifications */
2995 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2996 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2998 extern __checkReturn efx_rc_t
3000 __in efx_nic_t *enp);
3004 __in efx_nic_t *enp);
3006 extern __checkReturn efx_rc_t
3008 __in efx_nic_t *enp,
3009 __inout efx_filter_spec_t *spec);
3011 extern __checkReturn efx_rc_t
3013 __in efx_nic_t *enp,
3014 __inout efx_filter_spec_t *spec);
3016 extern __checkReturn efx_rc_t
3018 __in efx_nic_t *enp);
3020 extern __checkReturn efx_rc_t
3021 efx_filter_supported_filters(
3022 __in efx_nic_t *enp,
3023 __out_ecount(buffer_length) uint32_t *buffer,
3024 __in size_t buffer_length,
3025 __out size_t *list_lengthp);
3028 efx_filter_spec_init_rx(
3029 __out efx_filter_spec_t *spec,
3030 __in efx_filter_priority_t priority,
3031 __in efx_filter_flags_t flags,
3032 __in efx_rxq_t *erp);
3035 efx_filter_spec_init_tx(
3036 __out efx_filter_spec_t *spec,
3037 __in efx_txq_t *etp);
3039 extern __checkReturn efx_rc_t
3040 efx_filter_spec_set_ipv4_local(
3041 __inout efx_filter_spec_t *spec,
3044 __in uint16_t port);
3046 extern __checkReturn efx_rc_t
3047 efx_filter_spec_set_ipv4_full(
3048 __inout efx_filter_spec_t *spec,
3050 __in uint32_t lhost,
3051 __in uint16_t lport,
3052 __in uint32_t rhost,
3053 __in uint16_t rport);
3055 extern __checkReturn efx_rc_t
3056 efx_filter_spec_set_eth_local(
3057 __inout efx_filter_spec_t *spec,
3059 __in const uint8_t *addr);
3062 efx_filter_spec_set_ether_type(
3063 __inout efx_filter_spec_t *spec,
3064 __in uint16_t ether_type);
3066 extern __checkReturn efx_rc_t
3067 efx_filter_spec_set_uc_def(
3068 __inout efx_filter_spec_t *spec);
3070 extern __checkReturn efx_rc_t
3071 efx_filter_spec_set_mc_def(
3072 __inout efx_filter_spec_t *spec);
3074 typedef enum efx_filter_inner_frame_match_e {
3075 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
3076 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
3077 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
3078 } efx_filter_inner_frame_match_t;
3080 extern __checkReturn efx_rc_t
3081 efx_filter_spec_set_encap_type(
3082 __inout efx_filter_spec_t *spec,
3083 __in efx_tunnel_protocol_t encap_type,
3084 __in efx_filter_inner_frame_match_t inner_frame_match);
3086 extern __checkReturn efx_rc_t
3087 efx_filter_spec_set_vxlan(
3088 __inout efx_filter_spec_t *spec,
3089 __in const uint8_t *vni,
3090 __in const uint8_t *inner_addr,
3091 __in const uint8_t *outer_addr);
3093 extern __checkReturn efx_rc_t
3094 efx_filter_spec_set_geneve(
3095 __inout efx_filter_spec_t *spec,
3096 __in const uint8_t *vni,
3097 __in const uint8_t *inner_addr,
3098 __in const uint8_t *outer_addr);
3100 extern __checkReturn efx_rc_t
3101 efx_filter_spec_set_nvgre(
3102 __inout efx_filter_spec_t *spec,
3103 __in const uint8_t *vsid,
3104 __in const uint8_t *inner_addr,
3105 __in const uint8_t *outer_addr);
3107 #if EFSYS_OPT_RX_SCALE
3108 extern __checkReturn efx_rc_t
3109 efx_filter_spec_set_rss_context(
3110 __inout efx_filter_spec_t *spec,
3111 __in uint32_t rss_context);
3113 #endif /* EFSYS_OPT_FILTER */
3117 extern __checkReturn uint32_t
3119 __in_ecount(count) uint32_t const *input,
3121 __in uint32_t init);
3123 extern __checkReturn uint32_t
3125 __in_ecount(length) uint8_t const *input,
3127 __in uint32_t init);
3129 #if EFSYS_OPT_LICENSING
3133 typedef struct efx_key_stats_s {
3135 uint32_t eks_invalid;
3136 uint32_t eks_blacklisted;
3137 uint32_t eks_unverifiable;
3138 uint32_t eks_wrong_node;
3139 uint32_t eks_licensed_apps_lo;
3140 uint32_t eks_licensed_apps_hi;
3141 uint32_t eks_licensed_features_lo;
3142 uint32_t eks_licensed_features_hi;
3145 extern __checkReturn efx_rc_t
3147 __in efx_nic_t *enp);
3151 __in efx_nic_t *enp);
3153 extern __checkReturn boolean_t
3154 efx_lic_check_support(
3155 __in efx_nic_t *enp);
3157 extern __checkReturn efx_rc_t
3158 efx_lic_update_licenses(
3159 __in efx_nic_t *enp);
3161 extern __checkReturn efx_rc_t
3162 efx_lic_get_key_stats(
3163 __in efx_nic_t *enp,
3164 __out efx_key_stats_t *ksp);
3166 extern __checkReturn efx_rc_t
3168 __in efx_nic_t *enp,
3169 __in uint64_t app_id,
3170 __out boolean_t *licensedp);
3172 extern __checkReturn efx_rc_t
3174 __in efx_nic_t *enp,
3175 __in size_t buffer_size,
3176 __out uint32_t *typep,
3177 __out size_t *lengthp,
3178 __out_opt uint8_t *bufferp);
3181 extern __checkReturn efx_rc_t
3183 __in efx_nic_t *enp,
3184 __in_bcount(buffer_size)
3186 __in size_t buffer_size,
3187 __out uint32_t *startp);
3189 extern __checkReturn efx_rc_t
3191 __in efx_nic_t *enp,
3192 __in_bcount(buffer_size)
3194 __in size_t buffer_size,
3195 __in uint32_t offset,
3196 __out uint32_t *endp);
3198 extern __checkReturn __success(return != B_FALSE) boolean_t
3200 __in efx_nic_t *enp,
3201 __in_bcount(buffer_size)
3203 __in size_t buffer_size,
3204 __in uint32_t offset,
3205 __out uint32_t *startp,
3206 __out uint32_t *lengthp);
3208 extern __checkReturn __success(return != B_FALSE) boolean_t
3209 efx_lic_validate_key(
3210 __in efx_nic_t *enp,
3211 __in_bcount(length) caddr_t keyp,
3212 __in uint32_t length);
3214 extern __checkReturn efx_rc_t
3216 __in efx_nic_t *enp,
3217 __in_bcount(buffer_size)
3219 __in size_t buffer_size,
3220 __in uint32_t offset,
3221 __in uint32_t length,
3222 __out_bcount_part(key_max_size, *lengthp)
3224 __in size_t key_max_size,
3225 __out uint32_t *lengthp);
3227 extern __checkReturn efx_rc_t
3229 __in efx_nic_t *enp,
3230 __in_bcount(buffer_size)
3232 __in size_t buffer_size,
3233 __in uint32_t offset,
3234 __in_bcount(length) caddr_t keyp,
3235 __in uint32_t length,
3236 __out uint32_t *lengthp);
3238 __checkReturn efx_rc_t
3240 __in efx_nic_t *enp,
3241 __in_bcount(buffer_size)
3243 __in size_t buffer_size,
3244 __in uint32_t offset,
3245 __in uint32_t length,
3247 __out uint32_t *deltap);
3249 extern __checkReturn efx_rc_t
3250 efx_lic_create_partition(
3251 __in efx_nic_t *enp,
3252 __in_bcount(buffer_size)
3254 __in size_t buffer_size);
3256 extern __checkReturn efx_rc_t
3257 efx_lic_finish_partition(
3258 __in efx_nic_t *enp,
3259 __in_bcount(buffer_size)
3261 __in size_t buffer_size);
3263 #endif /* EFSYS_OPT_LICENSING */
3267 #if EFSYS_OPT_TUNNEL
3269 extern __checkReturn efx_rc_t
3271 __in efx_nic_t *enp);
3275 __in efx_nic_t *enp);
3278 * For overlay network encapsulation using UDP, the firmware needs to know
3279 * the configured UDP port for the overlay so it can decode encapsulated
3281 * The UDP port/protocol list is global.
3284 extern __checkReturn efx_rc_t
3285 efx_tunnel_config_udp_add(
3286 __in efx_nic_t *enp,
3287 __in uint16_t port /* host/cpu-endian */,
3288 __in efx_tunnel_protocol_t protocol);
3290 extern __checkReturn efx_rc_t
3291 efx_tunnel_config_udp_remove(
3292 __in efx_nic_t *enp,
3293 __in uint16_t port /* host/cpu-endian */,
3294 __in efx_tunnel_protocol_t protocol);
3297 efx_tunnel_config_clear(
3298 __in efx_nic_t *enp);
3301 * Apply tunnel UDP ports configuration to hardware.
3303 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3306 extern __checkReturn efx_rc_t
3307 efx_tunnel_reconfigure(
3308 __in efx_nic_t *enp);
3310 #endif /* EFSYS_OPT_TUNNEL */
3312 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3315 * Firmware subvariant choice options.
3317 * It may be switched to no Tx checksum if attached drivers are either
3318 * preboot or firmware subvariant aware and no VIS are allocated.
3319 * If may be always switched to default explicitly using set request or
3320 * implicitly if unaware driver is attaching. If switching is done when
3321 * a driver is attached, it gets MC_REBOOT event and should recreate its
3324 * See SF-119419-TC DPDK Firmware Driver Interface and
3325 * SF-109306-TC EF10 for Driver Writers for details.
3327 typedef enum efx_nic_fw_subvariant_e {
3328 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3329 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3330 EFX_NIC_FW_SUBVARIANT_NTYPES
3331 } efx_nic_fw_subvariant_t;
3333 extern __checkReturn efx_rc_t
3334 efx_nic_get_fw_subvariant(
3335 __in efx_nic_t *enp,
3336 __out efx_nic_fw_subvariant_t *subvariantp);
3338 extern __checkReturn efx_rc_t
3339 efx_nic_set_fw_subvariant(
3340 __in efx_nic_t *enp,
3341 __in efx_nic_fw_subvariant_t subvariant);
3343 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3345 typedef enum efx_phy_fec_type_e {
3346 EFX_PHY_FEC_NONE = 0,
3349 } efx_phy_fec_type_t;
3351 extern __checkReturn efx_rc_t
3352 efx_phy_fec_type_get(
3353 __in efx_nic_t *enp,
3354 __out efx_phy_fec_type_t *typep);
3356 typedef struct efx_phy_link_state_s {
3357 uint32_t epls_adv_cap_mask;
3358 uint32_t epls_lp_cap_mask;
3359 uint32_t epls_ld_cap_mask;
3360 unsigned int epls_fcntl;
3361 efx_phy_fec_type_t epls_fec;
3362 efx_link_mode_t epls_link_mode;
3363 } efx_phy_link_state_t;
3365 extern __checkReturn efx_rc_t
3366 efx_phy_link_state_get(
3367 __in efx_nic_t *enp,
3368 __out efx_phy_link_state_t *eplsp);
3373 typedef uint32_t efx_vswitch_id_t;
3374 typedef uint32_t efx_vport_id_t;
3376 typedef enum efx_vswitch_type_e {
3377 EFX_VSWITCH_TYPE_VLAN = 1,
3378 EFX_VSWITCH_TYPE_VEB,
3379 /* VSWITCH_TYPE_VEPA: obsolete */
3380 EFX_VSWITCH_TYPE_MUX = 4,
3381 } efx_vswitch_type_t;
3383 typedef enum efx_vport_type_e {
3384 EFX_VPORT_TYPE_NORMAL = 4,
3385 EFX_VPORT_TYPE_EXPANSION,
3386 EFX_VPORT_TYPE_TEST,
3389 /* Unspecified VLAN ID to support disabling of VLAN filtering */
3390 #define EFX_FILTER_VID_UNSPEC 0xffff
3391 #define EFX_DEFAULT_VSWITCH_ID 1
3393 /* Default VF VLAN ID on creation */
3394 #define EFX_VF_VID_DEFAULT EFX_FILTER_VID_UNSPEC
3395 #define EFX_VPORT_ID_INVALID 0
3397 typedef struct efx_vport_config_s {
3398 /* Either VF index or 0xffff for PF */
3399 uint16_t evc_function;
3400 /* VLAN ID of the associated function */
3402 /* vport id shared with client driver */
3403 efx_vport_id_t evc_vport_id;
3404 /* MAC address of the associated function */
3405 uint8_t evc_mac_addr[EFX_MAC_ADDR_LEN];
3407 * vports created with this flag set may only transfer traffic on the
3408 * VLANs permitted by the vport. Also, an attempt to install filter with
3409 * VLAN will be refused unless requesting function has VLAN privilege.
3411 boolean_t evc_vlan_restrict;
3412 /* Whether this function is assigned or not */
3413 boolean_t evc_vport_assigned;
3414 } efx_vport_config_t;
3416 typedef struct efx_vswitch_s efx_vswitch_t;
3418 extern __checkReturn efx_rc_t
3420 __in efx_nic_t *enp);
3424 __in efx_nic_t *enp);
3426 extern __checkReturn efx_rc_t
3427 efx_evb_vswitch_create(
3428 __in efx_nic_t *enp,
3429 __in uint32_t num_vports,
3430 __inout_ecount(num_vports) efx_vport_config_t *vport_configp,
3431 __deref_out efx_vswitch_t **evpp);
3433 extern __checkReturn efx_rc_t
3434 efx_evb_vswitch_destroy(
3435 __in efx_nic_t *enp,
3436 __in efx_vswitch_t *evp);
3438 extern __checkReturn efx_rc_t
3439 efx_evb_vport_mac_set(
3440 __in efx_nic_t *enp,
3441 __in efx_vswitch_t *evp,
3442 __in efx_vport_id_t vport_id,
3443 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp);
3445 extern __checkReturn efx_rc_t
3446 efx_evb_vport_vlan_set(
3447 __in efx_nic_t *enp,
3448 __in efx_vswitch_t *evp,
3449 __in efx_vport_id_t vport_id,
3452 extern __checkReturn efx_rc_t
3453 efx_evb_vport_reset(
3454 __in efx_nic_t *enp,
3455 __in efx_vswitch_t *evp,
3456 __in efx_vport_id_t vport_id,
3457 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp,
3459 __out boolean_t *is_fn_resetp);
3461 extern __checkReturn efx_rc_t
3462 efx_evb_vport_stats(
3463 __in efx_nic_t *enp,
3464 __in efx_vswitch_t *evp,
3465 __in efx_vport_id_t vport_id,
3466 __out efsys_mem_t *stats_bufferp);
3468 #endif /* EFSYS_OPT_EVB */
3470 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
3472 typedef struct efx_proxy_auth_config_s {
3473 efsys_mem_t *request_bufferp;
3474 efsys_mem_t *response_bufferp;
3475 efsys_mem_t *status_bufferp;
3479 uint32_t handled_privileges;
3480 } efx_proxy_auth_config_t;
3482 typedef struct efx_proxy_cmd_params_s {
3485 uint8_t *request_bufferp;
3486 size_t request_size;
3487 uint8_t *response_bufferp;
3488 size_t response_size;
3489 size_t *response_size_actualp;
3490 } efx_proxy_cmd_params_t;
3492 extern __checkReturn efx_rc_t
3493 efx_proxy_auth_init(
3494 __in efx_nic_t *enp);
3497 efx_proxy_auth_fini(
3498 __in efx_nic_t *enp);
3500 extern __checkReturn efx_rc_t
3501 efx_proxy_auth_configure(
3502 __in efx_nic_t *enp,
3503 __in efx_proxy_auth_config_t *configp);
3505 __checkReturn efx_rc_t
3506 efx_proxy_auth_destroy(
3507 __in efx_nic_t *enp,
3508 __in uint32_t handled_privileges);
3510 __checkReturn efx_rc_t
3511 efx_proxy_auth_complete_request(
3512 __in efx_nic_t *enp,
3513 __in uint32_t fn_index,
3514 __in uint32_t proxy_result,
3515 __in uint32_t handle);
3517 __checkReturn efx_rc_t
3518 efx_proxy_auth_exec_cmd(
3519 __in efx_nic_t *enp,
3520 __inout efx_proxy_cmd_params_t *paramsp);
3522 __checkReturn efx_rc_t
3523 efx_proxy_auth_set_privilege_mask(
3524 __in efx_nic_t *enp,
3525 __in uint32_t vf_index,
3527 __in uint32_t value);
3529 __checkReturn efx_rc_t
3530 efx_proxy_auth_privilege_mask_get(
3531 __in efx_nic_t *enp,
3532 __in uint32_t pf_index,
3533 __in uint32_t vf_index,
3534 __out uint32_t *maskp);
3536 __checkReturn efx_rc_t
3537 efx_proxy_auth_privilege_modify(
3538 __in efx_nic_t *enp,
3539 __in uint32_t pf_index,
3540 __in uint32_t vf_index,
3541 __in uint32_t add_privileges_mask,
3542 __in uint32_t remove_privileges_mask);
3544 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
3550 #endif /* _SYS_EFX_H */