1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2006-2019 Solarflare Communications Inc.
10 #include "efx_annote.h"
12 #include "efx_types.h"
13 #include "efx_check.h"
14 #include "efx_phy_ids.h"
20 #define EFX_STATIC_ASSERT(_cond) \
21 ((void)sizeof (char[(_cond) ? 1 : -1]))
23 #define EFX_ARRAY_SIZE(_array) \
24 (sizeof (_array) / sizeof ((_array)[0]))
26 #define EFX_FIELD_OFFSET(_type, _field) \
27 ((size_t)&(((_type *)0)->_field))
29 /* The macro expands divider twice */
30 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 /* Round value up to the nearest power of two. */
33 #define EFX_P2ROUNDUP(_type, _value, _align) \
34 (-(-(_type)(_value) & -(_type)(_align)))
36 /* Align value down to the nearest power of two. */
37 #define EFX_P2ALIGN(_type, _value, _align) \
38 ((_type)(_value) & -(_type)(_align))
40 /* Test if value is power of 2 aligned. */
41 #define EFX_IS_P2ALIGNED(_type, _value, _align) \
42 ((((_type)(_value)) & ((_type)(_align) - 1)) == 0)
46 typedef __success(return == 0) int efx_rc_t;
51 typedef enum efx_family_e {
53 EFX_FAMILY_FALCON, /* Obsolete and not supported */
55 EFX_FAMILY_HUNTINGTON,
62 typedef enum efx_bar_type_e {
67 typedef struct efx_bar_region_s {
68 efx_bar_type_t ebr_type;
70 efsys_dma_addr_t ebr_offset;
71 efsys_dma_addr_t ebr_length;
74 /* The function is deprecated. It is used only if Riverhead is not supported. */
76 extern __checkReturn efx_rc_t
80 __out efx_family_t *efp,
81 __out unsigned int *membarp);
85 /* PCIe interface numbers for multi-host configurations. */
86 typedef enum efx_pcie_interface_e {
87 EFX_PCIE_INTERFACE_CALLER = 1000,
88 EFX_PCIE_INTERFACE_HOST_PRIMARY,
89 EFX_PCIE_INTERFACE_NIC_EMBEDDED,
90 } efx_pcie_interface_t;
92 typedef struct efx_pci_ops_s {
94 * Function for reading PCIe configuration space.
96 * espcp System-specific PCIe device handle;
97 * offset Offset inside PCIe configuration space to start reading
99 * edp EFX DWORD structure that should be populated by function
100 * in little-endian order;
102 * Returns status code, 0 on success, any other value on error.
104 efx_rc_t (*epo_config_readd)(efsys_pci_config_t *espcp,
105 uint32_t offset, efx_dword_t *edp);
107 * Function for finding PCIe memory bar handle by its index from a PCIe
108 * device handle. The found memory bar is available in read-only mode.
110 * configp System-specific PCIe device handle;
111 * index Memory bar index;
112 * memp Pointer to the found memory bar handle;
114 * Returns status code, 0 on success, any other value on error.
116 efx_rc_t (*epo_find_mem_bar)(efsys_pci_config_t *configp,
117 int index, efsys_bar_t *memp);
120 /* Determine EFX family and perform lookup of the function control window
122 * The function requires PCI config handle from which all memory bars can
124 * A user of the API must be aware of memory bars indexes (not available
128 extern __checkReturn efx_rc_t
129 efx_family_probe_bar(
132 __in efsys_pci_config_t *espcp,
133 __in const efx_pci_ops_t *epop,
134 __out efx_family_t *efp,
135 __out efx_bar_region_t *ebrp);
137 #endif /* EFSYS_OPT_PCI */
140 #define EFX_PCI_VENID_SFC 0x1924
141 #define EFX_PCI_VENID_XILINX 0x10EE
143 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
145 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
146 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
147 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
149 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
150 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
151 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
153 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
154 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
156 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
157 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
158 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
160 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
161 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
162 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
164 #define EFX_PCI_DEVID_RIVERHEAD 0x0100
165 #define EFX_PCI_DEVID_RIVERHEAD_VF 0x1100
167 #define EFX_MEM_BAR_SIENA 2
169 #define EFX_MEM_BAR_HUNTINGTON_PF 2
170 #define EFX_MEM_BAR_HUNTINGTON_VF 0
172 #define EFX_MEM_BAR_MEDFORD_PF 2
173 #define EFX_MEM_BAR_MEDFORD_VF 0
175 #define EFX_MEM_BAR_MEDFORD2 0
177 /* FIXME Fix it when memory bar is fixed in FPGA image. It must be 0. */
178 #define EFX_MEM_BAR_RIVERHEAD 2
186 EFX_ERR_BUFID_DC_OOB,
199 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
201 extern __checkReturn uint32_t
203 __in uint32_t crc_init,
204 __in_ecount(length) uint8_t const *input,
208 /* Type prototypes */
210 typedef struct efx_rxq_s efx_rxq_t;
214 typedef struct efx_nic_s efx_nic_t;
217 extern __checkReturn efx_rc_t
219 __in efx_family_t family,
220 __in efsys_identifier_t *esip,
221 __in efsys_bar_t *esbp,
222 __in uint32_t fcw_offset,
223 __in efsys_lock_t *eslp,
224 __deref_out efx_nic_t **enpp);
226 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
227 typedef enum efx_fw_variant_e {
228 EFX_FW_VARIANT_FULL_FEATURED,
229 EFX_FW_VARIANT_LOW_LATENCY,
230 EFX_FW_VARIANT_PACKED_STREAM,
231 EFX_FW_VARIANT_HIGH_TX_RATE,
232 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
233 EFX_FW_VARIANT_RULES_ENGINE,
235 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
239 extern __checkReturn efx_rc_t
242 __in efx_fw_variant_t efv);
245 extern __checkReturn efx_rc_t
247 __in efx_nic_t *enp);
250 extern __checkReturn efx_rc_t
252 __in efx_nic_t *enp);
255 extern __checkReturn boolean_t
256 efx_nic_hw_unavailable(
257 __in efx_nic_t *enp);
261 efx_nic_set_hw_unavailable(
262 __in efx_nic_t *enp);
267 extern __checkReturn efx_rc_t
268 efx_nic_register_test(
269 __in efx_nic_t *enp);
271 #endif /* EFSYS_OPT_DIAG */
276 __in efx_nic_t *enp);
281 __in efx_nic_t *enp);
286 __in efx_nic_t *enp);
288 #define EFX_PCIE_LINK_SPEED_GEN1 1
289 #define EFX_PCIE_LINK_SPEED_GEN2 2
290 #define EFX_PCIE_LINK_SPEED_GEN3 3
292 typedef enum efx_pcie_link_performance_e {
293 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
294 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
295 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
296 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
297 } efx_pcie_link_performance_t;
300 extern __checkReturn efx_rc_t
301 efx_nic_calculate_pcie_link_bandwidth(
302 __in uint32_t pcie_link_width,
303 __in uint32_t pcie_link_gen,
304 __out uint32_t *bandwidth_mbpsp);
307 extern __checkReturn efx_rc_t
308 efx_nic_check_pcie_link_speed(
310 __in uint32_t pcie_link_width,
311 __in uint32_t pcie_link_gen,
312 __out efx_pcie_link_performance_t *resultp);
316 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
317 /* EF10 architecture and Riverhead NICs require MCDIv2 commands */
318 #define WITH_MCDI_V2 1
321 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
323 typedef enum efx_mcdi_exception_e {
324 EFX_MCDI_EXCEPTION_MC_REBOOT,
325 EFX_MCDI_EXCEPTION_MC_BADASSERT,
326 } efx_mcdi_exception_t;
328 #if EFSYS_OPT_MCDI_LOGGING
329 typedef enum efx_log_msg_e {
331 EFX_LOG_MCDI_REQUEST,
332 EFX_LOG_MCDI_RESPONSE,
334 #endif /* EFSYS_OPT_MCDI_LOGGING */
336 typedef struct efx_mcdi_transport_s {
338 efsys_mem_t *emt_dma_mem;
339 void (*emt_execute)(void *, efx_mcdi_req_t *);
340 void (*emt_ev_cpl)(void *);
341 void (*emt_exception)(void *, efx_mcdi_exception_t);
342 #if EFSYS_OPT_MCDI_LOGGING
343 void (*emt_logger)(void *, efx_log_msg_t,
344 void *, size_t, void *, size_t);
345 #endif /* EFSYS_OPT_MCDI_LOGGING */
346 #if EFSYS_OPT_MCDI_PROXY_AUTH
347 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
348 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
349 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
350 void (*emt_ev_proxy_request)(void *, uint32_t);
351 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
352 } efx_mcdi_transport_t;
355 extern __checkReturn efx_rc_t
358 __in const efx_mcdi_transport_t *mtp);
361 extern __checkReturn efx_rc_t
363 __in efx_nic_t *enp);
368 __in efx_nic_t *enp);
372 efx_mcdi_get_timeout(
374 __in efx_mcdi_req_t *emrp,
375 __out uint32_t *usec_timeoutp);
379 efx_mcdi_request_start(
381 __in efx_mcdi_req_t *emrp,
382 __in boolean_t ev_cpl);
385 extern __checkReturn boolean_t
386 efx_mcdi_request_poll(
387 __in efx_nic_t *enp);
390 extern __checkReturn boolean_t
391 efx_mcdi_request_abort(
392 __in efx_nic_t *enp);
395 extern __checkReturn efx_rc_t
396 efx_mcdi_get_client_handle(
398 __in efx_pcie_interface_t intf,
401 __out uint32_t *handle);
404 extern __checkReturn efx_rc_t
405 efx_mcdi_get_own_client_handle(
407 __out uint32_t *handle);
412 __in efx_nic_t *enp);
414 #endif /* EFSYS_OPT_MCDI */
418 #define EFX_NINTR_SIENA 1024
420 typedef enum efx_intr_type_e {
421 EFX_INTR_INVALID = 0,
427 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
430 extern __checkReturn efx_rc_t
433 __in efx_intr_type_t type,
434 __in_opt efsys_mem_t *esmp);
439 __in efx_nic_t *enp);
444 __in efx_nic_t *enp);
448 efx_intr_disable_unlocked(
449 __in efx_nic_t *enp);
451 #define EFX_INTR_NEVQS 32
454 extern __checkReturn efx_rc_t
457 __in unsigned int level);
461 efx_intr_status_line(
463 __out boolean_t *fatalp,
464 __out uint32_t *maskp);
468 efx_intr_status_message(
470 __in unsigned int message,
471 __out boolean_t *fatalp);
476 __in efx_nic_t *enp);
481 __in efx_nic_t *enp);
485 #if EFSYS_OPT_MAC_STATS
487 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
488 typedef enum efx_mac_stat_e {
491 EFX_MAC_RX_UNICST_PKTS,
492 EFX_MAC_RX_MULTICST_PKTS,
493 EFX_MAC_RX_BRDCST_PKTS,
494 EFX_MAC_RX_PAUSE_PKTS,
495 EFX_MAC_RX_LE_64_PKTS,
496 EFX_MAC_RX_65_TO_127_PKTS,
497 EFX_MAC_RX_128_TO_255_PKTS,
498 EFX_MAC_RX_256_TO_511_PKTS,
499 EFX_MAC_RX_512_TO_1023_PKTS,
500 EFX_MAC_RX_1024_TO_15XX_PKTS,
501 EFX_MAC_RX_GE_15XX_PKTS,
503 EFX_MAC_RX_FCS_ERRORS,
504 EFX_MAC_RX_DROP_EVENTS,
505 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
506 EFX_MAC_RX_SYMBOL_ERRORS,
507 EFX_MAC_RX_ALIGN_ERRORS,
508 EFX_MAC_RX_INTERNAL_ERRORS,
509 EFX_MAC_RX_JABBER_PKTS,
510 EFX_MAC_RX_LANE0_CHAR_ERR,
511 EFX_MAC_RX_LANE1_CHAR_ERR,
512 EFX_MAC_RX_LANE2_CHAR_ERR,
513 EFX_MAC_RX_LANE3_CHAR_ERR,
514 EFX_MAC_RX_LANE0_DISP_ERR,
515 EFX_MAC_RX_LANE1_DISP_ERR,
516 EFX_MAC_RX_LANE2_DISP_ERR,
517 EFX_MAC_RX_LANE3_DISP_ERR,
518 EFX_MAC_RX_MATCH_FAULT,
519 EFX_MAC_RX_NODESC_DROP_CNT,
522 EFX_MAC_TX_UNICST_PKTS,
523 EFX_MAC_TX_MULTICST_PKTS,
524 EFX_MAC_TX_BRDCST_PKTS,
525 EFX_MAC_TX_PAUSE_PKTS,
526 EFX_MAC_TX_LE_64_PKTS,
527 EFX_MAC_TX_65_TO_127_PKTS,
528 EFX_MAC_TX_128_TO_255_PKTS,
529 EFX_MAC_TX_256_TO_511_PKTS,
530 EFX_MAC_TX_512_TO_1023_PKTS,
531 EFX_MAC_TX_1024_TO_15XX_PKTS,
532 EFX_MAC_TX_GE_15XX_PKTS,
534 EFX_MAC_TX_SGL_COL_PKTS,
535 EFX_MAC_TX_MULT_COL_PKTS,
536 EFX_MAC_TX_EX_COL_PKTS,
537 EFX_MAC_TX_LATE_COL_PKTS,
539 EFX_MAC_TX_EX_DEF_PKTS,
540 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
541 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
542 EFX_MAC_PM_TRUNC_VFIFO_FULL,
543 EFX_MAC_PM_DISCARD_VFIFO_FULL,
544 EFX_MAC_PM_TRUNC_QBB,
545 EFX_MAC_PM_DISCARD_QBB,
546 EFX_MAC_PM_DISCARD_MAPPING,
547 EFX_MAC_RXDP_Q_DISABLED_PKTS,
548 EFX_MAC_RXDP_DI_DROPPED_PKTS,
549 EFX_MAC_RXDP_STREAMING_PKTS,
550 EFX_MAC_RXDP_HLB_FETCH,
551 EFX_MAC_RXDP_HLB_WAIT,
552 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
553 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
554 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
555 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
556 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
557 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
558 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
559 EFX_MAC_VADAPTER_RX_BAD_BYTES,
560 EFX_MAC_VADAPTER_RX_OVERFLOW,
561 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
562 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
563 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
564 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
565 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
566 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
567 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
568 EFX_MAC_VADAPTER_TX_BAD_BYTES,
569 EFX_MAC_VADAPTER_TX_OVERFLOW,
570 EFX_MAC_FEC_UNCORRECTED_ERRORS,
571 EFX_MAC_FEC_CORRECTED_ERRORS,
572 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
573 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
574 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
575 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
576 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
577 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
578 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
579 EFX_MAC_CTPIO_OVERFLOW_FAIL,
580 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
581 EFX_MAC_CTPIO_TIMEOUT_FAIL,
582 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
583 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
584 EFX_MAC_CTPIO_INVALID_WR_FAIL,
585 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
586 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
587 EFX_MAC_CTPIO_RUNT_FALLBACK,
588 EFX_MAC_CTPIO_SUCCESS,
589 EFX_MAC_CTPIO_FALLBACK,
590 EFX_MAC_CTPIO_POISON,
592 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
593 EFX_MAC_RXDP_HLB_IDLE,
594 EFX_MAC_RXDP_HLB_TIMEOUT,
598 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
600 #endif /* EFSYS_OPT_MAC_STATS */
602 typedef enum efx_link_mode_e {
603 EFX_LINK_UNKNOWN = 0,
619 #define EFX_MAC_ADDR_LEN 6
621 #define EFX_VNI_OR_VSID_LEN 3
623 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
625 #define EFX_MAC_MULTICAST_LIST_MAX 256
627 #define EFX_MAC_SDU_MAX 9202
629 #define EFX_MAC_PDU_ADJUSTMENT \
633 + /* bug16011 */ 16) \
635 #define EFX_MAC_PDU(_sdu) \
636 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
639 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
640 * the SDU rounded up slightly.
642 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
644 #define EFX_MAC_PDU_MIN 60
645 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
648 extern __checkReturn efx_rc_t
654 extern __checkReturn efx_rc_t
660 extern __checkReturn efx_rc_t
666 extern __checkReturn efx_rc_t
669 __in boolean_t all_unicst,
670 __in boolean_t mulcst,
671 __in boolean_t all_mulcst,
672 __in boolean_t brdcst);
676 efx_mac_filter_get_all_ucast_mcast(
678 __out boolean_t *all_unicst,
679 __out boolean_t *all_mulcst);
682 extern __checkReturn efx_rc_t
683 efx_mac_multicast_list_set(
685 __in_ecount(6*count) uint8_t const *addrs,
689 extern __checkReturn efx_rc_t
690 efx_mac_filter_default_rxq_set(
693 __in boolean_t using_rss);
697 efx_mac_filter_default_rxq_clear(
698 __in efx_nic_t *enp);
701 extern __checkReturn efx_rc_t
704 __in boolean_t enabled);
707 extern __checkReturn efx_rc_t
710 __out boolean_t *mac_upp);
712 #define EFX_FCNTL_RESPOND 0x00000001
713 #define EFX_FCNTL_GENERATE 0x00000002
716 extern __checkReturn efx_rc_t
719 __in unsigned int fcntl,
720 __in boolean_t autoneg);
726 __out unsigned int *fcntl_wantedp,
727 __out unsigned int *fcntl_linkp);
730 #if EFSYS_OPT_MAC_STATS
735 extern __checkReturn const char *
738 __in unsigned int id);
740 #endif /* EFSYS_OPT_NAMES */
742 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
744 #define EFX_MAC_STATS_MASK_NPAGES \
745 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \
746 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
747 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
750 * Get mask of MAC statistics supported by the hardware.
752 * If mask_size is insufficient to return the mask, EINVAL error is
753 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
754 * (which is sizeof (uint32_t)) is sufficient.
757 extern __checkReturn efx_rc_t
758 efx_mac_stats_get_mask(
760 __out_bcount(mask_size) uint32_t *maskp,
761 __in size_t mask_size);
763 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
764 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
765 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
769 extern __checkReturn efx_rc_t
771 __in efx_nic_t *enp);
774 * Upload mac statistics supported by the hardware into the given buffer.
776 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
777 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
779 * The hardware will only DMA statistics that it understands (of course).
780 * Drivers should not make any assumptions about which statistics are
781 * supported, especially when the statistics are generated by firmware.
783 * Thus, drivers should zero this buffer before use, so that not-understood
784 * statistics read back as zero.
787 extern __checkReturn efx_rc_t
788 efx_mac_stats_upload(
790 __in efsys_mem_t *esmp);
793 extern __checkReturn efx_rc_t
794 efx_mac_stats_periodic(
796 __in efsys_mem_t *esmp,
797 __in uint16_t period_ms,
798 __in boolean_t events);
801 extern __checkReturn efx_rc_t
802 efx_mac_stats_update(
804 __in efsys_mem_t *esmp,
805 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
806 __inout_opt uint32_t *generationp);
808 #endif /* EFSYS_OPT_MAC_STATS */
812 typedef enum efx_mon_type_e {
825 __in efx_nic_t *enp);
827 #endif /* EFSYS_OPT_NAMES */
830 extern __checkReturn efx_rc_t
832 __in efx_nic_t *enp);
834 #if EFSYS_OPT_MON_STATS
836 #define EFX_MON_STATS_PAGE_SIZE 0x100
837 #define EFX_MON_MASK_ELEMENT_SIZE 32
839 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
840 typedef enum efx_mon_stat_e {
841 EFX_MON_STAT_CONTROLLER_TEMP,
842 EFX_MON_STAT_PHY_COMMON_TEMP,
843 EFX_MON_STAT_CONTROLLER_COOLING,
844 EFX_MON_STAT_PHY0_TEMP,
845 EFX_MON_STAT_PHY0_COOLING,
846 EFX_MON_STAT_PHY1_TEMP,
847 EFX_MON_STAT_PHY1_COOLING,
853 EFX_MON_STAT_IN_12V0,
854 EFX_MON_STAT_IN_1V2A,
855 EFX_MON_STAT_IN_VREF,
856 EFX_MON_STAT_OUT_VAOE,
857 EFX_MON_STAT_AOE_TEMP,
858 EFX_MON_STAT_PSU_AOE_TEMP,
859 EFX_MON_STAT_PSU_TEMP,
865 EFX_MON_STAT_IN_VAOE,
866 EFX_MON_STAT_OUT_IAOE,
867 EFX_MON_STAT_IN_IAOE,
868 EFX_MON_STAT_NIC_POWER,
870 EFX_MON_STAT_IN_I0V9,
871 EFX_MON_STAT_IN_I1V2,
872 EFX_MON_STAT_IN_0V9_ADC,
873 EFX_MON_STAT_CONTROLLER_2_TEMP,
874 EFX_MON_STAT_VREG_INTERNAL_TEMP,
875 EFX_MON_STAT_VREG_0V9_TEMP,
876 EFX_MON_STAT_VREG_1V2_TEMP,
877 EFX_MON_STAT_CONTROLLER_VPTAT,
878 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
879 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
880 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
881 EFX_MON_STAT_AMBIENT_TEMP,
882 EFX_MON_STAT_AIRFLOW,
883 EFX_MON_STAT_VDD08D_VSS08D_CSR,
884 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
885 EFX_MON_STAT_HOTPOINT_TEMP,
886 EFX_MON_STAT_PHY_POWER_PORT0,
887 EFX_MON_STAT_PHY_POWER_PORT1,
888 EFX_MON_STAT_MUM_VCC,
889 EFX_MON_STAT_IN_0V9_A,
890 EFX_MON_STAT_IN_I0V9_A,
891 EFX_MON_STAT_VREG_0V9_A_TEMP,
892 EFX_MON_STAT_IN_0V9_B,
893 EFX_MON_STAT_IN_I0V9_B,
894 EFX_MON_STAT_VREG_0V9_B_TEMP,
895 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
896 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
897 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
898 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
899 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
900 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
901 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
902 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
903 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
904 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
905 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
906 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
907 EFX_MON_STAT_SODIMM_VOUT,
908 EFX_MON_STAT_SODIMM_0_TEMP,
909 EFX_MON_STAT_SODIMM_1_TEMP,
910 EFX_MON_STAT_PHY0_VCC,
911 EFX_MON_STAT_PHY1_VCC,
912 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
913 EFX_MON_STAT_BOARD_FRONT_TEMP,
914 EFX_MON_STAT_BOARD_BACK_TEMP,
915 EFX_MON_STAT_IN_I1V8,
916 EFX_MON_STAT_IN_I2V5,
917 EFX_MON_STAT_IN_I3V3,
918 EFX_MON_STAT_IN_I12V0,
920 EFX_MON_STAT_IN_I1V3,
924 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
926 typedef enum efx_mon_stat_state_e {
927 EFX_MON_STAT_STATE_OK = 0,
928 EFX_MON_STAT_STATE_WARNING = 1,
929 EFX_MON_STAT_STATE_FATAL = 2,
930 EFX_MON_STAT_STATE_BROKEN = 3,
931 EFX_MON_STAT_STATE_NO_READING = 4,
932 } efx_mon_stat_state_t;
934 typedef enum efx_mon_stat_unit_e {
935 EFX_MON_STAT_UNIT_UNKNOWN = 0,
936 EFX_MON_STAT_UNIT_BOOL,
937 EFX_MON_STAT_UNIT_TEMP_C,
938 EFX_MON_STAT_UNIT_VOLTAGE_MV,
939 EFX_MON_STAT_UNIT_CURRENT_MA,
940 EFX_MON_STAT_UNIT_POWER_W,
941 EFX_MON_STAT_UNIT_RPM,
943 } efx_mon_stat_unit_t;
945 typedef struct efx_mon_stat_value_s {
947 efx_mon_stat_state_t emsv_state;
948 efx_mon_stat_unit_t emsv_unit;
949 } efx_mon_stat_value_t;
951 typedef struct efx_mon_limit_value_s {
952 uint16_t emlv_warning_min;
953 uint16_t emlv_warning_max;
954 uint16_t emlv_fatal_min;
955 uint16_t emlv_fatal_max;
956 } efx_mon_stat_limits_t;
958 typedef enum efx_mon_stat_portmask_e {
959 EFX_MON_STAT_PORTMAP_NONE = 0,
960 EFX_MON_STAT_PORTMAP_PORT0 = 1,
961 EFX_MON_STAT_PORTMAP_PORT1 = 2,
962 EFX_MON_STAT_PORTMAP_PORT2 = 3,
963 EFX_MON_STAT_PORTMAP_PORT3 = 4,
964 EFX_MON_STAT_PORTMAP_ALL = (-1),
965 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
966 } efx_mon_stat_portmask_t;
974 __in efx_mon_stat_t id);
978 efx_mon_stat_description(
980 __in efx_mon_stat_t id);
982 #endif /* EFSYS_OPT_NAMES */
985 extern __checkReturn boolean_t
986 efx_mon_mcdi_to_efx_stat(
988 __out efx_mon_stat_t *statp);
991 extern __checkReturn boolean_t
992 efx_mon_get_stat_unit(
993 __in efx_mon_stat_t stat,
994 __out efx_mon_stat_unit_t *unitp);
997 extern __checkReturn boolean_t
998 efx_mon_get_stat_portmap(
999 __in efx_mon_stat_t stat,
1000 __out efx_mon_stat_portmask_t *maskp);
1003 extern __checkReturn efx_rc_t
1004 efx_mon_stats_update(
1005 __in efx_nic_t *enp,
1006 __in efsys_mem_t *esmp,
1007 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
1010 extern __checkReturn efx_rc_t
1011 efx_mon_limits_update(
1012 __in efx_nic_t *enp,
1013 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
1015 #endif /* EFSYS_OPT_MON_STATS */
1020 __in efx_nic_t *enp);
1025 extern __checkReturn efx_rc_t
1027 __in efx_nic_t *enp);
1029 typedef enum efx_phy_led_mode_e {
1030 EFX_PHY_LED_DEFAULT = 0,
1035 } efx_phy_led_mode_t;
1037 #if EFSYS_OPT_PHY_LED_CONTROL
1040 extern __checkReturn efx_rc_t
1042 __in efx_nic_t *enp,
1043 __in efx_phy_led_mode_t mode);
1045 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1048 extern __checkReturn efx_rc_t
1050 __in efx_nic_t *enp);
1052 #if EFSYS_OPT_LOOPBACK
1054 typedef enum efx_loopback_type_e {
1055 EFX_LOOPBACK_OFF = 0,
1056 EFX_LOOPBACK_DATA = 1,
1057 EFX_LOOPBACK_GMAC = 2,
1058 EFX_LOOPBACK_XGMII = 3,
1059 EFX_LOOPBACK_XGXS = 4,
1060 EFX_LOOPBACK_XAUI = 5,
1061 EFX_LOOPBACK_GMII = 6,
1062 EFX_LOOPBACK_SGMII = 7,
1063 EFX_LOOPBACK_XGBR = 8,
1064 EFX_LOOPBACK_XFI = 9,
1065 EFX_LOOPBACK_XAUI_FAR = 10,
1066 EFX_LOOPBACK_GMII_FAR = 11,
1067 EFX_LOOPBACK_SGMII_FAR = 12,
1068 EFX_LOOPBACK_XFI_FAR = 13,
1069 EFX_LOOPBACK_GPHY = 14,
1070 EFX_LOOPBACK_PHY_XS = 15,
1071 EFX_LOOPBACK_PCS = 16,
1072 EFX_LOOPBACK_PMA_PMD = 17,
1073 EFX_LOOPBACK_XPORT = 18,
1074 EFX_LOOPBACK_XGMII_WS = 19,
1075 EFX_LOOPBACK_XAUI_WS = 20,
1076 EFX_LOOPBACK_XAUI_WS_FAR = 21,
1077 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
1078 EFX_LOOPBACK_GMII_WS = 23,
1079 EFX_LOOPBACK_XFI_WS = 24,
1080 EFX_LOOPBACK_XFI_WS_FAR = 25,
1081 EFX_LOOPBACK_PHYXS_WS = 26,
1082 EFX_LOOPBACK_PMA_INT = 27,
1083 EFX_LOOPBACK_SD_NEAR = 28,
1084 EFX_LOOPBACK_SD_FAR = 29,
1085 EFX_LOOPBACK_PMA_INT_WS = 30,
1086 EFX_LOOPBACK_SD_FEP2_WS = 31,
1087 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
1088 EFX_LOOPBACK_SD_FEP_WS = 33,
1089 EFX_LOOPBACK_SD_FES_WS = 34,
1090 EFX_LOOPBACK_AOE_INT_NEAR = 35,
1091 EFX_LOOPBACK_DATA_WS = 36,
1092 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
1094 } efx_loopback_type_t;
1096 typedef enum efx_loopback_kind_e {
1097 EFX_LOOPBACK_KIND_OFF = 0,
1098 EFX_LOOPBACK_KIND_ALL,
1099 EFX_LOOPBACK_KIND_MAC,
1100 EFX_LOOPBACK_KIND_PHY,
1102 } efx_loopback_kind_t;
1107 __in efx_loopback_kind_t loopback_kind,
1108 __out efx_qword_t *maskp);
1111 extern __checkReturn efx_rc_t
1112 efx_port_loopback_set(
1113 __in efx_nic_t *enp,
1114 __in efx_link_mode_t link_mode,
1115 __in efx_loopback_type_t type);
1120 extern __checkReturn const char *
1121 efx_loopback_type_name(
1122 __in efx_nic_t *enp,
1123 __in efx_loopback_type_t type);
1125 #endif /* EFSYS_OPT_NAMES */
1127 #endif /* EFSYS_OPT_LOOPBACK */
1130 extern __checkReturn efx_rc_t
1132 __in efx_nic_t *enp,
1133 __out_opt efx_link_mode_t *link_modep);
1138 __in efx_nic_t *enp);
1140 typedef enum efx_phy_cap_type_e {
1141 EFX_PHY_CAP_INVALID = 0,
1146 EFX_PHY_CAP_1000HDX,
1147 EFX_PHY_CAP_1000FDX,
1148 EFX_PHY_CAP_10000FDX,
1152 EFX_PHY_CAP_40000FDX,
1154 EFX_PHY_CAP_100000FDX,
1155 EFX_PHY_CAP_25000FDX,
1156 EFX_PHY_CAP_50000FDX,
1157 EFX_PHY_CAP_BASER_FEC,
1158 EFX_PHY_CAP_BASER_FEC_REQUESTED,
1160 EFX_PHY_CAP_RS_FEC_REQUESTED,
1161 EFX_PHY_CAP_25G_BASER_FEC,
1162 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
1164 } efx_phy_cap_type_t;
1167 #define EFX_PHY_CAP_CURRENT 0x00000000
1168 #define EFX_PHY_CAP_DEFAULT 0x00000001
1169 #define EFX_PHY_CAP_PERM 0x00000002
1173 efx_phy_adv_cap_get(
1174 __in efx_nic_t *enp,
1176 __out uint32_t *maskp);
1179 extern __checkReturn efx_rc_t
1180 efx_phy_adv_cap_set(
1181 __in efx_nic_t *enp,
1182 __in uint32_t mask);
1187 __in efx_nic_t *enp,
1188 __out uint32_t *maskp);
1191 extern __checkReturn efx_rc_t
1193 __in efx_nic_t *enp,
1194 __out uint32_t *ouip);
1196 typedef enum efx_phy_media_type_e {
1197 EFX_PHY_MEDIA_INVALID = 0,
1202 EFX_PHY_MEDIA_SFP_PLUS,
1203 EFX_PHY_MEDIA_BASE_T,
1204 EFX_PHY_MEDIA_QSFP_PLUS,
1205 EFX_PHY_MEDIA_NTYPES
1206 } efx_phy_media_type_t;
1209 * Get the type of medium currently used. If the board has ports for
1210 * modules, a module is present, and we recognise the media type of
1211 * the module, then this will be the media type of the module.
1212 * Otherwise it will be the media type of the port.
1216 efx_phy_media_type_get(
1217 __in efx_nic_t *enp,
1218 __out efx_phy_media_type_t *typep);
1221 * 2-wire device address of the base information in accordance with SFF-8472
1222 * Diagnostic Monitoring Interface for Optical Transceivers section
1223 * 4 Memory Organization.
1225 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0
1228 * 2-wire device address of the digital diagnostics monitoring interface
1229 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical
1230 * Transceivers section 4 Memory Organization.
1232 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2
1235 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436
1236 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and
1239 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0
1242 * Maximum accessible data offset for PHY module information.
1244 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100
1248 extern __checkReturn efx_rc_t
1249 efx_phy_module_get_info(
1250 __in efx_nic_t *enp,
1251 __in uint8_t dev_addr,
1254 __out_bcount(len) uint8_t *data);
1256 #if EFSYS_OPT_PHY_STATS
1258 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1259 typedef enum efx_phy_stat_e {
1261 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1262 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1263 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1264 EFX_PHY_STAT_PMA_PMD_REV_A,
1265 EFX_PHY_STAT_PMA_PMD_REV_B,
1266 EFX_PHY_STAT_PMA_PMD_REV_C,
1267 EFX_PHY_STAT_PMA_PMD_REV_D,
1268 EFX_PHY_STAT_PCS_LINK_UP,
1269 EFX_PHY_STAT_PCS_RX_FAULT,
1270 EFX_PHY_STAT_PCS_TX_FAULT,
1271 EFX_PHY_STAT_PCS_BER,
1272 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1273 EFX_PHY_STAT_PHY_XS_LINK_UP,
1274 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1275 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1276 EFX_PHY_STAT_PHY_XS_ALIGN,
1277 EFX_PHY_STAT_PHY_XS_SYNC_A,
1278 EFX_PHY_STAT_PHY_XS_SYNC_B,
1279 EFX_PHY_STAT_PHY_XS_SYNC_C,
1280 EFX_PHY_STAT_PHY_XS_SYNC_D,
1281 EFX_PHY_STAT_AN_LINK_UP,
1282 EFX_PHY_STAT_AN_MASTER,
1283 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1284 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1285 EFX_PHY_STAT_CL22EXT_LINK_UP,
1290 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1291 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1292 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1293 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1294 EFX_PHY_STAT_AN_COMPLETE,
1295 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1296 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1297 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1298 EFX_PHY_STAT_PCS_FW_VERSION_0,
1299 EFX_PHY_STAT_PCS_FW_VERSION_1,
1300 EFX_PHY_STAT_PCS_FW_VERSION_2,
1301 EFX_PHY_STAT_PCS_FW_VERSION_3,
1302 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1303 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1304 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1305 EFX_PHY_STAT_PCS_OP_MODE,
1309 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1316 __in efx_nic_t *enp,
1317 __in efx_phy_stat_t stat);
1319 #endif /* EFSYS_OPT_NAMES */
1321 #define EFX_PHY_STATS_SIZE 0x100
1324 extern __checkReturn efx_rc_t
1325 efx_phy_stats_update(
1326 __in efx_nic_t *enp,
1327 __in efsys_mem_t *esmp,
1328 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1330 #endif /* EFSYS_OPT_PHY_STATS */
1335 typedef enum efx_bist_type_e {
1336 EFX_BIST_TYPE_UNKNOWN,
1337 EFX_BIST_TYPE_PHY_NORMAL,
1338 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1339 EFX_BIST_TYPE_PHY_CABLE_LONG,
1340 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1341 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1342 EFX_BIST_TYPE_REG, /* Test the register memories */
1343 EFX_BIST_TYPE_NTYPES,
1346 typedef enum efx_bist_result_e {
1347 EFX_BIST_RESULT_UNKNOWN,
1348 EFX_BIST_RESULT_RUNNING,
1349 EFX_BIST_RESULT_PASSED,
1350 EFX_BIST_RESULT_FAILED,
1351 } efx_bist_result_t;
1353 typedef enum efx_phy_cable_status_e {
1354 EFX_PHY_CABLE_STATUS_OK,
1355 EFX_PHY_CABLE_STATUS_INVALID,
1356 EFX_PHY_CABLE_STATUS_OPEN,
1357 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1358 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1359 EFX_PHY_CABLE_STATUS_BUSY,
1360 } efx_phy_cable_status_t;
1362 typedef enum efx_bist_value_e {
1363 EFX_BIST_PHY_CABLE_LENGTH_A,
1364 EFX_BIST_PHY_CABLE_LENGTH_B,
1365 EFX_BIST_PHY_CABLE_LENGTH_C,
1366 EFX_BIST_PHY_CABLE_LENGTH_D,
1367 EFX_BIST_PHY_CABLE_STATUS_A,
1368 EFX_BIST_PHY_CABLE_STATUS_B,
1369 EFX_BIST_PHY_CABLE_STATUS_C,
1370 EFX_BIST_PHY_CABLE_STATUS_D,
1371 EFX_BIST_FAULT_CODE,
1373 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1379 EFX_BIST_MEM_EXPECT,
1380 EFX_BIST_MEM_ACTUAL,
1382 EFX_BIST_MEM_ECC_PARITY,
1383 EFX_BIST_MEM_ECC_FATAL,
1388 extern __checkReturn efx_rc_t
1389 efx_bist_enable_offline(
1390 __in efx_nic_t *enp);
1393 extern __checkReturn efx_rc_t
1395 __in efx_nic_t *enp,
1396 __in efx_bist_type_t type);
1399 extern __checkReturn efx_rc_t
1401 __in efx_nic_t *enp,
1402 __in efx_bist_type_t type,
1403 __out efx_bist_result_t *resultp,
1404 __out_opt uint32_t *value_maskp,
1405 __out_ecount_opt(count) unsigned long *valuesp,
1411 __in efx_nic_t *enp,
1412 __in efx_bist_type_t type);
1414 #endif /* EFSYS_OPT_BIST */
1416 #define EFX_FEATURE_IPV6 0x00000001
1417 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1418 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1419 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1420 #define EFX_FEATURE_MCDI 0x00000020
1421 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1422 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1423 #define EFX_FEATURE_TURBO 0x00000100
1424 #define EFX_FEATURE_MCDI_DMA 0x00000200
1425 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1426 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1427 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1428 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1429 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1430 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000
1432 typedef enum efx_tunnel_protocol_e {
1433 EFX_TUNNEL_PROTOCOL_NONE = 0,
1434 EFX_TUNNEL_PROTOCOL_VXLAN,
1435 EFX_TUNNEL_PROTOCOL_GENEVE,
1436 EFX_TUNNEL_PROTOCOL_NVGRE,
1438 } efx_tunnel_protocol_t;
1440 typedef enum efx_vi_window_shift_e {
1441 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1442 EFX_VI_WINDOW_SHIFT_8K = 13,
1443 EFX_VI_WINDOW_SHIFT_16K = 14,
1444 EFX_VI_WINDOW_SHIFT_64K = 16,
1445 } efx_vi_window_shift_t;
1447 typedef struct efx_nic_cfg_s {
1448 uint32_t enc_board_type;
1449 uint32_t enc_phy_type;
1451 char enc_phy_name[21];
1453 char enc_phy_revision[21];
1454 efx_mon_type_t enc_mon_type;
1455 #if EFSYS_OPT_MON_STATS
1456 uint32_t enc_mon_stat_dma_buf_size;
1457 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1459 unsigned int enc_features;
1460 efx_vi_window_shift_t enc_vi_window_shift;
1461 uint8_t enc_mac_addr[6];
1462 uint8_t enc_port; /* PHY port number */
1463 uint32_t enc_intr_vec_base;
1464 uint32_t enc_intr_limit;
1465 uint32_t enc_evq_limit;
1466 uint32_t enc_txq_limit;
1467 uint32_t enc_rxq_limit;
1468 uint32_t enc_evq_max_nevs;
1469 uint32_t enc_evq_min_nevs;
1470 uint32_t enc_rxq_max_ndescs;
1471 uint32_t enc_rxq_min_ndescs;
1472 uint32_t enc_txq_max_ndescs;
1473 uint32_t enc_txq_min_ndescs;
1474 uint32_t enc_buftbl_limit;
1475 uint32_t enc_piobuf_limit;
1476 uint32_t enc_piobuf_size;
1477 uint32_t enc_piobuf_min_alloc_size;
1478 uint32_t enc_evq_timer_quantum_ns;
1479 uint32_t enc_evq_timer_max_us;
1480 uint32_t enc_clk_mult;
1481 uint32_t enc_ev_ew_desc_size;
1482 uint32_t enc_ev_desc_size;
1483 uint32_t enc_rx_desc_size;
1484 uint32_t enc_tx_desc_size;
1485 /* Maximum Rx prefix size if many Rx prefixes are supported */
1486 uint32_t enc_rx_prefix_size;
1487 uint32_t enc_rx_buf_align_start;
1488 uint32_t enc_rx_buf_align_end;
1489 #if EFSYS_OPT_RX_SCALE
1490 uint32_t enc_rx_scale_max_exclusive_contexts;
1492 * Mask of supported hash algorithms.
1493 * Hash algorithm types are used as the bit indices.
1495 uint32_t enc_rx_scale_hash_alg_mask;
1497 * Indicates whether port numbers can be included to the
1498 * input data for hash computation.
1500 boolean_t enc_rx_scale_l4_hash_supported;
1501 boolean_t enc_rx_scale_additional_modes_supported;
1502 #endif /* EFSYS_OPT_RX_SCALE */
1503 #if EFSYS_OPT_LOOPBACK
1504 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1505 #endif /* EFSYS_OPT_LOOPBACK */
1506 #if EFSYS_OPT_PHY_FLAGS
1507 uint32_t enc_phy_flags_mask;
1508 #endif /* EFSYS_OPT_PHY_FLAGS */
1509 #if EFSYS_OPT_PHY_LED_CONTROL
1510 uint32_t enc_led_mask;
1511 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1512 #if EFSYS_OPT_PHY_STATS
1513 uint64_t enc_phy_stat_mask;
1514 #endif /* EFSYS_OPT_PHY_STATS */
1516 uint8_t enc_mcdi_mdio_channel;
1517 #if EFSYS_OPT_PHY_STATS
1518 uint32_t enc_mcdi_phy_stat_mask;
1519 #endif /* EFSYS_OPT_PHY_STATS */
1520 #if EFSYS_OPT_MON_STATS
1521 uint32_t *enc_mcdi_sensor_maskp;
1522 uint32_t enc_mcdi_sensor_mask_size;
1523 #endif /* EFSYS_OPT_MON_STATS */
1524 #endif /* EFSYS_OPT_MCDI */
1526 uint32_t enc_bist_mask;
1527 #endif /* EFSYS_OPT_BIST */
1528 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
1529 efx_pcie_interface_t enc_intf;
1532 uint32_t enc_privilege_mask;
1533 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
1534 boolean_t enc_evq_init_done_ev_supported;
1535 boolean_t enc_bug26807_workaround;
1536 boolean_t enc_bug35388_workaround;
1537 boolean_t enc_bug41750_workaround;
1538 boolean_t enc_bug61265_workaround;
1539 boolean_t enc_bug61297_workaround;
1540 boolean_t enc_rx_batching_enabled;
1541 /* Maximum number of descriptors completed in an rx event. */
1542 uint32_t enc_rx_batch_max;
1543 /* Number of rx descriptors the hardware requires for a push. */
1544 uint32_t enc_rx_push_align;
1545 /* Maximum amount of data in DMA descriptor */
1546 uint32_t enc_tx_dma_desc_size_max;
1548 * Boundary which DMA descriptor data must not cross or 0 if no
1551 uint32_t enc_tx_dma_desc_boundary;
1553 * Maximum number of bytes into the packet the TCP header can start for
1554 * the hardware to apply TSO packet edits.
1556 uint32_t enc_tx_tso_tcp_header_offset_limit;
1557 /* Maximum number of header DMA descriptors per TSO transaction. */
1558 uint32_t enc_tx_tso_max_header_ndescs;
1559 /* Maximum header length acceptable by TSO transaction. */
1560 uint32_t enc_tx_tso_max_header_length;
1561 /* Maximum number of payload DMA descriptors per TSO transaction. */
1562 uint32_t enc_tx_tso_max_payload_ndescs;
1563 /* Maximum payload length per TSO transaction. */
1564 uint32_t enc_tx_tso_max_payload_length;
1565 /* Maximum number of frames to be generated per TSO transaction. */
1566 uint32_t enc_tx_tso_max_nframes;
1567 boolean_t enc_fw_assisted_tso_enabled;
1568 boolean_t enc_fw_assisted_tso_v2_enabled;
1569 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1570 boolean_t enc_tso_v3_enabled;
1571 /* Number of TSO contexts on the NIC (FATSOv2) */
1572 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1573 boolean_t enc_hw_tx_insert_vlan_enabled;
1574 /* Number of PFs on the NIC */
1575 uint32_t enc_hw_pf_count;
1576 /* Datapath firmware vadapter/vport/vswitch support */
1577 boolean_t enc_datapath_cap_evb;
1578 /* Datapath firmware vport reconfigure support */
1579 boolean_t enc_vport_reconfigure_supported;
1580 boolean_t enc_rx_disable_scatter_supported;
1581 /* Maximum number of Rx scatter segments supported by HW */
1582 uint32_t enc_rx_scatter_max;
1583 boolean_t enc_allow_set_mac_with_installed_filters;
1584 boolean_t enc_enhanced_set_mac_supported;
1585 boolean_t enc_init_evq_v2_supported;
1586 boolean_t enc_init_evq_extended_width_supported;
1587 boolean_t enc_no_cont_ev_mode_supported;
1588 boolean_t enc_init_rxq_with_buffer_size;
1589 boolean_t enc_rx_packed_stream_supported;
1590 boolean_t enc_rx_var_packed_stream_supported;
1591 boolean_t enc_rx_es_super_buffer_supported;
1592 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1593 boolean_t enc_pm_and_rxdp_counters;
1594 boolean_t enc_mac_stats_40g_tx_size_bins;
1595 uint32_t enc_tunnel_encapsulations_supported;
1597 * NIC global maximum for unique UDP tunnel ports shared by all
1600 uint32_t enc_tunnel_config_udp_entries_max;
1601 /* External port identifier */
1602 uint8_t enc_external_port;
1603 uint32_t enc_mcdi_max_payload_length;
1604 /* VPD may be per-PF or global */
1605 boolean_t enc_vpd_is_global;
1606 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1607 uint32_t enc_required_pcie_bandwidth_mbps;
1608 uint32_t enc_max_pcie_link_gen;
1609 /* Firmware verifies integrity of NVRAM updates */
1610 boolean_t enc_nvram_update_verify_result_supported;
1611 /* Firmware supports polled NVRAM updates on select partitions */
1612 boolean_t enc_nvram_update_poll_verify_result_supported;
1613 /* Firmware accepts updates via the BUNDLE partition */
1614 boolean_t enc_nvram_bundle_update_supported;
1615 /* Firmware support for extended MAC_STATS buffer */
1616 uint32_t enc_mac_stats_nstats;
1617 boolean_t enc_fec_counters;
1618 boolean_t enc_hlb_counters;
1619 /* NIC support for Match-Action Engine (MAE). */
1620 boolean_t enc_mae_supported;
1622 * NIC is privileged, i.e. it is the MAE admin.
1623 * Only privileged MAE clients can manage MAE flow rules,
1624 * for example, modify, count and route traffic to selected
1625 * destination (a MAE client or network port).
1627 boolean_t enc_mae_admin;
1628 /* Firmware support for "FLAG" and "MARK" filter actions */
1629 boolean_t enc_filter_action_flag_supported;
1630 boolean_t enc_filter_action_mark_supported;
1631 uint32_t enc_filter_action_mark_max;
1632 /* Port assigned to this PCI function */
1633 uint32_t enc_assigned_port;
1636 #define EFX_PCI_VF_INVALID 0xffff
1638 #define EFX_VPORT_PCI_FUNCTION_IS_PF(configp) \
1639 ((configp)->evc_function == EFX_PCI_VF_INVALID)
1641 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == EFX_PCI_VF_INVALID)
1642 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != EFX_PCI_VF_INVALID)
1644 #define EFX_PCI_FUNCTION(_encp) \
1645 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1647 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1650 extern const efx_nic_cfg_t *
1652 __in const efx_nic_t *enp);
1654 /* RxDPCPU firmware id values by which FW variant can be identified */
1655 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1656 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1657 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1658 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1659 #define EFX_RXDP_DPDK_FW_ID 0x6
1661 typedef struct efx_nic_fw_info_s {
1662 /* Basic FW version information */
1663 uint16_t enfi_mc_fw_version[4];
1665 * If datapath capabilities can be detected,
1666 * additional FW information is to be shown
1668 boolean_t enfi_dpcpu_fw_ids_valid;
1669 /* Rx and Tx datapath CPU FW IDs */
1670 uint16_t enfi_rx_dpcpu_fw_id;
1671 uint16_t enfi_tx_dpcpu_fw_id;
1672 } efx_nic_fw_info_t;
1675 extern __checkReturn efx_rc_t
1676 efx_nic_get_fw_version(
1677 __in efx_nic_t *enp,
1678 __out efx_nic_fw_info_t *enfip);
1680 #define EFX_NIC_BOARD_INFO_SERIAL_LEN (64)
1681 #define EFX_NIC_BOARD_INFO_NAME_LEN (16)
1683 typedef struct efx_nic_board_info_s {
1684 /* The following two fields are NUL-terminated ASCII strings. */
1685 char enbi_serial[EFX_NIC_BOARD_INFO_SERIAL_LEN];
1686 char enbi_name[EFX_NIC_BOARD_INFO_NAME_LEN];
1687 uint32_t enbi_revision;
1688 } efx_nic_board_info_t;
1691 extern __checkReturn efx_rc_t
1692 efx_nic_get_board_info(
1693 __in efx_nic_t *enp,
1694 __out efx_nic_board_info_t *board_infop);
1696 /* Driver resource limits (minimum required/maximum usable). */
1697 typedef struct efx_drv_limits_s {
1698 uint32_t edl_min_evq_count;
1699 uint32_t edl_max_evq_count;
1701 uint32_t edl_min_rxq_count;
1702 uint32_t edl_max_rxq_count;
1704 uint32_t edl_min_txq_count;
1705 uint32_t edl_max_txq_count;
1707 /* PIO blocks (sub-allocated from piobuf) */
1708 uint32_t edl_min_pio_alloc_size;
1709 uint32_t edl_max_pio_alloc_count;
1713 extern __checkReturn efx_rc_t
1714 efx_nic_set_drv_limits(
1715 __inout efx_nic_t *enp,
1716 __in efx_drv_limits_t *edlp);
1719 * Register the OS driver version string for management agents
1720 * (e.g. via NC-SI). The content length is provided (i.e. no
1721 * NUL terminator). Use length 0 to indicate no version string
1722 * should be advertised. It is valid to set the version string
1723 * only before efx_nic_probe() is called.
1726 extern __checkReturn efx_rc_t
1727 efx_nic_set_drv_version(
1728 __inout efx_nic_t *enp,
1729 __in_ecount(length) char const *verp,
1730 __in size_t length);
1732 typedef enum efx_nic_region_e {
1733 EFX_REGION_VI, /* Memory BAR UC mapping */
1734 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1738 extern __checkReturn efx_rc_t
1739 efx_nic_get_bar_region(
1740 __in efx_nic_t *enp,
1741 __in efx_nic_region_t region,
1742 __out uint32_t *offsetp,
1743 __out size_t *sizep);
1746 extern __checkReturn efx_rc_t
1747 efx_nic_get_vi_pool(
1748 __in efx_nic_t *enp,
1749 __out uint32_t *evq_countp,
1750 __out uint32_t *rxq_countp,
1751 __out uint32_t *txq_countp);
1756 typedef enum efx_vpd_tag_e {
1763 typedef uint16_t efx_vpd_keyword_t;
1765 typedef struct efx_vpd_value_s {
1766 efx_vpd_tag_t evv_tag;
1767 efx_vpd_keyword_t evv_keyword;
1769 uint8_t evv_value[0x100];
1773 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1776 extern __checkReturn efx_rc_t
1778 __in efx_nic_t *enp);
1781 extern __checkReturn efx_rc_t
1783 __in efx_nic_t *enp,
1784 __out size_t *sizep);
1787 extern __checkReturn efx_rc_t
1789 __in efx_nic_t *enp,
1790 __out_bcount(size) caddr_t data,
1794 extern __checkReturn efx_rc_t
1796 __in efx_nic_t *enp,
1797 __in_bcount(size) caddr_t data,
1801 extern __checkReturn efx_rc_t
1803 __in efx_nic_t *enp,
1804 __in_bcount(size) caddr_t data,
1808 extern __checkReturn efx_rc_t
1810 __in efx_nic_t *enp,
1811 __in_bcount(size) caddr_t data,
1813 __inout efx_vpd_value_t *evvp);
1816 extern __checkReturn efx_rc_t
1818 __in efx_nic_t *enp,
1819 __inout_bcount(size) caddr_t data,
1821 __in efx_vpd_value_t *evvp);
1824 extern __checkReturn efx_rc_t
1826 __in efx_nic_t *enp,
1827 __inout_bcount(size) caddr_t data,
1829 __out efx_vpd_value_t *evvp,
1830 __inout unsigned int *contp);
1833 extern __checkReturn efx_rc_t
1835 __in efx_nic_t *enp,
1836 __in_bcount(size) caddr_t data,
1842 __in efx_nic_t *enp);
1844 #endif /* EFSYS_OPT_VPD */
1850 typedef enum efx_nvram_type_e {
1851 EFX_NVRAM_INVALID = 0,
1853 EFX_NVRAM_BOOTROM_CFG,
1854 EFX_NVRAM_MC_FIRMWARE,
1855 EFX_NVRAM_MC_GOLDEN,
1861 EFX_NVRAM_FPGA_BACKUP,
1862 EFX_NVRAM_DYNAMIC_CFG,
1865 EFX_NVRAM_MUM_FIRMWARE,
1866 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1867 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1869 EFX_NVRAM_BUNDLE_METADATA,
1873 typedef struct efx_nvram_info_s {
1875 uint32_t eni_partn_size;
1876 uint32_t eni_address;
1877 uint32_t eni_erase_size;
1878 uint32_t eni_write_size;
1881 #define EFX_NVRAM_FLAG_READ_ONLY (1 << 0)
1884 extern __checkReturn efx_rc_t
1886 __in efx_nic_t *enp);
1891 extern __checkReturn efx_rc_t
1893 __in efx_nic_t *enp);
1895 #endif /* EFSYS_OPT_DIAG */
1898 extern __checkReturn efx_rc_t
1900 __in efx_nic_t *enp,
1901 __in efx_nvram_type_t type,
1902 __out size_t *sizep);
1905 extern __checkReturn efx_rc_t
1907 __in efx_nic_t *enp,
1908 __in efx_nvram_type_t type,
1909 __out efx_nvram_info_t *enip);
1912 extern __checkReturn efx_rc_t
1914 __in efx_nic_t *enp,
1915 __in efx_nvram_type_t type,
1916 __out_opt size_t *pref_chunkp);
1919 extern __checkReturn efx_rc_t
1920 efx_nvram_rw_finish(
1921 __in efx_nic_t *enp,
1922 __in efx_nvram_type_t type,
1923 __out_opt uint32_t *verify_resultp);
1926 extern __checkReturn efx_rc_t
1927 efx_nvram_get_version(
1928 __in efx_nic_t *enp,
1929 __in efx_nvram_type_t type,
1930 __out uint32_t *subtypep,
1931 __out_ecount(4) uint16_t version[4]);
1934 extern __checkReturn efx_rc_t
1935 efx_nvram_read_chunk(
1936 __in efx_nic_t *enp,
1937 __in efx_nvram_type_t type,
1938 __in unsigned int offset,
1939 __out_bcount(size) caddr_t data,
1943 extern __checkReturn efx_rc_t
1944 efx_nvram_read_backup(
1945 __in efx_nic_t *enp,
1946 __in efx_nvram_type_t type,
1947 __in unsigned int offset,
1948 __out_bcount(size) caddr_t data,
1952 extern __checkReturn efx_rc_t
1953 efx_nvram_set_version(
1954 __in efx_nic_t *enp,
1955 __in efx_nvram_type_t type,
1956 __in_ecount(4) uint16_t version[4]);
1959 extern __checkReturn efx_rc_t
1961 __in efx_nic_t *enp,
1962 __in efx_nvram_type_t type,
1963 __in_bcount(partn_size) caddr_t partn_data,
1964 __in size_t partn_size);
1967 extern __checkReturn efx_rc_t
1969 __in efx_nic_t *enp,
1970 __in efx_nvram_type_t type);
1973 extern __checkReturn efx_rc_t
1974 efx_nvram_write_chunk(
1975 __in efx_nic_t *enp,
1976 __in efx_nvram_type_t type,
1977 __in unsigned int offset,
1978 __in_bcount(size) caddr_t data,
1984 __in efx_nic_t *enp);
1986 #endif /* EFSYS_OPT_NVRAM */
1988 #if EFSYS_OPT_BOOTCFG
1990 /* Report size and offset of bootcfg sector in NVRAM partition. */
1992 extern __checkReturn efx_rc_t
1993 efx_bootcfg_sector_info(
1994 __in efx_nic_t *enp,
1996 __out_opt uint32_t *sector_countp,
1997 __out size_t *offsetp,
1998 __out size_t *max_sizep);
2001 * Copy bootcfg sector data to a target buffer which may differ in size.
2002 * Optionally corrects format errors in source buffer.
2006 efx_bootcfg_copy_sector(
2007 __in efx_nic_t *enp,
2008 __inout_bcount(sector_length)
2010 __in size_t sector_length,
2011 __out_bcount(data_size) uint8_t *data,
2012 __in size_t data_size,
2013 __in boolean_t handle_format_errors);
2018 __in efx_nic_t *enp,
2019 __out_bcount(size) uint8_t *data,
2025 __in efx_nic_t *enp,
2026 __in_bcount(size) uint8_t *data,
2031 * Processing routines for buffers arranged in the DHCP/BOOTP option format
2032 * (see https://tools.ietf.org/html/rfc1533)
2034 * Summarising the format: the buffer is a sequence of options. All options
2035 * begin with a tag octet, which uniquely identifies the option. Fixed-
2036 * length options without data consist of only a tag octet. Only options PAD
2037 * (0) and END (255) are fixed length. All other options are variable-length
2038 * with a length octet following the tag octet. The value of the length
2039 * octet does not include the two octets specifying the tag and length. The
2040 * length octet is followed by "length" octets of data.
2042 * Option data may be a sequence of sub-options in the same format. The data
2043 * content of the encapsulating option is one or more encapsulated sub-options,
2044 * with no terminating END tag is required.
2046 * To be valid, the top-level sequence of options should be terminated by an
2047 * END tag. The buffer should be padded with the PAD byte.
2049 * When stored to NVRAM, the DHCP option format buffer is preceded by a
2050 * checksum octet. The full buffer (including after the END tag) contributes
2051 * to the checksum, hence the need to fill the buffer to the end with PAD.
2054 #define EFX_DHCP_END ((uint8_t)0xff)
2055 #define EFX_DHCP_PAD ((uint8_t)0)
2057 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \
2058 (uint16_t)(((encapsulator) << 8) | (encapsulated))
2061 extern __checkReturn uint8_t
2063 __in_bcount(size) uint8_t const *data,
2067 extern __checkReturn efx_rc_t
2069 __in_bcount(size) uint8_t const *data,
2071 __out_opt size_t *usedp);
2074 extern __checkReturn efx_rc_t
2076 __in_bcount(buffer_length) uint8_t *bufferp,
2077 __in size_t buffer_length,
2079 __deref_out uint8_t **valuepp,
2080 __out size_t *value_lengthp);
2083 extern __checkReturn efx_rc_t
2085 __in_bcount(buffer_length) uint8_t *bufferp,
2086 __in size_t buffer_length,
2087 __deref_out uint8_t **endpp);
2091 extern __checkReturn efx_rc_t
2092 efx_dhcp_delete_tag(
2093 __inout_bcount(buffer_length) uint8_t *bufferp,
2094 __in size_t buffer_length,
2098 extern __checkReturn efx_rc_t
2100 __inout_bcount(buffer_length) uint8_t *bufferp,
2101 __in size_t buffer_length,
2103 __in_bcount_opt(value_length) uint8_t *valuep,
2104 __in size_t value_length);
2107 extern __checkReturn efx_rc_t
2108 efx_dhcp_update_tag(
2109 __inout_bcount(buffer_length) uint8_t *bufferp,
2110 __in size_t buffer_length,
2112 __in uint8_t *value_locationp,
2113 __in_bcount_opt(value_length) uint8_t *valuep,
2114 __in size_t value_length);
2117 #endif /* EFSYS_OPT_BOOTCFG */
2119 #if EFSYS_OPT_IMAGE_LAYOUT
2121 #include "ef10_signed_image_layout.h"
2124 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
2127 * The image header format is extensible. However, older drivers require an
2128 * exact match of image header version and header length when validating and
2129 * writing firmware images.
2131 * To avoid breaking backward compatibility, we use the upper bits of the
2132 * controller version fields to contain an extra version number used for
2133 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
2134 * version). See bug39254 and SF-102785-PS for details.
2136 typedef struct efx_image_header_s {
2138 uint32_t eih_version;
2140 uint32_t eih_subtype;
2141 uint32_t eih_code_size;
2144 uint32_t eih_controller_version_min;
2146 uint16_t eih_controller_version_min_short;
2147 uint8_t eih_extra_version_a;
2148 uint8_t eih_extra_version_b;
2152 uint32_t eih_controller_version_max;
2154 uint16_t eih_controller_version_max_short;
2155 uint8_t eih_extra_version_c;
2156 uint8_t eih_extra_version_d;
2159 uint16_t eih_code_version_a;
2160 uint16_t eih_code_version_b;
2161 uint16_t eih_code_version_c;
2162 uint16_t eih_code_version_d;
2163 } efx_image_header_t;
2165 #define EFX_IMAGE_HEADER_SIZE (40)
2166 #define EFX_IMAGE_HEADER_VERSION (4)
2167 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
2170 typedef struct efx_image_trailer_s {
2172 } efx_image_trailer_t;
2174 #define EFX_IMAGE_TRAILER_SIZE (4)
2176 typedef enum efx_image_format_e {
2177 EFX_IMAGE_FORMAT_NO_IMAGE,
2178 EFX_IMAGE_FORMAT_INVALID,
2179 EFX_IMAGE_FORMAT_UNSIGNED,
2180 EFX_IMAGE_FORMAT_SIGNED,
2181 EFX_IMAGE_FORMAT_SIGNED_PACKAGE
2182 } efx_image_format_t;
2184 typedef struct efx_image_info_s {
2185 efx_image_format_t eii_format;
2186 uint8_t * eii_imagep;
2187 size_t eii_image_size;
2188 efx_image_header_t * eii_headerp;
2192 extern __checkReturn efx_rc_t
2193 efx_check_reflash_image(
2195 __in uint32_t buffer_size,
2196 __out efx_image_info_t *infop);
2199 extern __checkReturn efx_rc_t
2200 efx_build_signed_image_write_buffer(
2201 __out_bcount(buffer_size)
2203 __in uint32_t buffer_size,
2204 __in efx_image_info_t *infop,
2205 __out efx_image_header_t **headerpp);
2207 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
2211 typedef enum efx_pattern_type_t {
2212 EFX_PATTERN_BYTE_INCREMENT = 0,
2213 EFX_PATTERN_ALL_THE_SAME,
2214 EFX_PATTERN_BIT_ALTERNATE,
2215 EFX_PATTERN_BYTE_ALTERNATE,
2216 EFX_PATTERN_BYTE_CHANGING,
2217 EFX_PATTERN_BIT_SWEEP,
2219 } efx_pattern_type_t;
2222 (*efx_sram_pattern_fn_t)(
2224 __in boolean_t negate,
2225 __out efx_qword_t *eqp);
2228 extern __checkReturn efx_rc_t
2230 __in efx_nic_t *enp,
2231 __in efx_pattern_type_t type);
2233 #endif /* EFSYS_OPT_DIAG */
2236 extern __checkReturn efx_rc_t
2237 efx_sram_buf_tbl_set(
2238 __in efx_nic_t *enp,
2240 __in efsys_mem_t *esmp,
2245 efx_sram_buf_tbl_clear(
2246 __in efx_nic_t *enp,
2250 #define EFX_BUF_TBL_SIZE 0x20000
2252 #define EFX_BUF_SIZE 4096
2256 typedef struct efx_evq_s efx_evq_t;
2258 #if EFSYS_OPT_QSTATS
2260 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 0a147ace40844969 */
2261 typedef enum efx_ev_qstat_e {
2267 EV_RX_PAUSE_FRM_ERR,
2268 EV_RX_BUF_OWNER_ID_ERR,
2269 EV_RX_IPV4_HDR_CHKSUM_ERR,
2270 EV_RX_TCP_UDP_CHKSUM_ERR,
2274 EV_RX_MCAST_HASH_MATCH,
2291 EV_DRIVER_SRM_UPD_DONE,
2292 EV_DRIVER_TX_DESCQ_FLS_DONE,
2293 EV_DRIVER_RX_DESCQ_FLS_DONE,
2294 EV_DRIVER_RX_DESCQ_FLS_FAILED,
2295 EV_DRIVER_RX_DSC_ERROR,
2296 EV_DRIVER_TX_DSC_ERROR,
2299 EV_RX_PARSE_INCOMPLETE,
2303 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
2305 #endif /* EFSYS_OPT_QSTATS */
2308 extern __checkReturn efx_rc_t
2310 __in efx_nic_t *enp);
2315 __in efx_nic_t *enp);
2318 extern __checkReturn size_t
2320 __in const efx_nic_t *enp,
2321 __in unsigned int ndescs,
2322 __in uint32_t flags);
2325 extern __checkReturn unsigned int
2327 __in const efx_nic_t *enp,
2328 __in unsigned int ndescs,
2329 __in uint32_t flags);
2331 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
2332 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
2333 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
2334 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
2336 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
2337 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
2338 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
2341 * Use the NO_CONT_EV RX event format, which allows the firmware to operate more
2342 * efficiently at high data rates. See SF-109306-TC 5.11 "Events for RXQs in
2345 * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set,
2346 * which is the case when an event queue is set to THROUGHPUT mode.
2348 #define EFX_EVQ_FLAGS_NO_CONT_EV (0x10)
2350 /* Configure EVQ for extended width events (EF100 only) */
2351 #define EFX_EVQ_FLAGS_EXTENDED_WIDTH (0x20)
2355 extern __checkReturn efx_rc_t
2357 __in efx_nic_t *enp,
2358 __in unsigned int index,
2359 __in efsys_mem_t *esmp,
2363 __in uint32_t flags,
2364 __deref_out efx_evq_t **eepp);
2367 extern __checkReturn efx_rc_t
2369 __in efx_nic_t *enp,
2370 __in unsigned int index,
2371 __in efsys_mem_t *esmp,
2375 __in uint32_t flags,
2377 __deref_out efx_evq_t **eepp);
2382 __in efx_evq_t *eep,
2383 __in uint16_t data);
2385 typedef __checkReturn boolean_t
2386 (*efx_initialized_ev_t)(
2387 __in_opt void *arg);
2389 #define EFX_PKT_UNICAST 0x0004
2390 #define EFX_PKT_START 0x0008
2392 #define EFX_PKT_VLAN_TAGGED 0x0010
2393 #define EFX_CKSUM_TCPUDP 0x0020
2394 #define EFX_CKSUM_IPV4 0x0040
2395 #define EFX_PKT_CONT 0x0080
2397 #define EFX_CHECK_VLAN 0x0100
2398 #define EFX_PKT_TCP 0x0200
2399 #define EFX_PKT_UDP 0x0400
2400 #define EFX_PKT_IPV4 0x0800
2402 #define EFX_PKT_IPV6 0x1000
2403 #define EFX_PKT_PREFIX_LEN 0x2000
2404 #define EFX_ADDR_MISMATCH 0x4000
2405 #define EFX_DISCARD 0x8000
2408 * The following flags are used only for packed stream
2409 * mode. The values for the flags are reused to fit into 16 bit,
2410 * since EFX_PKT_START and EFX_PKT_CONT are never used in
2411 * packed stream mode
2413 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
2414 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
2417 #define EFX_EV_RX_NLABELS 32
2418 #define EFX_EV_TX_NLABELS 32
2420 typedef __checkReturn boolean_t
2423 __in uint32_t label,
2426 __in uint16_t flags);
2428 typedef __checkReturn boolean_t
2429 (*efx_rx_packets_ev_t)(
2431 __in uint32_t label,
2432 __in unsigned int num_packets,
2433 __in uint32_t flags);
2435 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2438 * Packed stream mode is documented in SF-112241-TC.
2439 * The general idea is that, instead of putting each incoming
2440 * packet into a separate buffer which is specified in a RX
2441 * descriptor, a large buffer is provided to the hardware and
2442 * packets are put there in a continuous stream.
2443 * The main advantage of such an approach is that RX queue refilling
2444 * happens much less frequently.
2446 * Equal stride packed stream mode is documented in SF-119419-TC.
2447 * The general idea is to utilize advantages of the packed stream,
2448 * but avoid indirection in packets representation.
2449 * The main advantage of such an approach is that RX queue refilling
2450 * happens much less frequently and packets buffers are independent
2451 * from upper layers point of view.
2454 typedef __checkReturn boolean_t
2457 __in uint32_t label,
2459 __in uint32_t pkt_count,
2460 __in uint16_t flags);
2464 typedef __checkReturn boolean_t
2467 __in uint32_t label,
2470 typedef __checkReturn boolean_t
2471 (*efx_tx_ndescs_ev_t)(
2473 __in uint32_t label,
2474 __in unsigned int ndescs);
2476 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
2477 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
2478 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
2479 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
2480 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
2481 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
2482 #define EFX_EXCEPTION_RX_ERROR 0x00000007
2483 #define EFX_EXCEPTION_TX_ERROR 0x00000008
2484 #define EFX_EXCEPTION_EV_ERROR 0x00000009
2486 typedef __checkReturn boolean_t
2487 (*efx_exception_ev_t)(
2489 __in uint32_t label,
2490 __in uint32_t data);
2492 typedef __checkReturn boolean_t
2493 (*efx_rxq_flush_done_ev_t)(
2495 __in uint32_t rxq_index);
2497 typedef __checkReturn boolean_t
2498 (*efx_rxq_flush_failed_ev_t)(
2500 __in uint32_t rxq_index);
2502 typedef __checkReturn boolean_t
2503 (*efx_txq_flush_done_ev_t)(
2505 __in uint32_t txq_index);
2507 typedef __checkReturn boolean_t
2508 (*efx_software_ev_t)(
2510 __in uint16_t magic);
2512 typedef __checkReturn boolean_t
2515 __in uint32_t code);
2517 #define EFX_SRAM_CLEAR 0
2518 #define EFX_SRAM_UPDATE 1
2519 #define EFX_SRAM_ILLEGAL_CLEAR 2
2521 typedef __checkReturn boolean_t
2522 (*efx_wake_up_ev_t)(
2524 __in uint32_t label);
2526 typedef __checkReturn boolean_t
2529 __in uint32_t label);
2531 typedef __checkReturn boolean_t
2532 (*efx_link_change_ev_t)(
2534 __in efx_link_mode_t link_mode);
2536 #if EFSYS_OPT_MON_STATS
2538 typedef __checkReturn boolean_t
2539 (*efx_monitor_ev_t)(
2541 __in efx_mon_stat_t id,
2542 __in efx_mon_stat_value_t value);
2544 #endif /* EFSYS_OPT_MON_STATS */
2546 #if EFSYS_OPT_MAC_STATS
2548 typedef __checkReturn boolean_t
2549 (*efx_mac_stats_ev_t)(
2551 __in uint32_t generation);
2553 #endif /* EFSYS_OPT_MAC_STATS */
2555 #if EFSYS_OPT_DESC_PROXY
2558 * NOTE: This callback returns the raw descriptor data, which has not been
2559 * converted to host endian. The callback must use the EFX_OWORD macros
2560 * to extract the descriptor fields as host endian values.
2562 typedef __checkReturn boolean_t
2563 (*efx_desc_proxy_txq_desc_ev_t)(
2565 __in uint16_t vi_id,
2566 __in efx_oword_t txq_desc);
2569 * NOTE: This callback returns the raw descriptor data, which has not been
2570 * converted to host endian. The callback must use the EFX_OWORD macros
2571 * to extract the descriptor fields as host endian values.
2573 typedef __checkReturn boolean_t
2574 (*efx_desc_proxy_virtq_desc_ev_t)(
2576 __in uint16_t vi_id,
2577 __in uint16_t avail,
2578 __in efx_oword_t virtq_desc);
2580 #endif /* EFSYS_OPT_DESC_PROXY */
2582 typedef struct efx_ev_callbacks_s {
2583 efx_initialized_ev_t eec_initialized;
2585 efx_rx_packets_ev_t eec_rx_packets;
2586 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2587 efx_rx_ps_ev_t eec_rx_ps;
2590 efx_tx_ndescs_ev_t eec_tx_ndescs;
2591 efx_exception_ev_t eec_exception;
2592 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2593 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2594 efx_txq_flush_done_ev_t eec_txq_flush_done;
2595 efx_software_ev_t eec_software;
2596 efx_sram_ev_t eec_sram;
2597 efx_wake_up_ev_t eec_wake_up;
2598 efx_timer_ev_t eec_timer;
2599 efx_link_change_ev_t eec_link_change;
2600 #if EFSYS_OPT_MON_STATS
2601 efx_monitor_ev_t eec_monitor;
2602 #endif /* EFSYS_OPT_MON_STATS */
2603 #if EFSYS_OPT_MAC_STATS
2604 efx_mac_stats_ev_t eec_mac_stats;
2605 #endif /* EFSYS_OPT_MAC_STATS */
2606 #if EFSYS_OPT_DESC_PROXY
2607 efx_desc_proxy_txq_desc_ev_t eec_desc_proxy_txq_desc;
2608 efx_desc_proxy_virtq_desc_ev_t eec_desc_proxy_virtq_desc;
2609 #endif /* EFSYS_OPT_DESC_PROXY */
2611 } efx_ev_callbacks_t;
2614 extern __checkReturn boolean_t
2616 __in efx_evq_t *eep,
2617 __in unsigned int count);
2619 #if EFSYS_OPT_EV_PREFETCH
2624 __in efx_evq_t *eep,
2625 __in unsigned int count);
2627 #endif /* EFSYS_OPT_EV_PREFETCH */
2631 efx_ev_qcreate_check_init_done(
2632 __in efx_evq_t *eep,
2633 __in const efx_ev_callbacks_t *eecp,
2634 __in_opt void *arg);
2639 __in efx_evq_t *eep,
2640 __inout unsigned int *countp,
2641 __in const efx_ev_callbacks_t *eecp,
2642 __in_opt void *arg);
2645 extern __checkReturn efx_rc_t
2646 efx_ev_usecs_to_ticks(
2647 __in efx_nic_t *enp,
2648 __in unsigned int usecs,
2649 __out unsigned int *ticksp);
2652 extern __checkReturn efx_rc_t
2654 __in efx_evq_t *eep,
2655 __in unsigned int us);
2658 extern __checkReturn efx_rc_t
2660 __in efx_evq_t *eep,
2661 __in unsigned int count);
2663 #if EFSYS_OPT_QSTATS
2670 __in efx_nic_t *enp,
2671 __in unsigned int id);
2673 #endif /* EFSYS_OPT_NAMES */
2677 efx_ev_qstats_update(
2678 __in efx_evq_t *eep,
2679 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2681 #endif /* EFSYS_OPT_QSTATS */
2686 __in efx_evq_t *eep);
2691 extern __checkReturn efx_rc_t
2693 __inout efx_nic_t *enp);
2698 __in efx_nic_t *enp);
2700 #if EFSYS_OPT_RX_SCATTER
2702 extern __checkReturn efx_rc_t
2703 efx_rx_scatter_enable(
2704 __in efx_nic_t *enp,
2705 __in unsigned int buf_size);
2706 #endif /* EFSYS_OPT_RX_SCATTER */
2708 /* Handle to represent use of the default RSS context. */
2709 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2711 #if EFSYS_OPT_RX_SCALE
2713 typedef enum efx_rx_hash_alg_e {
2714 EFX_RX_HASHALG_LFSR = 0,
2715 EFX_RX_HASHALG_TOEPLITZ,
2716 EFX_RX_HASHALG_PACKED_STREAM,
2718 } efx_rx_hash_alg_t;
2721 * Legacy hash type flags.
2723 * They represent standard tuples for distinct traffic classes.
2725 #define EFX_RX_HASH_IPV4 (1U << 0)
2726 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2727 #define EFX_RX_HASH_IPV6 (1U << 2)
2728 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2730 #define EFX_RX_HASH_LEGACY_MASK \
2731 (EFX_RX_HASH_IPV4 | \
2732 EFX_RX_HASH_TCPIPV4 | \
2733 EFX_RX_HASH_IPV6 | \
2734 EFX_RX_HASH_TCPIPV6)
2737 * The type of the argument used by efx_rx_scale_mode_set() to
2738 * provide a means for the client drivers to configure hashing.
2740 * A properly constructed value can either be:
2741 * - a combination of legacy flags
2742 * - a combination of EFX_RX_HASH() flags
2744 typedef uint32_t efx_rx_hash_type_t;
2746 typedef enum efx_rx_hash_support_e {
2747 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2748 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2749 } efx_rx_hash_support_t;
2751 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2752 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2753 #define EFX_MAXRSS 64 /* RX indirection entry range */
2754 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2756 typedef enum efx_rx_scale_context_type_e {
2757 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2758 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2759 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2760 } efx_rx_scale_context_type_t;
2763 * Traffic classes eligible for hash computation.
2765 * Select packet headers used in computing the receive hash.
2766 * This uses the same encoding as the RSS_MODES field of
2767 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2769 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2770 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2771 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2772 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2773 #define EFX_RX_CLASS_IPV4_LBN 16
2774 #define EFX_RX_CLASS_IPV4_WIDTH 4
2775 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2776 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2777 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2778 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2779 #define EFX_RX_CLASS_IPV6_LBN 28
2780 #define EFX_RX_CLASS_IPV6_WIDTH 4
2782 #define EFX_RX_NCLASSES 6
2785 * Ancillary flags used to construct generic hash tuples.
2786 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2788 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2789 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2790 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2791 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2794 * Generic hash tuples.
2796 * They express combinations of packet fields
2797 * which can contribute to the hash value for
2798 * a particular traffic class.
2800 #define EFX_RX_CLASS_HASH_DISABLE 0
2802 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2803 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2805 #define EFX_RX_CLASS_HASH_2TUPLE \
2806 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2807 EFX_RX_CLASS_HASH_DST_ADDR)
2809 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2810 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2811 EFX_RX_CLASS_HASH_SRC_PORT)
2813 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2814 (EFX_RX_CLASS_HASH_DST_ADDR | \
2815 EFX_RX_CLASS_HASH_DST_PORT)
2817 #define EFX_RX_CLASS_HASH_4TUPLE \
2818 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2819 EFX_RX_CLASS_HASH_DST_ADDR | \
2820 EFX_RX_CLASS_HASH_SRC_PORT | \
2821 EFX_RX_CLASS_HASH_DST_PORT)
2823 #define EFX_RX_CLASS_HASH_NTUPLES 7
2826 * Hash flag constructor.
2828 * Resulting flags encode hash tuples for specific traffic classes.
2829 * The client drivers are encouraged to use these flags to form
2830 * a hash type value.
2832 #define EFX_RX_HASH(_class, _tuple) \
2833 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2834 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2837 * The maximum number of EFX_RX_HASH() flags.
2839 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2842 extern __checkReturn efx_rc_t
2843 efx_rx_scale_hash_flags_get(
2844 __in efx_nic_t *enp,
2845 __in efx_rx_hash_alg_t hash_alg,
2846 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
2847 __in unsigned int max_nflags,
2848 __out unsigned int *nflagsp);
2851 extern __checkReturn efx_rc_t
2852 efx_rx_hash_default_support_get(
2853 __in efx_nic_t *enp,
2854 __out efx_rx_hash_support_t *supportp);
2858 extern __checkReturn efx_rc_t
2859 efx_rx_scale_default_support_get(
2860 __in efx_nic_t *enp,
2861 __out efx_rx_scale_context_type_t *typep);
2864 extern __checkReturn efx_rc_t
2865 efx_rx_scale_context_alloc(
2866 __in efx_nic_t *enp,
2867 __in efx_rx_scale_context_type_t type,
2868 __in uint32_t num_queues,
2869 __out uint32_t *rss_contextp);
2872 extern __checkReturn efx_rc_t
2873 efx_rx_scale_context_free(
2874 __in efx_nic_t *enp,
2875 __in uint32_t rss_context);
2878 extern __checkReturn efx_rc_t
2879 efx_rx_scale_mode_set(
2880 __in efx_nic_t *enp,
2881 __in uint32_t rss_context,
2882 __in efx_rx_hash_alg_t alg,
2883 __in efx_rx_hash_type_t type,
2884 __in boolean_t insert);
2887 extern __checkReturn efx_rc_t
2888 efx_rx_scale_tbl_set(
2889 __in efx_nic_t *enp,
2890 __in uint32_t rss_context,
2891 __in_ecount(n) unsigned int *table,
2895 extern __checkReturn efx_rc_t
2896 efx_rx_scale_key_set(
2897 __in efx_nic_t *enp,
2898 __in uint32_t rss_context,
2899 __in_ecount(n) uint8_t *key,
2903 extern __checkReturn uint32_t
2904 efx_pseudo_hdr_hash_get(
2905 __in efx_rxq_t *erp,
2906 __in efx_rx_hash_alg_t func,
2907 __in uint8_t *buffer);
2909 #endif /* EFSYS_OPT_RX_SCALE */
2912 extern __checkReturn efx_rc_t
2913 efx_pseudo_hdr_pkt_length_get(
2914 __in efx_rxq_t *erp,
2915 __in uint8_t *buffer,
2916 __out uint16_t *pkt_lengthp);
2919 extern __checkReturn size_t
2921 __in const efx_nic_t *enp,
2922 __in unsigned int ndescs);
2925 extern __checkReturn unsigned int
2927 __in const efx_nic_t *enp,
2928 __in unsigned int ndescs);
2930 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2933 * libefx representation of the Rx prefix layout information.
2935 * The information may be used inside libefx to implement Rx prefix fields
2936 * accessors and by drivers which process Rx prefix itself.
2940 * All known Rx prefix fields.
2942 * An Rx prefix may have a subset of these fields.
2944 typedef enum efx_rx_prefix_field_e {
2945 EFX_RX_PREFIX_FIELD_LENGTH = 0,
2946 EFX_RX_PREFIX_FIELD_ORIG_LENGTH,
2947 EFX_RX_PREFIX_FIELD_CLASS,
2948 EFX_RX_PREFIX_FIELD_RSS_HASH,
2949 EFX_RX_PREFIX_FIELD_RSS_HASH_VALID,
2950 EFX_RX_PREFIX_FIELD_PARTIAL_TSTAMP,
2951 EFX_RX_PREFIX_FIELD_VLAN_STRIP_TCI,
2952 EFX_RX_PREFIX_FIELD_INNER_VLAN_STRIP_TCI,
2953 EFX_RX_PREFIX_FIELD_USER_FLAG,
2954 EFX_RX_PREFIX_FIELD_USER_MARK,
2955 EFX_RX_PREFIX_FIELD_USER_MARK_VALID,
2956 EFX_RX_PREFIX_FIELD_CSUM_FRAME,
2957 EFX_RX_PREFIX_FIELD_INGRESS_VPORT,
2958 EFX_RX_PREFIX_FIELD_INGRESS_MPORT = EFX_RX_PREFIX_FIELD_INGRESS_VPORT,
2959 EFX_RX_PREFIX_NFIELDS
2960 } efx_rx_prefix_field_t;
2963 * Location and endianness of a field in Rx prefix.
2965 * If width is zero, the field is not present.
2967 typedef struct efx_rx_prefix_field_info_s {
2968 uint16_t erpfi_offset_bits;
2969 uint8_t erpfi_width_bits;
2970 boolean_t erpfi_big_endian;
2971 } efx_rx_prefix_field_info_t;
2973 /* Helper macro to define Rx prefix fields */
2974 #define EFX_RX_PREFIX_FIELD(_efx, _field, _big_endian) \
2975 [EFX_RX_PREFIX_FIELD_ ## _efx] = { \
2976 .erpfi_offset_bits = EFX_LOW_BIT(_field), \
2977 .erpfi_width_bits = EFX_WIDTH(_field), \
2978 .erpfi_big_endian = (_big_endian), \
2981 typedef struct efx_rx_prefix_layout_s {
2983 uint8_t erpl_length;
2984 efx_rx_prefix_field_info_t erpl_fields[EFX_RX_PREFIX_NFIELDS];
2985 } efx_rx_prefix_layout_t;
2988 * Helper function to find out a bit mask of wanted but not available
2991 * A field is considered as not available if any parameter mismatch.
2994 extern __checkReturn uint32_t
2995 efx_rx_prefix_layout_check(
2996 __in const efx_rx_prefix_layout_t *available,
2997 __in const efx_rx_prefix_layout_t *wanted);
3000 extern __checkReturn efx_rc_t
3001 efx_rx_prefix_get_layout(
3002 __in const efx_rxq_t *erp,
3003 __out efx_rx_prefix_layout_t *erplp);
3005 typedef enum efx_rxq_type_e {
3006 EFX_RXQ_TYPE_DEFAULT,
3007 EFX_RXQ_TYPE_PACKED_STREAM,
3008 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
3013 * Dummy flag to be used instead of 0 to make it clear that the argument
3014 * is receive queue flags.
3016 #define EFX_RXQ_FLAG_NONE 0x0
3017 #define EFX_RXQ_FLAG_SCATTER 0x1
3019 * If tunnels are supported and Rx event can provide information about
3020 * either outer or inner packet classes (e.g. SFN8xxx adapters with
3021 * full-feature firmware variant running), outer classes are requested by
3022 * default. However, if the driver supports tunnels, the flag allows to
3023 * request inner classes which are required to be able to interpret inner
3024 * Rx checksum offload results.
3026 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
3028 * Request delivery of the RSS hash calculated by HW to be used by
3031 #define EFX_RXQ_FLAG_RSS_HASH 0x4
3033 * Request ingress mport field in the Rx prefix of a queue.
3035 #define EFX_RXQ_FLAG_INGRESS_MPORT 0x8
3037 * Request user mark field in the Rx prefix of a queue.
3039 #define EFX_RXQ_FLAG_USER_MARK 0x10
3041 * Request user flag field in the Rx prefix of a queue.
3043 #define EFX_RXQ_FLAG_USER_FLAG 0x20
3046 extern __checkReturn efx_rc_t
3048 __in efx_nic_t *enp,
3049 __in unsigned int index,
3050 __in unsigned int label,
3051 __in efx_rxq_type_t type,
3052 __in size_t buf_size,
3053 __in efsys_mem_t *esmp,
3056 __in unsigned int flags,
3057 __in efx_evq_t *eep,
3058 __deref_out efx_rxq_t **erpp);
3060 #if EFSYS_OPT_RX_PACKED_STREAM
3062 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
3063 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
3064 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
3065 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
3066 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
3069 extern __checkReturn efx_rc_t
3070 efx_rx_qcreate_packed_stream(
3071 __in efx_nic_t *enp,
3072 __in unsigned int index,
3073 __in unsigned int label,
3074 __in uint32_t ps_buf_size,
3075 __in efsys_mem_t *esmp,
3077 __in efx_evq_t *eep,
3078 __deref_out efx_rxq_t **erpp);
3082 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
3084 /* Maximum head-of-line block timeout in nanoseconds */
3085 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
3088 extern __checkReturn efx_rc_t
3089 efx_rx_qcreate_es_super_buffer(
3090 __in efx_nic_t *enp,
3091 __in unsigned int index,
3092 __in unsigned int label,
3093 __in uint32_t n_bufs_per_desc,
3094 __in uint32_t max_dma_len,
3095 __in uint32_t buf_stride,
3096 __in uint32_t hol_block_timeout,
3097 __in efsys_mem_t *esmp,
3099 __in unsigned int flags,
3100 __in efx_evq_t *eep,
3101 __deref_out efx_rxq_t **erpp);
3105 typedef struct efx_buffer_s {
3106 efsys_dma_addr_t eb_addr;
3111 typedef struct efx_desc_s {
3118 __in efx_rxq_t *erp,
3119 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
3121 __in unsigned int ndescs,
3122 __in unsigned int completed,
3123 __in unsigned int added);
3128 __in efx_rxq_t *erp,
3129 __in unsigned int added,
3130 __inout unsigned int *pushedp);
3132 #if EFSYS_OPT_RX_PACKED_STREAM
3136 efx_rx_qpush_ps_credits(
3137 __in efx_rxq_t *erp);
3140 extern __checkReturn uint8_t *
3141 efx_rx_qps_packet_info(
3142 __in efx_rxq_t *erp,
3143 __in uint8_t *buffer,
3144 __in uint32_t buffer_length,
3145 __in uint32_t current_offset,
3146 __out uint16_t *lengthp,
3147 __out uint32_t *next_offsetp,
3148 __out uint32_t *timestamp);
3152 extern __checkReturn efx_rc_t
3154 __in efx_rxq_t *erp);
3159 __in efx_rxq_t *erp);
3164 __in efx_rxq_t *erp);
3168 typedef struct efx_txq_s efx_txq_t;
3170 #if EFSYS_OPT_QSTATS
3172 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
3173 typedef enum efx_tx_qstat_e {
3179 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
3181 #endif /* EFSYS_OPT_QSTATS */
3184 extern __checkReturn efx_rc_t
3186 __in efx_nic_t *enp);
3191 __in efx_nic_t *enp);
3194 extern __checkReturn size_t
3196 __in const efx_nic_t *enp,
3197 __in unsigned int ndescs);
3200 extern __checkReturn unsigned int
3202 __in const efx_nic_t *enp,
3203 __in unsigned int ndescs);
3205 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
3207 #define EFX_TXQ_CKSUM_IPV4 0x0001
3208 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
3209 #define EFX_TXQ_FATSOV2 0x0004
3210 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
3211 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
3214 extern __checkReturn efx_rc_t
3216 __in efx_nic_t *enp,
3217 __in unsigned int index,
3218 __in unsigned int label,
3219 __in efsys_mem_t *esmp,
3222 __in uint16_t flags,
3223 __in efx_evq_t *eep,
3224 __deref_out efx_txq_t **etpp,
3225 __out unsigned int *addedp);
3228 extern __checkReturn efx_rc_t
3230 __in efx_txq_t *etp,
3231 __in_ecount(ndescs) efx_buffer_t *eb,
3232 __in unsigned int ndescs,
3233 __in unsigned int completed,
3234 __inout unsigned int *addedp);
3237 extern __checkReturn efx_rc_t
3239 __in efx_txq_t *etp,
3240 __in unsigned int ns);
3245 __in efx_txq_t *etp,
3246 __in unsigned int added,
3247 __in unsigned int pushed);
3250 extern __checkReturn efx_rc_t
3252 __in efx_txq_t *etp);
3257 __in efx_txq_t *etp);
3260 extern __checkReturn efx_rc_t
3262 __in efx_txq_t *etp);
3266 efx_tx_qpio_disable(
3267 __in efx_txq_t *etp);
3270 extern __checkReturn efx_rc_t
3272 __in efx_txq_t *etp,
3273 __in_ecount(buf_length) uint8_t *buffer,
3274 __in size_t buf_length,
3275 __in size_t pio_buf_offset);
3278 extern __checkReturn efx_rc_t
3280 __in efx_txq_t *etp,
3281 __in size_t pkt_length,
3282 __in unsigned int completed,
3283 __inout unsigned int *addedp);
3286 extern __checkReturn efx_rc_t
3288 __in efx_txq_t *etp,
3289 __in_ecount(n) efx_desc_t *ed,
3290 __in unsigned int n,
3291 __in unsigned int completed,
3292 __inout unsigned int *addedp);
3296 efx_tx_qdesc_dma_create(
3297 __in efx_txq_t *etp,
3298 __in efsys_dma_addr_t addr,
3301 __out efx_desc_t *edp);
3305 efx_tx_qdesc_tso_create(
3306 __in efx_txq_t *etp,
3307 __in uint16_t ipv4_id,
3308 __in uint32_t tcp_seq,
3309 __in uint8_t tcp_flags,
3310 __out efx_desc_t *edp);
3312 /* Number of FATSOv2 option descriptors */
3313 #define EFX_TX_FATSOV2_OPT_NDESCS 2
3315 /* Maximum number of DMA segments per TSO packet (not superframe) */
3316 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
3320 efx_tx_qdesc_tso2_create(
3321 __in efx_txq_t *etp,
3322 __in uint16_t ipv4_id,
3323 __in uint16_t outer_ipv4_id,
3324 __in uint32_t tcp_seq,
3325 __in uint16_t tcp_mss,
3326 __out_ecount(count) efx_desc_t *edp,
3331 efx_tx_qdesc_vlantci_create(
3332 __in efx_txq_t *etp,
3334 __out efx_desc_t *edp);
3338 efx_tx_qdesc_checksum_create(
3339 __in efx_txq_t *etp,
3340 __in uint16_t flags,
3341 __out efx_desc_t *edp);
3343 #if EFSYS_OPT_QSTATS
3350 __in efx_nic_t *etp,
3351 __in unsigned int id);
3353 #endif /* EFSYS_OPT_NAMES */
3357 efx_tx_qstats_update(
3358 __in efx_txq_t *etp,
3359 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
3361 #endif /* EFSYS_OPT_QSTATS */
3366 __in efx_txq_t *etp);
3371 #if EFSYS_OPT_FILTER
3373 #define EFX_ETHER_TYPE_IPV4 0x0800
3374 #define EFX_ETHER_TYPE_IPV6 0x86DD
3376 #define EFX_IPPROTO_TCP 6
3377 #define EFX_IPPROTO_UDP 17
3378 #define EFX_IPPROTO_GRE 47
3380 /* Use RSS to spread across multiple queues */
3381 #define EFX_FILTER_FLAG_RX_RSS 0x01
3382 /* Enable RX scatter */
3383 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
3385 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
3386 * May only be set by the filter implementation for each type.
3387 * A removal request will restore the automatic filter in its place.
3389 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
3390 /* Filter is for RX */
3391 #define EFX_FILTER_FLAG_RX 0x08
3392 /* Filter is for TX */
3393 #define EFX_FILTER_FLAG_TX 0x10
3394 /* Set match flag on the received packet */
3395 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
3396 /* Set match mark on the received packet */
3397 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
3399 typedef uint8_t efx_filter_flags_t;
3402 * Flags which specify the fields to match on. The values are the same as in the
3403 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
3406 /* Match by remote IP host address */
3407 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
3408 /* Match by local IP host address */
3409 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
3410 /* Match by remote MAC address */
3411 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
3412 /* Match by remote TCP/UDP port */
3413 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
3414 /* Match by remote TCP/UDP port */
3415 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
3416 /* Match by local TCP/UDP port */
3417 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
3418 /* Match by Ether-type */
3419 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
3420 /* Match by inner VLAN ID */
3421 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
3422 /* Match by outer VLAN ID */
3423 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
3424 /* Match by IP transport protocol */
3425 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
3426 /* Match by ingress MPORT */
3427 #define EFX_FILTER_MATCH_MPORT 0x00000400
3428 /* Match by VNI or VSID */
3429 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
3430 /* For encapsulated packets, match by inner frame local MAC address */
3431 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
3432 /* For encapsulated packets, match all multicast inner frames */
3433 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
3434 /* For encapsulated packets, match all unicast inner frames */
3435 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
3437 * Match by encap type, this flag does not correspond to
3438 * the MCDI match flags and any unoccupied value may be used
3440 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
3441 /* Match otherwise-unmatched multicast and broadcast packets */
3442 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
3443 /* Match otherwise-unmatched unicast packets */
3444 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
3446 typedef uint32_t efx_filter_match_flags_t;
3448 /* Filter priority from lowest to highest */
3449 typedef enum efx_filter_priority_s {
3450 EFX_FILTER_PRI_AUTO = 0, /* Automatic filter based on device
3451 * address list or hardware
3452 * requirements. This may only be used
3453 * by the filter implementation for
3455 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
3457 } efx_filter_priority_t;
3460 * FIXME: All these fields are assumed to be in little-endian byte order.
3461 * It may be better for some to be big-endian. See bug42804.
3464 typedef struct efx_filter_spec_s {
3465 efx_filter_match_flags_t efs_match_flags;
3466 uint8_t efs_priority;
3467 efx_filter_flags_t efs_flags;
3468 uint16_t efs_dmaq_id;
3469 uint32_t efs_rss_context;
3472 * Saved lower-priority filter. If it is set, it is restored on
3473 * filter delete operation.
3475 struct efx_filter_spec_s *efs_overridden_spec;
3476 /* Fields below here are hashed for software filter lookup */
3477 uint16_t efs_outer_vid;
3478 uint16_t efs_inner_vid;
3479 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
3480 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
3481 uint16_t efs_ether_type;
3482 uint8_t efs_ip_proto;
3483 efx_tunnel_protocol_t efs_encap_type;
3484 uint16_t efs_loc_port;
3485 uint16_t efs_rem_port;
3486 efx_oword_t efs_rem_host;
3487 efx_oword_t efs_loc_host;
3488 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
3489 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
3490 uint32_t efs_ingress_mport;
3491 } efx_filter_spec_t;
3494 /* Default values for use in filter specifications */
3495 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
3496 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
3499 extern __checkReturn efx_rc_t
3501 __in efx_nic_t *enp);
3506 __in efx_nic_t *enp);
3509 extern __checkReturn efx_rc_t
3511 __in efx_nic_t *enp,
3512 __inout efx_filter_spec_t *spec);
3515 extern __checkReturn efx_rc_t
3517 __in efx_nic_t *enp,
3518 __inout efx_filter_spec_t *spec);
3521 extern __checkReturn efx_rc_t
3523 __in efx_nic_t *enp);
3526 extern __checkReturn efx_rc_t
3527 efx_filter_supported_filters(
3528 __in efx_nic_t *enp,
3529 __out_ecount(buffer_length) uint32_t *buffer,
3530 __in size_t buffer_length,
3531 __out size_t *list_lengthp);
3535 efx_filter_spec_init_rx(
3536 __out efx_filter_spec_t *spec,
3537 __in efx_filter_priority_t priority,
3538 __in efx_filter_flags_t flags,
3539 __in efx_rxq_t *erp);
3543 efx_filter_spec_init_tx(
3544 __out efx_filter_spec_t *spec,
3545 __in efx_txq_t *etp);
3548 extern __checkReturn efx_rc_t
3549 efx_filter_spec_set_ipv4_local(
3550 __inout efx_filter_spec_t *spec,
3553 __in uint16_t port);
3556 extern __checkReturn efx_rc_t
3557 efx_filter_spec_set_ipv4_full(
3558 __inout efx_filter_spec_t *spec,
3560 __in uint32_t lhost,
3561 __in uint16_t lport,
3562 __in uint32_t rhost,
3563 __in uint16_t rport);
3566 extern __checkReturn efx_rc_t
3567 efx_filter_spec_set_eth_local(
3568 __inout efx_filter_spec_t *spec,
3570 __in const uint8_t *addr);
3574 efx_filter_spec_set_ether_type(
3575 __inout efx_filter_spec_t *spec,
3576 __in uint16_t ether_type);
3579 extern __checkReturn efx_rc_t
3580 efx_filter_spec_set_uc_def(
3581 __inout efx_filter_spec_t *spec);
3584 extern __checkReturn efx_rc_t
3585 efx_filter_spec_set_mc_def(
3586 __inout efx_filter_spec_t *spec);
3588 typedef enum efx_filter_inner_frame_match_e {
3589 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
3590 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
3591 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
3592 } efx_filter_inner_frame_match_t;
3595 extern __checkReturn efx_rc_t
3596 efx_filter_spec_set_encap_type(
3597 __inout efx_filter_spec_t *spec,
3598 __in efx_tunnel_protocol_t encap_type,
3599 __in efx_filter_inner_frame_match_t inner_frame_match);
3602 extern __checkReturn efx_rc_t
3603 efx_filter_spec_set_vxlan(
3604 __inout efx_filter_spec_t *spec,
3605 __in const uint8_t *vni,
3606 __in const uint8_t *inner_addr,
3607 __in const uint8_t *outer_addr);
3610 extern __checkReturn efx_rc_t
3611 efx_filter_spec_set_geneve(
3612 __inout efx_filter_spec_t *spec,
3613 __in const uint8_t *vni,
3614 __in const uint8_t *inner_addr,
3615 __in const uint8_t *outer_addr);
3618 extern __checkReturn efx_rc_t
3619 efx_filter_spec_set_nvgre(
3620 __inout efx_filter_spec_t *spec,
3621 __in const uint8_t *vsid,
3622 __in const uint8_t *inner_addr,
3623 __in const uint8_t *outer_addr);
3625 #if EFSYS_OPT_RX_SCALE
3627 extern __checkReturn efx_rc_t
3628 efx_filter_spec_set_rss_context(
3629 __inout efx_filter_spec_t *spec,
3630 __in uint32_t rss_context);
3632 #endif /* EFSYS_OPT_FILTER */
3637 extern __checkReturn uint32_t
3639 __in_ecount(count) uint32_t const *input,
3641 __in uint32_t init);
3644 extern __checkReturn uint32_t
3646 __in_ecount(length) uint8_t const *input,
3648 __in uint32_t init);
3650 #if EFSYS_OPT_LICENSING
3654 typedef struct efx_key_stats_s {
3656 uint32_t eks_invalid;
3657 uint32_t eks_blacklisted;
3658 uint32_t eks_unverifiable;
3659 uint32_t eks_wrong_node;
3660 uint32_t eks_licensed_apps_lo;
3661 uint32_t eks_licensed_apps_hi;
3662 uint32_t eks_licensed_features_lo;
3663 uint32_t eks_licensed_features_hi;
3667 extern __checkReturn efx_rc_t
3669 __in efx_nic_t *enp);
3674 __in efx_nic_t *enp);
3677 extern __checkReturn boolean_t
3678 efx_lic_check_support(
3679 __in efx_nic_t *enp);
3682 extern __checkReturn efx_rc_t
3683 efx_lic_update_licenses(
3684 __in efx_nic_t *enp);
3687 extern __checkReturn efx_rc_t
3688 efx_lic_get_key_stats(
3689 __in efx_nic_t *enp,
3690 __out efx_key_stats_t *ksp);
3693 extern __checkReturn efx_rc_t
3695 __in efx_nic_t *enp,
3696 __in uint64_t app_id,
3697 __out boolean_t *licensedp);
3700 extern __checkReturn efx_rc_t
3702 __in efx_nic_t *enp,
3703 __in size_t buffer_size,
3704 __out uint32_t *typep,
3705 __out size_t *lengthp,
3706 __out_opt uint8_t *bufferp);
3710 extern __checkReturn efx_rc_t
3712 __in efx_nic_t *enp,
3713 __in_bcount(buffer_size)
3715 __in size_t buffer_size,
3716 __out uint32_t *startp);
3719 extern __checkReturn efx_rc_t
3721 __in efx_nic_t *enp,
3722 __in_bcount(buffer_size)
3724 __in size_t buffer_size,
3725 __in uint32_t offset,
3726 __out uint32_t *endp);
3729 extern __checkReturn __success(return != B_FALSE) boolean_t
3731 __in efx_nic_t *enp,
3732 __in_bcount(buffer_size)
3734 __in size_t buffer_size,
3735 __in uint32_t offset,
3736 __out uint32_t *startp,
3737 __out uint32_t *lengthp);
3740 extern __checkReturn __success(return != B_FALSE) boolean_t
3741 efx_lic_validate_key(
3742 __in efx_nic_t *enp,
3743 __in_bcount(length) caddr_t keyp,
3744 __in uint32_t length);
3747 extern __checkReturn efx_rc_t
3749 __in efx_nic_t *enp,
3750 __in_bcount(buffer_size)
3752 __in size_t buffer_size,
3753 __in uint32_t offset,
3754 __in uint32_t length,
3755 __out_bcount_part(key_max_size, *lengthp)
3757 __in size_t key_max_size,
3758 __out uint32_t *lengthp);
3761 extern __checkReturn efx_rc_t
3763 __in efx_nic_t *enp,
3764 __in_bcount(buffer_size)
3766 __in size_t buffer_size,
3767 __in uint32_t offset,
3768 __in_bcount(length) caddr_t keyp,
3769 __in uint32_t length,
3770 __out uint32_t *lengthp);
3773 extern __checkReturn efx_rc_t
3775 __in efx_nic_t *enp,
3776 __in_bcount(buffer_size)
3778 __in size_t buffer_size,
3779 __in uint32_t offset,
3780 __in uint32_t length,
3782 __out uint32_t *deltap);
3785 extern __checkReturn efx_rc_t
3786 efx_lic_create_partition(
3787 __in efx_nic_t *enp,
3788 __in_bcount(buffer_size)
3790 __in size_t buffer_size);
3792 extern __checkReturn efx_rc_t
3793 efx_lic_finish_partition(
3794 __in efx_nic_t *enp,
3795 __in_bcount(buffer_size)
3797 __in size_t buffer_size);
3799 #endif /* EFSYS_OPT_LICENSING */
3803 #if EFSYS_OPT_TUNNEL
3806 extern __checkReturn efx_rc_t
3808 __in efx_nic_t *enp);
3813 __in efx_nic_t *enp);
3816 * For overlay network encapsulation using UDP, the firmware needs to know
3817 * the configured UDP port for the overlay so it can decode encapsulated
3819 * The UDP port/protocol list is global.
3823 extern __checkReturn efx_rc_t
3824 efx_tunnel_config_udp_add(
3825 __in efx_nic_t *enp,
3826 __in uint16_t port /* host/cpu-endian */,
3827 __in efx_tunnel_protocol_t protocol);
3830 * Returns EBUSY if reconfiguration of the port is in progress in other thread.
3833 extern __checkReturn efx_rc_t
3834 efx_tunnel_config_udp_remove(
3835 __in efx_nic_t *enp,
3836 __in uint16_t port /* host/cpu-endian */,
3837 __in efx_tunnel_protocol_t protocol);
3840 * Returns EBUSY if reconfiguration of any of the tunnel entries
3841 * is in progress in other thread.
3844 extern __checkReturn efx_rc_t
3845 efx_tunnel_config_clear(
3846 __in efx_nic_t *enp);
3849 * Apply tunnel UDP ports configuration to hardware.
3851 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3855 extern __checkReturn efx_rc_t
3856 efx_tunnel_reconfigure(
3857 __in efx_nic_t *enp);
3859 #endif /* EFSYS_OPT_TUNNEL */
3861 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3864 * Firmware subvariant choice options.
3866 * It may be switched to no Tx checksum if attached drivers are either
3867 * preboot or firmware subvariant aware and no VIS are allocated.
3868 * If may be always switched to default explicitly using set request or
3869 * implicitly if unaware driver is attaching. If switching is done when
3870 * a driver is attached, it gets MC_REBOOT event and should recreate its
3873 * See SF-119419-TC DPDK Firmware Driver Interface and
3874 * SF-109306-TC EF10 for Driver Writers for details.
3876 typedef enum efx_nic_fw_subvariant_e {
3877 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3878 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3879 EFX_NIC_FW_SUBVARIANT_NTYPES
3880 } efx_nic_fw_subvariant_t;
3883 extern __checkReturn efx_rc_t
3884 efx_nic_get_fw_subvariant(
3885 __in efx_nic_t *enp,
3886 __out efx_nic_fw_subvariant_t *subvariantp);
3889 extern __checkReturn efx_rc_t
3890 efx_nic_set_fw_subvariant(
3891 __in efx_nic_t *enp,
3892 __in efx_nic_fw_subvariant_t subvariant);
3894 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3896 typedef enum efx_phy_fec_type_e {
3897 EFX_PHY_FEC_NONE = 0,
3900 } efx_phy_fec_type_t;
3903 extern __checkReturn efx_rc_t
3904 efx_phy_fec_type_get(
3905 __in efx_nic_t *enp,
3906 __out efx_phy_fec_type_t *typep);
3908 typedef struct efx_phy_link_state_s {
3909 uint32_t epls_adv_cap_mask;
3910 uint32_t epls_lp_cap_mask;
3911 uint32_t epls_ld_cap_mask;
3912 unsigned int epls_fcntl;
3913 efx_phy_fec_type_t epls_fec;
3914 efx_link_mode_t epls_link_mode;
3915 } efx_phy_link_state_t;
3918 extern __checkReturn efx_rc_t
3919 efx_phy_link_state_get(
3920 __in efx_nic_t *enp,
3921 __out efx_phy_link_state_t *eplsp);
3926 typedef uint32_t efx_vswitch_id_t;
3927 typedef uint32_t efx_vport_id_t;
3929 typedef enum efx_vswitch_type_e {
3930 EFX_VSWITCH_TYPE_VLAN = 1,
3931 EFX_VSWITCH_TYPE_VEB,
3932 /* VSWITCH_TYPE_VEPA: obsolete */
3933 EFX_VSWITCH_TYPE_MUX = 4,
3934 } efx_vswitch_type_t;
3936 typedef enum efx_vport_type_e {
3937 EFX_VPORT_TYPE_NORMAL = 4,
3938 EFX_VPORT_TYPE_EXPANSION,
3939 EFX_VPORT_TYPE_TEST,
3942 /* Unspecified VLAN ID to support disabling of VLAN filtering */
3943 #define EFX_FILTER_VID_UNSPEC 0xffff
3944 #define EFX_DEFAULT_VSWITCH_ID 1
3946 /* Default VF VLAN ID on creation */
3947 #define EFX_VF_VID_DEFAULT EFX_FILTER_VID_UNSPEC
3948 #define EFX_VPORT_ID_INVALID 0
3950 typedef struct efx_vport_config_s {
3951 /* Either VF index or EFX_PCI_VF_INVALID for PF */
3952 uint16_t evc_function;
3953 /* VLAN ID of the associated function */
3955 /* vport id shared with client driver */
3956 efx_vport_id_t evc_vport_id;
3957 /* MAC address of the associated function */
3958 uint8_t evc_mac_addr[EFX_MAC_ADDR_LEN];
3960 * vports created with this flag set may only transfer traffic on the
3961 * VLANs permitted by the vport. Also, an attempt to install filter with
3962 * VLAN will be refused unless requesting function has VLAN privilege.
3964 boolean_t evc_vlan_restrict;
3965 /* Whether this function is assigned or not */
3966 boolean_t evc_vport_assigned;
3967 } efx_vport_config_t;
3969 typedef struct efx_vswitch_s efx_vswitch_t;
3972 extern __checkReturn efx_rc_t
3974 __in efx_nic_t *enp);
3979 __in efx_nic_t *enp);
3982 extern __checkReturn efx_rc_t
3983 efx_evb_vswitch_create(
3984 __in efx_nic_t *enp,
3985 __in uint32_t num_vports,
3986 __inout_ecount(num_vports) efx_vport_config_t *vport_configp,
3987 __deref_out efx_vswitch_t **evpp);
3990 extern __checkReturn efx_rc_t
3991 efx_evb_vswitch_destroy(
3992 __in efx_nic_t *enp,
3993 __in efx_vswitch_t *evp);
3996 extern __checkReturn efx_rc_t
3997 efx_evb_vport_mac_set(
3998 __in efx_nic_t *enp,
3999 __in efx_vswitch_t *evp,
4000 __in efx_vport_id_t vport_id,
4001 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp);
4004 extern __checkReturn efx_rc_t
4005 efx_evb_vport_vlan_set(
4006 __in efx_nic_t *enp,
4007 __in efx_vswitch_t *evp,
4008 __in efx_vport_id_t vport_id,
4012 extern __checkReturn efx_rc_t
4013 efx_evb_vport_reset(
4014 __in efx_nic_t *enp,
4015 __in efx_vswitch_t *evp,
4016 __in efx_vport_id_t vport_id,
4017 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp,
4019 __out boolean_t *is_fn_resetp);
4022 extern __checkReturn efx_rc_t
4023 efx_evb_vport_stats(
4024 __in efx_nic_t *enp,
4025 __in efx_vswitch_t *evp,
4026 __in efx_vport_id_t vport_id,
4027 __out efsys_mem_t *stats_bufferp);
4029 #endif /* EFSYS_OPT_EVB */
4031 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
4033 typedef struct efx_proxy_auth_config_s {
4034 efsys_mem_t *request_bufferp;
4035 efsys_mem_t *response_bufferp;
4036 efsys_mem_t *status_bufferp;
4040 uint32_t handled_privileges;
4041 } efx_proxy_auth_config_t;
4043 typedef struct efx_proxy_cmd_params_s {
4046 uint8_t *request_bufferp;
4047 size_t request_size;
4048 uint8_t *response_bufferp;
4049 size_t response_size;
4050 size_t *response_size_actualp;
4051 } efx_proxy_cmd_params_t;
4054 extern __checkReturn efx_rc_t
4055 efx_proxy_auth_init(
4056 __in efx_nic_t *enp);
4060 efx_proxy_auth_fini(
4061 __in efx_nic_t *enp);
4064 extern __checkReturn efx_rc_t
4065 efx_proxy_auth_configure(
4066 __in efx_nic_t *enp,
4067 __in efx_proxy_auth_config_t *configp);
4070 extern __checkReturn efx_rc_t
4071 efx_proxy_auth_destroy(
4072 __in efx_nic_t *enp,
4073 __in uint32_t handled_privileges);
4076 extern __checkReturn efx_rc_t
4077 efx_proxy_auth_complete_request(
4078 __in efx_nic_t *enp,
4079 __in uint32_t fn_index,
4080 __in uint32_t proxy_result,
4081 __in uint32_t handle);
4084 extern __checkReturn efx_rc_t
4085 efx_proxy_auth_exec_cmd(
4086 __in efx_nic_t *enp,
4087 __inout efx_proxy_cmd_params_t *paramsp);
4090 extern __checkReturn efx_rc_t
4091 efx_proxy_auth_set_privilege_mask(
4092 __in efx_nic_t *enp,
4093 __in uint32_t vf_index,
4095 __in uint32_t value);
4098 extern __checkReturn efx_rc_t
4099 efx_proxy_auth_privilege_mask_get(
4100 __in efx_nic_t *enp,
4101 __in uint32_t pf_index,
4102 __in uint32_t vf_index,
4103 __out uint32_t *maskp);
4106 extern __checkReturn efx_rc_t
4107 efx_proxy_auth_privilege_modify(
4108 __in efx_nic_t *enp,
4109 __in uint32_t pf_index,
4110 __in uint32_t vf_index,
4111 __in uint32_t add_privileges_mask,
4112 __in uint32_t remove_privileges_mask);
4114 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
4119 extern __checkReturn efx_rc_t
4121 __in efx_nic_t *enp);
4126 __in efx_nic_t *enp);
4128 typedef struct efx_mae_limits_s {
4129 uint32_t eml_max_n_action_prios;
4130 uint32_t eml_max_n_outer_prios;
4131 uint32_t eml_encap_types_supported;
4132 uint32_t eml_encap_header_size_limit;
4133 uint32_t eml_max_n_counters;
4137 extern __checkReturn efx_rc_t
4139 __in efx_nic_t *enp,
4140 __out efx_mae_limits_t *emlp);
4142 typedef enum efx_mae_rule_type_e {
4143 EFX_MAE_RULE_ACTION = 0,
4147 } efx_mae_rule_type_t;
4149 typedef struct efx_mae_match_spec_s efx_mae_match_spec_t;
4152 extern __checkReturn efx_rc_t
4153 efx_mae_match_spec_init(
4154 __in efx_nic_t *enp,
4155 __in efx_mae_rule_type_t type,
4157 __out efx_mae_match_spec_t **specp);
4161 efx_mae_match_spec_fini(
4162 __in efx_nic_t *enp,
4163 __in efx_mae_match_spec_t *spec);
4165 typedef enum efx_mae_field_id_e {
4167 * Fields which can be set by efx_mae_match_spec_field_set()
4168 * or by using dedicated field-specific helper APIs.
4170 EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR = 0,
4171 EFX_MAE_FIELD_ETHER_TYPE_BE,
4172 EFX_MAE_FIELD_ETH_SADDR_BE,
4173 EFX_MAE_FIELD_ETH_DADDR_BE,
4174 EFX_MAE_FIELD_VLAN0_TCI_BE,
4175 EFX_MAE_FIELD_VLAN0_PROTO_BE,
4176 EFX_MAE_FIELD_VLAN1_TCI_BE,
4177 EFX_MAE_FIELD_VLAN1_PROTO_BE,
4178 EFX_MAE_FIELD_SRC_IP4_BE,
4179 EFX_MAE_FIELD_DST_IP4_BE,
4180 EFX_MAE_FIELD_IP_PROTO,
4181 EFX_MAE_FIELD_IP_TOS,
4182 EFX_MAE_FIELD_IP_TTL,
4183 EFX_MAE_FIELD_SRC_IP6_BE,
4184 EFX_MAE_FIELD_DST_IP6_BE,
4185 EFX_MAE_FIELD_L4_SPORT_BE,
4186 EFX_MAE_FIELD_L4_DPORT_BE,
4187 EFX_MAE_FIELD_TCP_FLAGS_BE,
4188 EFX_MAE_FIELD_ENC_ETHER_TYPE_BE,
4189 EFX_MAE_FIELD_ENC_ETH_SADDR_BE,
4190 EFX_MAE_FIELD_ENC_ETH_DADDR_BE,
4191 EFX_MAE_FIELD_ENC_VLAN0_TCI_BE,
4192 EFX_MAE_FIELD_ENC_VLAN0_PROTO_BE,
4193 EFX_MAE_FIELD_ENC_VLAN1_TCI_BE,
4194 EFX_MAE_FIELD_ENC_VLAN1_PROTO_BE,
4195 EFX_MAE_FIELD_ENC_SRC_IP4_BE,
4196 EFX_MAE_FIELD_ENC_DST_IP4_BE,
4197 EFX_MAE_FIELD_ENC_IP_PROTO,
4198 EFX_MAE_FIELD_ENC_IP_TOS,
4199 EFX_MAE_FIELD_ENC_IP_TTL,
4200 EFX_MAE_FIELD_ENC_SRC_IP6_BE,
4201 EFX_MAE_FIELD_ENC_DST_IP6_BE,
4202 EFX_MAE_FIELD_ENC_L4_SPORT_BE,
4203 EFX_MAE_FIELD_ENC_L4_DPORT_BE,
4204 EFX_MAE_FIELD_ENC_VNET_ID_BE,
4205 EFX_MAE_FIELD_OUTER_RULE_ID,
4207 /* Single bits which can be set by efx_mae_match_spec_bit_set(). */
4208 EFX_MAE_FIELD_HAS_OVLAN,
4209 EFX_MAE_FIELD_HAS_IVLAN,
4210 EFX_MAE_FIELD_ENC_HAS_OVLAN,
4211 EFX_MAE_FIELD_ENC_HAS_IVLAN,
4214 * Fields which can be set by efx_mae_match_spec_field_set()
4215 * or by using dedicated field-specific helper APIs.
4217 EFX_MAE_FIELD_RECIRC_ID,
4219 } efx_mae_field_id_t;
4221 /* MPORT selector. Used to refer to MPORTs in match/action rules. */
4222 typedef struct efx_mport_sel_s {
4227 * MPORT ID. Used to refer dynamically to a specific MPORT.
4228 * The difference between MPORT selector and MPORT ID is that
4229 * selector can specify an exact MPORT ID or it can specify a
4230 * pattern by which an exact MPORT ID can be selected. For example,
4231 * static MPORT selector can specify MPORT of a current PF, which
4232 * will be translated to the dynamic MPORT ID based on which PF is
4233 * using that MPORT selector.
4235 typedef struct efx_mport_id_s {
4239 typedef enum efx_mport_type_e {
4240 EFX_MPORT_TYPE_NET_PORT = 0,
4241 EFX_MPORT_TYPE_ALIAS,
4242 EFX_MPORT_TYPE_VNIC,
4245 typedef enum efx_mport_vnic_client_type_e {
4246 EFX_MPORT_VNIC_CLIENT_FUNCTION = 1,
4247 EFX_MPORT_VNIC_CLIENT_PLUGIN,
4248 } efx_mport_vnic_client_type_t;
4250 typedef struct efx_mport_desc_s {
4251 efx_mport_id_t emd_id;
4252 boolean_t emd_can_receive_on;
4253 boolean_t emd_can_deliver_to;
4254 boolean_t emd_can_delete;
4255 boolean_t emd_zombie;
4256 efx_mport_type_t emd_type;
4262 efx_mport_id_t ea_target_mport_id;
4265 efx_mport_vnic_client_type_t ev_client_type;
4266 efx_pcie_interface_t ev_intf;
4269 /* MCDI client handle for this VNIC. */
4275 #define EFX_MPORT_NULL (0U)
4278 * Generate an invalid MPORT selector.
4280 * The resulting MPORT selector is opaque to the caller. Requests
4281 * that attempt to use it will be rejected.
4284 extern __checkReturn efx_rc_t
4285 efx_mae_mport_invalid(
4286 __out efx_mport_sel_t *mportp);
4289 * Get MPORT selector of a physical port.
4291 * The resulting MPORT selector is opaque to the caller and can be
4292 * passed as an argument to efx_mae_match_spec_mport_set()
4293 * and efx_mae_action_set_populate_deliver().
4296 extern __checkReturn efx_rc_t
4297 efx_mae_mport_by_phy_port(
4298 __in uint32_t phy_port,
4299 __out efx_mport_sel_t *mportp);
4302 * Get MPORT selector of a PCIe function.
4304 * The resulting MPORT selector is opaque to the caller and can be
4305 * passed as an argument to efx_mae_match_spec_mport_set()
4306 * and efx_mae_action_set_populate_deliver().
4309 extern __checkReturn efx_rc_t
4310 efx_mae_mport_by_pcie_function(
4313 __out efx_mport_sel_t *mportp);
4316 * Get MPORT selector of a multi-host PCIe function.
4318 * The resulting MPORT selector is opaque to the caller and can be
4319 * passed as an argument to efx_mae_match_spec_mport_set()
4320 * and efx_mae_action_set_populate_deliver().
4323 extern __checkReturn efx_rc_t
4324 efx_mae_mport_by_pcie_mh_function(
4325 __in efx_pcie_interface_t intf,
4328 __out efx_mport_sel_t *mportp);
4331 * Get MPORT selector by an MPORT ID
4333 * The resulting MPORT selector is opaque to the caller and can be
4334 * passed as an argument to efx_mae_match_spec_mport_set()
4335 * and efx_mae_action_set_populate_deliver().
4338 extern __checkReturn efx_rc_t
4339 efx_mae_mport_by_id(
4340 __in const efx_mport_id_t *mport_idp,
4341 __out efx_mport_sel_t *mportp);
4343 /* Get MPORT ID by an MPORT selector */
4345 extern __checkReturn efx_rc_t
4346 efx_mae_mport_id_by_selector(
4347 __in efx_nic_t *enp,
4348 __in const efx_mport_sel_t *mport_selectorp,
4349 __out efx_mport_id_t *mport_idp);
4352 * Fields which have BE postfix in their named constants are expected
4353 * to be passed by callers in big-endian byte order. They will appear
4354 * in the MCDI buffer, which is a part of the match specification, in
4355 * the very same byte order, that is, no conversion will be performed.
4357 * Fields which don't have BE postfix in their named constants are in
4358 * host byte order. MCDI expects them to be little-endian, so the API
4359 * will take care to carry out conversion to little-endian byte order.
4360 * At the moment, the only field in host byte order is MPORT selector.
4363 extern __checkReturn efx_rc_t
4364 efx_mae_match_spec_field_set(
4365 __in efx_mae_match_spec_t *spec,
4366 __in efx_mae_field_id_t field_id,
4367 __in size_t value_size,
4368 __in_bcount(value_size) const uint8_t *value,
4369 __in size_t mask_size,
4370 __in_bcount(mask_size) const uint8_t *mask);
4372 /* The corresponding mask will be set to B_TRUE. */
4374 extern __checkReturn efx_rc_t
4375 efx_mae_match_spec_bit_set(
4376 __in efx_mae_match_spec_t *spec,
4377 __in efx_mae_field_id_t field_id,
4378 __in boolean_t value);
4380 /* If the mask argument is NULL, the API will use full mask by default. */
4382 extern __checkReturn efx_rc_t
4383 efx_mae_match_spec_mport_set(
4384 __in efx_mae_match_spec_t *spec,
4385 __in const efx_mport_sel_t *valuep,
4386 __in_opt const efx_mport_sel_t *maskp);
4389 extern __checkReturn efx_rc_t
4390 efx_mae_match_spec_recirc_id_set(
4391 __in efx_mae_match_spec_t *spec,
4392 __in uint8_t recirc_id);
4395 extern __checkReturn boolean_t
4396 efx_mae_match_specs_equal(
4397 __in const efx_mae_match_spec_t *left,
4398 __in const efx_mae_match_spec_t *right);
4401 * Make sure that match fields known by EFX have proper masks set
4402 * in the match specification as per requirements of SF-122526-TC.
4404 * In the case efx_mae_field_id_t lacks named identifiers for any
4405 * fields which the FW maintains with support status MATCH_ALWAYS,
4406 * the validation result may not be accurate.
4409 extern __checkReturn boolean_t
4410 efx_mae_match_spec_is_valid(
4411 __in efx_nic_t *enp,
4412 __in const efx_mae_match_spec_t *spec);
4414 typedef struct efx_mae_actions_s efx_mae_actions_t;
4417 extern __checkReturn efx_rc_t
4418 efx_mae_action_set_spec_init(
4419 __in efx_nic_t *enp,
4420 __out efx_mae_actions_t **specp);
4424 efx_mae_action_set_spec_fini(
4425 __in efx_nic_t *enp,
4426 __in efx_mae_actions_t *spec);
4429 extern __checkReturn efx_rc_t
4430 efx_mae_action_set_populate_decap(
4431 __in efx_mae_actions_t *spec);
4434 extern __checkReturn efx_rc_t
4435 efx_mae_action_set_populate_vlan_pop(
4436 __in efx_mae_actions_t *spec);
4439 extern __checkReturn efx_rc_t
4440 efx_mae_action_set_populate_vlan_push(
4441 __in efx_mae_actions_t *spec,
4442 __in uint16_t tpid_be,
4443 __in uint16_t tci_be);
4446 * Use efx_mae_action_set_fill_in_eh_id() to set ID of the allocated
4447 * encap. header in the specification prior to action set allocation.
4450 extern __checkReturn efx_rc_t
4451 efx_mae_action_set_populate_encap(
4452 __in efx_mae_actions_t *spec);
4455 * Use efx_mae_action_set_fill_in_counter_id() to set ID of a counter
4456 * in the specification prior to action set allocation.
4458 * NOTICE: the HW will conduct action COUNT after actions DECAP,
4459 * VLAN_POP, VLAN_PUSH (if any) have been applied to the packet,
4460 * but, as a workaround, this order is not validated by the API.
4462 * The workaround helps to unblock DPDK + Open vSwitch use case.
4463 * In Open vSwitch, this action is always the first to be added,
4464 * in particular, it's known to be inserted before action DECAP,
4465 * so enforcing the right order here would cause runtime errors.
4466 * The existing behaviour in Open vSwitch is unlikely to change
4467 * any time soon, and the workaround is a good solution because
4468 * in fact the real COUNT order is a don't care to Open vSwitch.
4471 extern __checkReturn efx_rc_t
4472 efx_mae_action_set_populate_count(
4473 __in efx_mae_actions_t *spec);
4476 extern __checkReturn efx_rc_t
4477 efx_mae_action_set_populate_flag(
4478 __in efx_mae_actions_t *spec);
4481 extern __checkReturn efx_rc_t
4482 efx_mae_action_set_populate_mark(
4483 __in efx_mae_actions_t *spec,
4484 __in uint32_t mark_value);
4487 extern __checkReturn efx_rc_t
4488 efx_mae_action_set_populate_deliver(
4489 __in efx_mae_actions_t *spec,
4490 __in const efx_mport_sel_t *mportp);
4493 extern __checkReturn efx_rc_t
4494 efx_mae_action_set_populate_drop(
4495 __in efx_mae_actions_t *spec);
4498 extern __checkReturn boolean_t
4499 efx_mae_action_set_specs_equal(
4500 __in const efx_mae_actions_t *left,
4501 __in const efx_mae_actions_t *right);
4504 * Conduct a comparison to check whether two match specifications
4505 * of equal rule type (action / outer) and priority would map to
4506 * the very same rule class from the firmware's standpoint.
4508 * For match specification fields that are not supported by firmware,
4509 * the rule class only matches if the mask/value pairs for that field
4510 * are equal. Clients should use efx_mae_match_spec_is_valid() before
4511 * calling this API to detect usage of unsupported fields.
4514 extern __checkReturn efx_rc_t
4515 efx_mae_match_specs_class_cmp(
4516 __in efx_nic_t *enp,
4517 __in const efx_mae_match_spec_t *left,
4518 __in const efx_mae_match_spec_t *right,
4519 __out boolean_t *have_same_classp);
4521 #define EFX_MAE_RSRC_ID_INVALID UINT32_MAX
4524 typedef struct efx_mae_rule_id_s {
4526 } efx_mae_rule_id_t;
4529 * Set the initial recirculation ID. It goes to action rule (AR) lookup.
4531 * To match on this ID in an AR, use efx_mae_match_spec_recirc_id_set().
4534 extern __checkReturn efx_rc_t
4535 efx_mae_outer_rule_recirc_id_set(
4536 __in efx_mae_match_spec_t *spec,
4537 __in uint8_t recirc_id);
4540 extern __checkReturn efx_rc_t
4541 efx_mae_outer_rule_insert(
4542 __in efx_nic_t *enp,
4543 __in const efx_mae_match_spec_t *spec,
4544 __in efx_tunnel_protocol_t encap_type,
4545 __out efx_mae_rule_id_t *or_idp);
4548 extern __checkReturn efx_rc_t
4549 efx_mae_outer_rule_remove(
4550 __in efx_nic_t *enp,
4551 __in const efx_mae_rule_id_t *or_idp);
4554 extern __checkReturn efx_rc_t
4555 efx_mae_match_spec_outer_rule_id_set(
4556 __in efx_mae_match_spec_t *spec,
4557 __in const efx_mae_rule_id_t *or_idp);
4559 /* Encap. header ID */
4560 typedef struct efx_mae_eh_id_s {
4565 extern __checkReturn efx_rc_t
4566 efx_mae_encap_header_alloc(
4567 __in efx_nic_t *enp,
4568 __in efx_tunnel_protocol_t encap_type,
4569 __in_bcount(header_size) uint8_t *header_data,
4570 __in size_t header_size,
4571 __out efx_mae_eh_id_t *eh_idp);
4574 extern __checkReturn efx_rc_t
4575 efx_mae_encap_header_free(
4576 __in efx_nic_t *enp,
4577 __in const efx_mae_eh_id_t *eh_idp);
4579 /* See description before efx_mae_action_set_populate_encap(). */
4581 extern __checkReturn efx_rc_t
4582 efx_mae_action_set_fill_in_eh_id(
4583 __in efx_mae_actions_t *spec,
4584 __in const efx_mae_eh_id_t *eh_idp);
4586 typedef struct efx_counter_s {
4591 extern __checkReturn unsigned int
4592 efx_mae_action_set_get_nb_count(
4593 __in const efx_mae_actions_t *spec);
4595 /* See description before efx_mae_action_set_populate_count(). */
4597 extern __checkReturn efx_rc_t
4598 efx_mae_action_set_fill_in_counter_id(
4599 __in efx_mae_actions_t *spec,
4600 __in const efx_counter_t *counter_idp);
4603 typedef struct efx_mae_aset_id_s {
4605 } efx_mae_aset_id_t;
4608 extern __checkReturn efx_rc_t
4609 efx_mae_action_set_alloc(
4610 __in efx_nic_t *enp,
4611 __in const efx_mae_actions_t *spec,
4612 __out efx_mae_aset_id_t *aset_idp);
4615 * Generation count has two purposes:
4617 * 1) Distinguish between counter packets that belong to freed counter
4618 * and the packets that belong to reallocated counter (with the same ID);
4619 * 2) Make sure that all packets are received for a counter that was freed;
4621 * API users should provide generation count out parameter in allocation
4622 * function if counters can be reallocated and consistent counter values are
4625 * API users that need consistent final counter values after counter
4626 * deallocation or counter stream stop should provide the parameter in
4627 * functions that free the counters and stop the counter stream.
4630 extern __checkReturn efx_rc_t
4631 efx_mae_counters_alloc(
4632 __in efx_nic_t *enp,
4633 __in uint32_t n_counters,
4634 __out uint32_t *n_allocatedp,
4635 __out_ecount(n_counters) efx_counter_t *countersp,
4636 __out_opt uint32_t *gen_countp);
4639 extern __checkReturn efx_rc_t
4640 efx_mae_counters_free(
4641 __in efx_nic_t *enp,
4642 __in uint32_t n_counters,
4643 __out uint32_t *n_freedp,
4644 __in_ecount(n_counters) const efx_counter_t *countersp,
4645 __out_opt uint32_t *gen_countp);
4647 /* When set, include counters with a value of zero */
4648 #define EFX_MAE_COUNTERS_STREAM_IN_ZERO_SQUASH_DISABLE (1U << 0)
4651 * Set if credit-based flow control is used. In this case the driver
4652 * must call efx_mae_counters_stream_give_credits() to notify the
4653 * packetiser of descriptors written.
4655 #define EFX_MAE_COUNTERS_STREAM_OUT_USES_CREDITS (1U << 0)
4658 extern __checkReturn efx_rc_t
4659 efx_mae_counters_stream_start(
4660 __in efx_nic_t *enp,
4661 __in uint16_t rxq_id,
4662 __in uint16_t packet_size,
4663 __in uint32_t flags_in,
4664 __out uint32_t *flags_out);
4667 extern __checkReturn efx_rc_t
4668 efx_mae_counters_stream_stop(
4669 __in efx_nic_t *enp,
4670 __in uint16_t rxq_id,
4671 __out_opt uint32_t *gen_countp);
4674 extern __checkReturn efx_rc_t
4675 efx_mae_counters_stream_give_credits(
4676 __in efx_nic_t *enp,
4677 __in uint32_t n_credits);
4680 extern __checkReturn efx_rc_t
4681 efx_mae_action_set_free(
4682 __in efx_nic_t *enp,
4683 __in const efx_mae_aset_id_t *aset_idp);
4685 /* Action set list ID */
4686 typedef struct efx_mae_aset_list_id_s {
4688 } efx_mae_aset_list_id_t;
4691 * Either action set list ID or action set ID must be passed to this API,
4695 extern __checkReturn efx_rc_t
4696 efx_mae_action_rule_insert(
4697 __in efx_nic_t *enp,
4698 __in const efx_mae_match_spec_t *spec,
4699 __in const efx_mae_aset_list_id_t *asl_idp,
4700 __in const efx_mae_aset_id_t *as_idp,
4701 __out efx_mae_rule_id_t *ar_idp);
4704 extern __checkReturn efx_rc_t
4705 efx_mae_action_rule_remove(
4706 __in efx_nic_t *enp,
4707 __in const efx_mae_rule_id_t *ar_idp);
4710 extern __checkReturn efx_rc_t
4711 efx_mcdi_mport_alloc_alias(
4712 __in efx_nic_t *enp,
4713 __out efx_mport_id_t *mportp,
4714 __out_opt uint32_t *labelp);
4717 extern __checkReturn efx_rc_t
4719 __in efx_nic_t *enp,
4720 __in const efx_mport_id_t *mportp);
4722 typedef __checkReturn efx_rc_t
4723 (efx_mae_read_mport_journal_cb)(
4724 __in void *cb_datap,
4725 __in efx_mport_desc_t *mportp,
4726 __in size_t mport_len);
4729 * Read mport descriptions from the MAE journal (which describes added and
4730 * removed mports) and pass them to a user-supplied callback. The user gets
4731 * only one chance to process the data it's given. Once the callback function
4732 * finishes, that particular mport description will be gone.
4733 * The journal will be fully repopulated on PCI reset (efx_nic_reset function).
4736 extern __checkReturn efx_rc_t
4737 efx_mae_read_mport_journal(
4738 __in efx_nic_t *enp,
4739 __in efx_mae_read_mport_journal_cb *cbp,
4740 __in void *cb_datap);
4742 #endif /* EFSYS_OPT_MAE */
4744 #if EFSYS_OPT_VIRTIO
4746 /* A Virtio net device can have one or more pairs of Rx/Tx virtqueues
4747 * while virtio block device has a single virtqueue,
4748 * for further details refer section of 4.2.3 of SF-120734
4750 typedef enum efx_virtio_vq_type_e {
4751 EFX_VIRTIO_VQ_TYPE_NET_RXQ,
4752 EFX_VIRTIO_VQ_TYPE_NET_TXQ,
4753 EFX_VIRTIO_VQ_TYPE_BLOCK,
4754 EFX_VIRTIO_VQ_NTYPES
4755 } efx_virtio_vq_type_t;
4757 typedef struct efx_virtio_vq_dyncfg_s {
4759 * If queue is being created to be migrated then this
4760 * should be the FINAL_PIDX value returned by MC_CMD_VIRTIO_FINI_QUEUE
4761 * of the queue being migrated from. Otherwise, it should be zero.
4763 uint32_t evvd_vq_pidx;
4765 * If this queue is being created to be migrated then this
4766 * should be the FINAL_CIDX value returned by MC_CMD_VIRTIO_FINI_QUEUE
4767 * of the queue being migrated from. Otherwise, it should be zero.
4769 uint32_t evvd_vq_cidx;
4770 } efx_virtio_vq_dyncfg_t;
4773 * Virtqueue size must be a power of 2, maximum size is 32768
4774 * (see VIRTIO v1.1 section 2.6)
4776 #define EFX_VIRTIO_MAX_VQ_SIZE 0x8000
4778 typedef struct efx_virtio_vq_cfg_s {
4779 unsigned int evvc_vq_num;
4780 efx_virtio_vq_type_t evvc_type;
4782 * vDPA as VF : It is target VF number if queue is being created on VF.
4783 * vDPA as PF : If queue to be created on PF then it should be
4784 * EFX_PCI_VF_INVALID.
4786 uint16_t evvc_target_vf;
4788 * Maximum virtqueue size is EFX_VIRTIO_MAX_VQ_SIZE and
4789 * virtqueue size 0 means the queue is unavailable.
4791 uint32_t evvc_vq_size;
4792 efsys_dma_addr_t evvc_desc_tbl_addr;
4793 efsys_dma_addr_t evvc_avail_ring_addr;
4794 efsys_dma_addr_t evvc_used_ring_addr;
4795 /* MSIX vector number for the virtqueue or 0xFFFF if MSIX is not used */
4796 uint16_t evvc_msix_vector;
4798 * evvc_pas_id contains a PCIe address space identifier if the queue
4801 boolean_t evvc_use_pasid;
4802 uint32_t evvc_pas_id;
4803 /* Negotiated virtio features to be applied to this virtqueue */
4804 uint64_t evcc_features;
4805 } efx_virtio_vq_cfg_t;
4807 typedef struct efx_virtio_vq_s efx_virtio_vq_t;
4809 typedef enum efx_virtio_device_type_e {
4810 EFX_VIRTIO_DEVICE_TYPE_RESERVED,
4811 EFX_VIRTIO_DEVICE_TYPE_NET,
4812 EFX_VIRTIO_DEVICE_TYPE_BLOCK,
4813 EFX_VIRTIO_DEVICE_NTYPES
4814 } efx_virtio_device_type_t;
4817 extern __checkReturn efx_rc_t
4819 __in efx_nic_t *enp);
4824 __in efx_nic_t *enp);
4827 * When virtio net driver in the guest sets VIRTIO_CONFIG_STATUS_DRIVER_OK bit,
4828 * hypervisor starts configuring all the virtqueues in the device. When the
4829 * vhost_user has received VHOST_USER_SET_VRING_ENABLE for all the virtqueues,
4830 * then it invokes VDPA driver callback dev_conf. APIs qstart and qcreate would
4831 * be invoked from dev_conf callback to create the virtqueues, For further
4832 * details refer SF-122427.
4835 extern __checkReturn efx_rc_t
4837 __in efx_nic_t *enp,
4838 __deref_out efx_virtio_vq_t **evvpp);
4841 extern __checkReturn efx_rc_t
4843 __in efx_virtio_vq_t *evvp,
4844 __in efx_virtio_vq_cfg_t *evvcp,
4845 __in_opt efx_virtio_vq_dyncfg_t *evvdp);
4848 extern __checkReturn efx_rc_t
4850 __in efx_virtio_vq_t *evvp,
4851 __out_opt efx_virtio_vq_dyncfg_t *evvdp);
4855 efx_virtio_qdestroy(
4856 __in efx_virtio_vq_t *evvp);
4859 * Get the offset in the BAR of the doorbells for a VI.
4860 * net device : doorbell offset of RX & TX queues
4861 * block device : request doorbell offset in the BAR.
4862 * For further details refer section of 4 of SF-119689
4865 extern __checkReturn efx_rc_t
4866 efx_virtio_get_doorbell_offset(
4867 __in efx_virtio_vq_t *evvp,
4868 __out uint32_t *offsetp);
4871 extern __checkReturn efx_rc_t
4872 efx_virtio_get_features(
4873 __in efx_nic_t *enp,
4874 __in efx_virtio_device_type_t type,
4875 __out uint64_t *featuresp);
4878 extern __checkReturn efx_rc_t
4879 efx_virtio_verify_features(
4880 __in efx_nic_t *enp,
4881 __in efx_virtio_device_type_t type,
4882 __in uint64_t features);
4884 #endif /* EFSYS_OPT_VIRTIO */
4890 #endif /* _SYS_EFX_H */