1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2007-2019 Solarflare Communications Inc.
12 static __checkReturn efx_rc_t
13 siena_mac_multicast_list_set(
16 #endif /* EFSYS_OPT_SIENA */
19 static const efx_mac_ops_t __efx_mac_siena_ops = {
20 siena_mac_poll, /* emo_poll */
21 siena_mac_up, /* emo_up */
22 siena_mac_reconfigure, /* emo_addr_set */
23 siena_mac_reconfigure, /* emo_pdu_set */
24 siena_mac_pdu_get, /* emo_pdu_get */
25 siena_mac_reconfigure, /* emo_reconfigure */
26 siena_mac_multicast_list_set, /* emo_multicast_list_set */
27 NULL, /* emo_filter_set_default_rxq */
28 NULL, /* emo_filter_default_rxq_clear */
29 #if EFSYS_OPT_LOOPBACK
30 siena_mac_loopback_set, /* emo_loopback_set */
31 #endif /* EFSYS_OPT_LOOPBACK */
32 #if EFSYS_OPT_MAC_STATS
33 siena_mac_stats_get_mask, /* emo_stats_get_mask */
34 efx_mcdi_mac_stats_clear, /* emo_stats_clear */
35 efx_mcdi_mac_stats_upload, /* emo_stats_upload */
36 efx_mcdi_mac_stats_periodic, /* emo_stats_periodic */
37 siena_mac_stats_update /* emo_stats_update */
38 #endif /* EFSYS_OPT_MAC_STATS */
40 #endif /* EFSYS_OPT_SIENA */
43 static const efx_mac_ops_t __efx_mac_ef10_ops = {
44 ef10_mac_poll, /* emo_poll */
45 ef10_mac_up, /* emo_up */
46 ef10_mac_addr_set, /* emo_addr_set */
47 ef10_mac_pdu_set, /* emo_pdu_set */
48 ef10_mac_pdu_get, /* emo_pdu_get */
49 ef10_mac_reconfigure, /* emo_reconfigure */
50 ef10_mac_multicast_list_set, /* emo_multicast_list_set */
51 ef10_mac_filter_default_rxq_set, /* emo_filter_default_rxq_set */
52 ef10_mac_filter_default_rxq_clear,
53 /* emo_filter_default_rxq_clear */
54 #if EFSYS_OPT_LOOPBACK
55 ef10_mac_loopback_set, /* emo_loopback_set */
56 #endif /* EFSYS_OPT_LOOPBACK */
57 #if EFSYS_OPT_MAC_STATS
58 ef10_mac_stats_get_mask, /* emo_stats_get_mask */
59 efx_mcdi_mac_stats_clear, /* emo_stats_clear */
60 efx_mcdi_mac_stats_upload, /* emo_stats_upload */
61 efx_mcdi_mac_stats_periodic, /* emo_stats_periodic */
62 ef10_mac_stats_update /* emo_stats_update */
63 #endif /* EFSYS_OPT_MAC_STATS */
65 #endif /* EFX_OPTS_EF10() */
67 #if EFSYS_OPT_RIVERHEAD
68 static const efx_mac_ops_t __efx_mac_rhead_ops = {
69 ef10_mac_poll, /* emo_poll */
70 ef10_mac_up, /* emo_up */
71 ef10_mac_addr_set, /* emo_addr_set */
72 ef10_mac_pdu_set, /* emo_pdu_set */
73 ef10_mac_pdu_get, /* emo_pdu_get */
74 ef10_mac_reconfigure, /* emo_reconfigure */
75 ef10_mac_multicast_list_set, /* emo_multicast_list_set */
76 ef10_mac_filter_default_rxq_set, /* emo_filter_default_rxq_set */
77 ef10_mac_filter_default_rxq_clear,
78 /* emo_filter_default_rxq_clear */
79 #if EFSYS_OPT_LOOPBACK
80 ef10_mac_loopback_set, /* emo_loopback_set */
81 #endif /* EFSYS_OPT_LOOPBACK */
82 #if EFSYS_OPT_MAC_STATS
83 ef10_mac_stats_get_mask, /* emo_stats_get_mask */
84 efx_mcdi_mac_stats_clear, /* emo_stats_clear */
85 efx_mcdi_mac_stats_upload, /* emo_stats_upload */
86 efx_mcdi_mac_stats_periodic, /* emo_stats_periodic */
87 ef10_mac_stats_update /* emo_stats_update */
88 #endif /* EFSYS_OPT_MAC_STATS */
90 #endif /* EFSYS_OPT_RIVERHEAD */
92 __checkReturn efx_rc_t
97 efx_port_t *epp = &(enp->en_port);
98 const efx_mac_ops_t *emop = epp->ep_emop;
102 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
103 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
104 EFSYS_ASSERT(emop != NULL);
106 if (pdu < EFX_MAC_PDU_MIN) {
111 if (pdu > EFX_MAC_PDU_MAX) {
116 old_pdu = epp->ep_mac_pdu;
117 epp->ep_mac_pdu = (uint32_t)pdu;
118 if ((rc = emop->emo_pdu_set(enp)) != 0)
126 epp->ep_mac_pdu = old_pdu;
131 EFSYS_PROBE1(fail1, efx_rc_t, rc);
136 __checkReturn efx_rc_t
141 efx_port_t *epp = &(enp->en_port);
142 const efx_mac_ops_t *emop = epp->ep_emop;
145 if ((rc = emop->emo_pdu_get(enp, pdu)) != 0)
151 EFSYS_PROBE1(fail1, efx_rc_t, rc);
156 __checkReturn efx_rc_t
161 efx_port_t *epp = &(enp->en_port);
162 const efx_mac_ops_t *emop = epp->ep_emop;
167 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
168 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
170 if (EFX_MAC_ADDR_IS_MULTICAST(addr)) {
175 oui = addr[0] << 16 | addr[1] << 8 | addr[2];
176 if (oui == 0x000000) {
181 EFX_MAC_ADDR_COPY(old_addr, epp->ep_mac_addr);
182 EFX_MAC_ADDR_COPY(epp->ep_mac_addr, addr);
183 if ((rc = emop->emo_addr_set(enp)) != 0)
191 EFX_MAC_ADDR_COPY(epp->ep_mac_addr, old_addr);
196 EFSYS_PROBE1(fail1, efx_rc_t, rc);
201 __checkReturn efx_rc_t
204 __in boolean_t all_unicst,
205 __in boolean_t mulcst,
206 __in boolean_t all_mulcst,
207 __in boolean_t brdcst)
209 efx_port_t *epp = &(enp->en_port);
210 const efx_mac_ops_t *emop = epp->ep_emop;
211 boolean_t old_all_unicst;
212 boolean_t old_mulcst;
213 boolean_t old_all_mulcst;
214 boolean_t old_brdcst;
217 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
218 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
220 old_all_unicst = epp->ep_all_unicst;
221 old_mulcst = epp->ep_mulcst;
222 old_all_mulcst = epp->ep_all_mulcst;
223 old_brdcst = epp->ep_brdcst;
225 epp->ep_all_unicst = all_unicst;
226 epp->ep_mulcst = mulcst;
227 epp->ep_all_mulcst = all_mulcst;
228 epp->ep_brdcst = brdcst;
230 if ((rc = emop->emo_reconfigure(enp)) != 0)
236 EFSYS_PROBE1(fail1, efx_rc_t, rc);
238 epp->ep_all_unicst = old_all_unicst;
239 epp->ep_mulcst = old_mulcst;
240 epp->ep_all_mulcst = old_all_mulcst;
241 epp->ep_brdcst = old_brdcst;
247 efx_mac_filter_get_all_ucast_mcast(
249 __out boolean_t *all_unicst,
250 __out boolean_t *all_mulcst)
252 efx_port_t *epp = &(enp->en_port);
254 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
255 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
257 *all_unicst = epp->ep_all_unicst_inserted;
258 *all_mulcst = epp->ep_all_mulcst_inserted;
261 __checkReturn efx_rc_t
264 __in boolean_t enabled)
266 efx_port_t *epp = &(enp->en_port);
267 const efx_mac_ops_t *emop = epp->ep_emop;
270 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
271 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
272 EFSYS_ASSERT(emop != NULL);
274 if (epp->ep_mac_drain == enabled)
277 epp->ep_mac_drain = enabled;
279 if ((rc = emop->emo_reconfigure(enp)) != 0)
285 EFSYS_PROBE1(fail1, efx_rc_t, rc);
290 __checkReturn efx_rc_t
293 __out boolean_t *mac_upp)
295 efx_port_t *epp = &(enp->en_port);
296 const efx_mac_ops_t *emop = epp->ep_emop;
299 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
300 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
302 if ((rc = emop->emo_up(enp, mac_upp)) != 0)
308 EFSYS_PROBE1(fail1, efx_rc_t, rc);
313 __checkReturn efx_rc_t
316 __in unsigned int fcntl,
317 __in boolean_t autoneg)
319 efx_port_t *epp = &(enp->en_port);
320 const efx_mac_ops_t *emop = epp->ep_emop;
321 const efx_phy_ops_t *epop = epp->ep_epop;
322 unsigned int old_fcntl;
323 boolean_t old_autoneg;
324 unsigned int old_adv_cap;
327 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
328 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
330 if ((fcntl & ~(EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE)) != 0) {
336 * Ignore a request to set flow control auto-negotiation
337 * if the PHY doesn't support it.
339 if (~epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN))
342 old_fcntl = epp->ep_fcntl;
343 old_autoneg = epp->ep_fcntl_autoneg;
344 old_adv_cap = epp->ep_adv_cap_mask;
346 epp->ep_fcntl = fcntl;
347 epp->ep_fcntl_autoneg = autoneg;
350 * Always encode the flow control settings in the advertised
351 * capabilities even if we are not trying to auto-negotiate
352 * them and reconfigure both the PHY and the MAC.
354 if (fcntl & EFX_FCNTL_RESPOND)
355 epp->ep_adv_cap_mask |= (1 << EFX_PHY_CAP_PAUSE |
356 1 << EFX_PHY_CAP_ASYM);
358 epp->ep_adv_cap_mask &= ~(1 << EFX_PHY_CAP_PAUSE |
359 1 << EFX_PHY_CAP_ASYM);
361 if (fcntl & EFX_FCNTL_GENERATE)
362 epp->ep_adv_cap_mask ^= (1 << EFX_PHY_CAP_ASYM);
364 if ((rc = epop->epo_reconfigure(enp)) != 0)
367 if ((rc = emop->emo_reconfigure(enp)) != 0)
378 epp->ep_fcntl = old_fcntl;
379 epp->ep_fcntl_autoneg = old_autoneg;
380 epp->ep_adv_cap_mask = old_adv_cap;
383 EFSYS_PROBE1(fail1, efx_rc_t, rc);
391 __out unsigned int *fcntl_wantedp,
392 __out unsigned int *fcntl_linkp)
394 efx_port_t *epp = &(enp->en_port);
395 unsigned int wanted = 0;
397 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
398 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
401 * Decode the requested flow control settings from the PHY
402 * advertised capabilities.
404 if (epp->ep_adv_cap_mask & (1 << EFX_PHY_CAP_PAUSE))
405 wanted = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE;
406 if (epp->ep_adv_cap_mask & (1 << EFX_PHY_CAP_ASYM))
407 wanted ^= EFX_FCNTL_GENERATE;
409 *fcntl_linkp = epp->ep_fcntl;
410 *fcntl_wantedp = wanted;
413 __checkReturn efx_rc_t
414 efx_mac_multicast_list_set(
416 __in_ecount(6*count) uint8_t const *addrs,
419 efx_port_t *epp = &(enp->en_port);
420 const efx_mac_ops_t *emop = epp->ep_emop;
421 uint8_t *old_mulcst_addr_list = NULL;
422 uint32_t old_mulcst_addr_count;
425 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
426 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
428 if (count > EFX_MAC_MULTICAST_LIST_MAX) {
433 old_mulcst_addr_count = epp->ep_mulcst_addr_count;
434 if (old_mulcst_addr_count > 0) {
435 /* Allocate memory to store old list (instead of using stack) */
436 EFSYS_KMEM_ALLOC(enp->en_esip,
437 old_mulcst_addr_count * EFX_MAC_ADDR_LEN,
438 old_mulcst_addr_list);
439 if (old_mulcst_addr_list == NULL) {
444 /* Save the old list in case we need to rollback */
445 memcpy(old_mulcst_addr_list, epp->ep_mulcst_addr_list,
446 old_mulcst_addr_count * EFX_MAC_ADDR_LEN);
449 /* Store the new list */
450 memcpy(epp->ep_mulcst_addr_list, addrs,
451 count * EFX_MAC_ADDR_LEN);
452 epp->ep_mulcst_addr_count = count;
454 if ((rc = emop->emo_multicast_list_set(enp)) != 0)
457 if (old_mulcst_addr_count > 0) {
458 EFSYS_KMEM_FREE(enp->en_esip,
459 old_mulcst_addr_count * EFX_MAC_ADDR_LEN,
460 old_mulcst_addr_list);
468 /* Restore original list on failure */
469 epp->ep_mulcst_addr_count = old_mulcst_addr_count;
470 if (old_mulcst_addr_count > 0) {
471 memcpy(epp->ep_mulcst_addr_list, old_mulcst_addr_list,
472 old_mulcst_addr_count * EFX_MAC_ADDR_LEN);
474 EFSYS_KMEM_FREE(enp->en_esip,
475 old_mulcst_addr_count * EFX_MAC_ADDR_LEN,
476 old_mulcst_addr_list);
483 EFSYS_PROBE1(fail1, efx_rc_t, rc);
489 __checkReturn efx_rc_t
490 efx_mac_filter_default_rxq_set(
493 __in boolean_t using_rss)
495 efx_port_t *epp = &(enp->en_port);
496 const efx_mac_ops_t *emop = epp->ep_emop;
499 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
500 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
502 if (emop->emo_filter_default_rxq_set != NULL) {
503 rc = emop->emo_filter_default_rxq_set(enp, erp, using_rss);
511 EFSYS_PROBE1(fail1, efx_rc_t, rc);
517 efx_mac_filter_default_rxq_clear(
520 efx_port_t *epp = &(enp->en_port);
521 const efx_mac_ops_t *emop = epp->ep_emop;
523 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
524 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
526 if (emop->emo_filter_default_rxq_clear != NULL)
527 emop->emo_filter_default_rxq_clear(enp);
531 #if EFSYS_OPT_MAC_STATS
535 /* START MKCONFIG GENERATED EfxMacStatNamesBlock 1a45a82fcfb30c1b */
536 static const char * const __efx_mac_stat_name[] = {
545 "rx_128_to_255_pkts",
546 "rx_256_to_511_pkts",
547 "rx_512_to_1023_pkts",
548 "rx_1024_to_15xx_pkts",
553 "rx_false_carrier_errors",
556 "rx_internal_errors",
567 "rx_nodesc_drop_cnt",
576 "tx_128_to_255_pkts",
577 "tx_256_to_511_pkts",
578 "tx_512_to_1023_pkts",
579 "tx_1024_to_15xx_pkts",
588 "pm_trunc_bb_overflow",
589 "pm_discard_bb_overflow",
590 "pm_trunc_vfifo_full",
591 "pm_discard_vfifo_full",
594 "pm_discard_mapping",
595 "rxdp_q_disabled_pkts",
596 "rxdp_di_dropped_pkts",
597 "rxdp_streaming_pkts",
600 "vadapter_rx_unicast_packets",
601 "vadapter_rx_unicast_bytes",
602 "vadapter_rx_multicast_packets",
603 "vadapter_rx_multicast_bytes",
604 "vadapter_rx_broadcast_packets",
605 "vadapter_rx_broadcast_bytes",
606 "vadapter_rx_bad_packets",
607 "vadapter_rx_bad_bytes",
608 "vadapter_rx_overflow",
609 "vadapter_tx_unicast_packets",
610 "vadapter_tx_unicast_bytes",
611 "vadapter_tx_multicast_packets",
612 "vadapter_tx_multicast_bytes",
613 "vadapter_tx_broadcast_packets",
614 "vadapter_tx_broadcast_bytes",
615 "vadapter_tx_bad_packets",
616 "vadapter_tx_bad_bytes",
617 "vadapter_tx_overflow",
618 "fec_uncorrected_errors",
619 "fec_corrected_errors",
620 "fec_corrected_symbols_lane0",
621 "fec_corrected_symbols_lane1",
622 "fec_corrected_symbols_lane2",
623 "fec_corrected_symbols_lane3",
624 "ctpio_vi_busy_fallback",
625 "ctpio_long_write_success",
626 "ctpio_missing_dbell_fail",
627 "ctpio_overflow_fail",
628 "ctpio_underflow_fail",
629 "ctpio_timeout_fail",
630 "ctpio_noncontig_wr_fail",
631 "ctpio_frm_clobber_fail",
632 "ctpio_invalid_wr_fail",
633 "ctpio_vi_clobber_fallback",
634 "ctpio_unqualified_fallback",
635 "ctpio_runt_fallback",
640 "rxdp_scatter_disabled_trunc",
644 /* END MKCONFIG GENERATED EfxMacStatNamesBlock */
646 __checkReturn const char *
649 __in unsigned int id)
651 _NOTE(ARGUNUSED(enp))
652 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
654 EFSYS_ASSERT3U(id, <, EFX_MAC_NSTATS);
655 return (__efx_mac_stat_name[id]);
658 #endif /* EFSYS_OPT_NAMES */
661 efx_mac_stats_mask_add_range(
662 __inout_bcount(mask_size) uint32_t *maskp,
663 __in size_t mask_size,
664 __in const struct efx_mac_stats_range *rngp)
666 unsigned int mask_npages = mask_size / sizeof (*maskp);
675 if ((mask_npages * EFX_MAC_STATS_MASK_BITS_PER_PAGE) <=
676 (unsigned int)rngp->last) {
681 EFSYS_ASSERT3U(rngp->first, <=, rngp->last);
682 EFSYS_ASSERT3U(rngp->last, <, EFX_MAC_NSTATS);
684 for (el = 0; el < mask_npages; ++el) {
685 el_min = el * EFX_MAC_STATS_MASK_BITS_PER_PAGE;
687 el_min + (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1);
688 if ((unsigned int)rngp->first > el_max ||
689 (unsigned int)rngp->last < el_min)
691 low = MAX((unsigned int)rngp->first, el_min);
692 high = MIN((unsigned int)rngp->last, el_max);
693 width = high - low + 1;
695 (width == EFX_MAC_STATS_MASK_BITS_PER_PAGE) ?
696 (~0ULL) : (((1ULL << width) - 1) << (low - el_min));
702 EFSYS_PROBE1(fail1, efx_rc_t, rc);
708 efx_mac_stats_mask_add_ranges(
709 __inout_bcount(mask_size) uint32_t *maskp,
710 __in size_t mask_size,
711 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp,
712 __in unsigned int rng_count)
717 for (i = 0; i < rng_count; ++i) {
718 if ((rc = efx_mac_stats_mask_add_range(maskp, mask_size,
726 EFSYS_PROBE1(fail1, efx_rc_t, rc);
731 __checkReturn efx_rc_t
732 efx_mac_stats_get_mask(
734 __out_bcount(mask_size) uint32_t *maskp,
735 __in size_t mask_size)
737 efx_port_t *epp = &(enp->en_port);
738 const efx_mac_ops_t *emop = epp->ep_emop;
741 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
742 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
743 EFSYS_ASSERT(maskp != NULL);
744 EFSYS_ASSERT(mask_size % sizeof (maskp[0]) == 0);
746 (void) memset(maskp, 0, mask_size);
748 if ((rc = emop->emo_stats_get_mask(enp, maskp, mask_size)) != 0)
754 EFSYS_PROBE1(fail1, efx_rc_t, rc);
759 __checkReturn efx_rc_t
763 efx_port_t *epp = &(enp->en_port);
764 const efx_mac_ops_t *emop = epp->ep_emop;
767 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
768 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
769 EFSYS_ASSERT(emop != NULL);
771 if ((rc = emop->emo_stats_clear(enp)) != 0)
777 EFSYS_PROBE1(fail1, efx_rc_t, rc);
782 __checkReturn efx_rc_t
783 efx_mac_stats_upload(
785 __in efsys_mem_t *esmp)
787 efx_port_t *epp = &(enp->en_port);
788 const efx_mac_ops_t *emop = epp->ep_emop;
791 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
792 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
793 EFSYS_ASSERT(emop != NULL);
795 if ((rc = emop->emo_stats_upload(enp, esmp)) != 0)
801 EFSYS_PROBE1(fail1, efx_rc_t, rc);
806 __checkReturn efx_rc_t
807 efx_mac_stats_periodic(
809 __in efsys_mem_t *esmp,
810 __in uint16_t period_ms,
811 __in boolean_t events)
813 efx_port_t *epp = &(enp->en_port);
814 const efx_mac_ops_t *emop = epp->ep_emop;
817 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
818 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
820 EFSYS_ASSERT(emop != NULL);
822 if (emop->emo_stats_periodic == NULL) {
827 if ((rc = emop->emo_stats_periodic(enp, esmp, period_ms, events)) != 0)
835 EFSYS_PROBE1(fail1, efx_rc_t, rc);
841 __checkReturn efx_rc_t
842 efx_mac_stats_update(
844 __in efsys_mem_t *esmp,
845 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *essp,
846 __inout_opt uint32_t *generationp)
848 efx_port_t *epp = &(enp->en_port);
849 const efx_mac_ops_t *emop = epp->ep_emop;
852 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
853 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
854 EFSYS_ASSERT(emop != NULL);
856 rc = emop->emo_stats_update(enp, esmp, essp, generationp);
861 #endif /* EFSYS_OPT_MAC_STATS */
863 __checkReturn efx_rc_t
867 efx_port_t *epp = &(enp->en_port);
868 efx_mac_type_t type = EFX_MAC_INVALID;
869 const efx_mac_ops_t *emop;
872 switch (enp->en_family) {
874 case EFX_FAMILY_SIENA:
875 emop = &__efx_mac_siena_ops;
876 type = EFX_MAC_SIENA;
878 #endif /* EFSYS_OPT_SIENA */
880 #if EFSYS_OPT_HUNTINGTON
881 case EFX_FAMILY_HUNTINGTON:
882 emop = &__efx_mac_ef10_ops;
883 type = EFX_MAC_HUNTINGTON;
885 #endif /* EFSYS_OPT_HUNTINGTON */
887 #if EFSYS_OPT_MEDFORD
888 case EFX_FAMILY_MEDFORD:
889 emop = &__efx_mac_ef10_ops;
890 type = EFX_MAC_MEDFORD;
892 #endif /* EFSYS_OPT_MEDFORD */
894 #if EFSYS_OPT_MEDFORD2
895 case EFX_FAMILY_MEDFORD2:
896 emop = &__efx_mac_ef10_ops;
897 type = EFX_MAC_MEDFORD2;
899 #endif /* EFSYS_OPT_MEDFORD2 */
901 #if EFSYS_OPT_RIVERHEAD
902 case EFX_FAMILY_RIVERHEAD:
903 emop = &__efx_mac_rhead_ops;
904 type = EFX_MAC_RIVERHEAD;
906 #endif /* EFSYS_OPT_RIVERHEAD */
913 EFSYS_ASSERT(type != EFX_MAC_INVALID);
914 EFSYS_ASSERT3U(type, <, EFX_MAC_NTYPES);
915 EFSYS_ASSERT(emop != NULL);
918 epp->ep_mac_type = type;
923 EFSYS_PROBE1(fail1, efx_rc_t, rc);
931 #define EFX_MAC_HASH_BITS (1 << 8)
933 /* Compute the multicast hash as used on Falcon and Siena. */
935 siena_mac_multicast_hash_compute(
936 __in_ecount(6*count) uint8_t const *addrs,
938 __out efx_oword_t *hash_low,
939 __out efx_oword_t *hash_high)
944 EFSYS_ASSERT(hash_low != NULL);
945 EFSYS_ASSERT(hash_high != NULL);
947 EFX_ZERO_OWORD(*hash_low);
948 EFX_ZERO_OWORD(*hash_high);
950 for (i = 0; i < count; i++) {
951 /* Calculate hash bucket (IEEE 802.3 CRC32 of the MAC addr) */
952 crc = efx_crc32_calculate(0xffffffff, addrs, EFX_MAC_ADDR_LEN);
953 index = crc % EFX_MAC_HASH_BITS;
955 EFX_SET_OWORD_BIT(*hash_low, index);
957 EFX_SET_OWORD_BIT(*hash_high, index - 128);
960 addrs += EFX_MAC_ADDR_LEN;
964 static __checkReturn efx_rc_t
965 siena_mac_multicast_list_set(
968 efx_port_t *epp = &(enp->en_port);
969 const efx_mac_ops_t *emop = epp->ep_emop;
970 efx_oword_t old_hash[2];
973 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
974 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
976 memcpy(old_hash, epp->ep_multicst_hash, sizeof (old_hash));
978 siena_mac_multicast_hash_compute(
979 epp->ep_mulcst_addr_list,
980 epp->ep_mulcst_addr_count,
981 &epp->ep_multicst_hash[0],
982 &epp->ep_multicst_hash[1]);
984 if ((rc = emop->emo_reconfigure(enp)) != 0)
990 EFSYS_PROBE1(fail1, efx_rc_t, rc);
992 memcpy(epp->ep_multicst_hash, old_hash, sizeof (old_hash));
997 #endif /* EFSYS_OPT_SIENA */