1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
12 static const efx_phy_ops_t __efx_phy_siena_ops = {
13 siena_phy_power, /* epo_power */
15 siena_phy_reconfigure, /* epo_reconfigure */
16 siena_phy_verify, /* epo_verify */
17 siena_phy_oui_get, /* epo_oui_get */
18 #if EFSYS_OPT_PHY_STATS
19 siena_phy_stats_update, /* epo_stats_update */
20 #endif /* EFSYS_OPT_PHY_STATS */
22 NULL, /* epo_bist_enable_offline */
23 siena_phy_bist_start, /* epo_bist_start */
24 siena_phy_bist_poll, /* epo_bist_poll */
25 siena_phy_bist_stop, /* epo_bist_stop */
26 #endif /* EFSYS_OPT_BIST */
28 #endif /* EFSYS_OPT_SIENA */
30 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
31 static const efx_phy_ops_t __efx_phy_ef10_ops = {
32 ef10_phy_power, /* epo_power */
34 ef10_phy_reconfigure, /* epo_reconfigure */
35 ef10_phy_verify, /* epo_verify */
36 ef10_phy_oui_get, /* epo_oui_get */
37 #if EFSYS_OPT_PHY_STATS
38 ef10_phy_stats_update, /* epo_stats_update */
39 #endif /* EFSYS_OPT_PHY_STATS */
41 ef10_bist_enable_offline, /* epo_bist_enable_offline */
42 ef10_bist_start, /* epo_bist_start */
43 ef10_bist_poll, /* epo_bist_poll */
44 ef10_bist_stop, /* epo_bist_stop */
45 #endif /* EFSYS_OPT_BIST */
47 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
49 __checkReturn efx_rc_t
53 efx_port_t *epp = &(enp->en_port);
54 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
55 const efx_phy_ops_t *epop;
58 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
60 epp->ep_port = encp->enc_port;
61 epp->ep_phy_type = encp->enc_phy_type;
63 /* Hook in operations structure */
64 switch (enp->en_family) {
66 case EFX_FAMILY_SIENA:
67 epop = &__efx_phy_siena_ops;
69 #endif /* EFSYS_OPT_SIENA */
71 #if EFSYS_OPT_HUNTINGTON
72 case EFX_FAMILY_HUNTINGTON:
73 epop = &__efx_phy_ef10_ops;
75 #endif /* EFSYS_OPT_HUNTINGTON */
78 case EFX_FAMILY_MEDFORD:
79 epop = &__efx_phy_ef10_ops;
81 #endif /* EFSYS_OPT_MEDFORD */
83 #if EFSYS_OPT_MEDFORD2
84 case EFX_FAMILY_MEDFORD2:
85 epop = &__efx_phy_ef10_ops;
87 #endif /* EFSYS_OPT_MEDFORD2 */
99 EFSYS_PROBE1(fail1, efx_rc_t, rc);
102 epp->ep_phy_type = 0;
107 __checkReturn efx_rc_t
111 efx_port_t *epp = &(enp->en_port);
112 const efx_phy_ops_t *epop = epp->ep_epop;
114 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
115 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
117 return (epop->epo_verify(enp));
120 #if EFSYS_OPT_PHY_LED_CONTROL
122 __checkReturn efx_rc_t
125 __in efx_phy_led_mode_t mode)
127 efx_nic_cfg_t *encp = (&enp->en_nic_cfg);
128 efx_port_t *epp = &(enp->en_port);
129 const efx_phy_ops_t *epop = epp->ep_epop;
133 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
134 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
136 if (epp->ep_phy_led_mode == mode)
139 mask = (1 << EFX_PHY_LED_DEFAULT);
140 mask |= encp->enc_led_mask;
142 if (!((1 << mode) & mask)) {
147 EFSYS_ASSERT3U(mode, <, EFX_PHY_LED_NMODES);
148 epp->ep_phy_led_mode = mode;
150 if ((rc = epop->epo_reconfigure(enp)) != 0)
159 EFSYS_PROBE1(fail1, efx_rc_t, rc);
163 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
169 __out uint32_t *maskp)
171 efx_port_t *epp = &(enp->en_port);
173 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
174 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
177 case EFX_PHY_CAP_CURRENT:
178 *maskp = epp->ep_adv_cap_mask;
180 case EFX_PHY_CAP_DEFAULT:
181 *maskp = epp->ep_default_adv_cap_mask;
183 case EFX_PHY_CAP_PERM:
184 *maskp = epp->ep_phy_cap_mask;
187 EFSYS_ASSERT(B_FALSE);
193 __checkReturn efx_rc_t
198 efx_port_t *epp = &(enp->en_port);
199 const efx_phy_ops_t *epop = epp->ep_epop;
203 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
204 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
206 if ((mask & ~epp->ep_phy_cap_mask) != 0) {
211 if (epp->ep_adv_cap_mask == mask)
214 old_mask = epp->ep_adv_cap_mask;
215 epp->ep_adv_cap_mask = mask;
217 if ((rc = epop->epo_reconfigure(enp)) != 0)
226 epp->ep_adv_cap_mask = old_mask;
227 /* Reconfigure for robustness */
228 if (epop->epo_reconfigure(enp) != 0) {
230 * We may have an inconsistent view of our advertised speed
237 EFSYS_PROBE1(fail1, efx_rc_t, rc);
245 __out uint32_t *maskp)
247 efx_port_t *epp = &(enp->en_port);
249 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
250 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
252 *maskp = epp->ep_lp_cap_mask;
255 __checkReturn efx_rc_t
258 __out uint32_t *ouip)
260 efx_port_t *epp = &(enp->en_port);
261 const efx_phy_ops_t *epop = epp->ep_epop;
263 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
264 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
266 return (epop->epo_oui_get(enp, ouip));
270 efx_phy_media_type_get(
272 __out efx_phy_media_type_t *typep)
274 efx_port_t *epp = &(enp->en_port);
276 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
277 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
279 if (epp->ep_module_type != EFX_PHY_MEDIA_INVALID)
280 *typep = epp->ep_module_type;
282 *typep = epp->ep_fixed_port_type;
285 __checkReturn efx_rc_t
286 efx_phy_module_get_info(
288 __in uint8_t dev_addr,
291 __out_bcount(len) uint8_t *data)
295 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
296 EFSYS_ASSERT(data != NULL);
298 if ((uint32_t)offset + len > 0xff) {
303 if ((rc = efx_mcdi_phy_module_get_info(enp, dev_addr,
304 offset, len, data)) != 0)
312 EFSYS_PROBE1(fail1, efx_rc_t, rc);
317 #if EFSYS_OPT_PHY_STATS
321 /* START MKCONFIG GENERATED PhyStatNamesBlock af9ffa24da3bc100 */
322 static const char * const __efx_phy_stat_name[] = {
371 /* END MKCONFIG GENERATED PhyStatNamesBlock */
376 __in efx_phy_stat_t type)
378 _NOTE(ARGUNUSED(enp))
379 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
380 EFSYS_ASSERT3U(type, <, EFX_PHY_NSTATS);
382 return (__efx_phy_stat_name[type]);
385 #endif /* EFSYS_OPT_NAMES */
387 __checkReturn efx_rc_t
388 efx_phy_stats_update(
390 __in efsys_mem_t *esmp,
391 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat)
393 efx_port_t *epp = &(enp->en_port);
394 const efx_phy_ops_t *epop = epp->ep_epop;
396 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
397 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
399 return (epop->epo_stats_update(enp, esmp, stat));
402 #endif /* EFSYS_OPT_PHY_STATS */
407 __checkReturn efx_rc_t
408 efx_bist_enable_offline(
411 efx_port_t *epp = &(enp->en_port);
412 const efx_phy_ops_t *epop = epp->ep_epop;
415 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
417 if (epop->epo_bist_enable_offline == NULL) {
422 if ((rc = epop->epo_bist_enable_offline(enp)) != 0)
430 EFSYS_PROBE1(fail1, efx_rc_t, rc);
436 __checkReturn efx_rc_t
439 __in efx_bist_type_t type)
441 efx_port_t *epp = &(enp->en_port);
442 const efx_phy_ops_t *epop = epp->ep_epop;
445 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
447 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
448 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
449 EFSYS_ASSERT3U(epp->ep_current_bist, ==, EFX_BIST_TYPE_UNKNOWN);
451 if (epop->epo_bist_start == NULL) {
456 if ((rc = epop->epo_bist_start(enp, type)) != 0)
459 epp->ep_current_bist = type;
466 EFSYS_PROBE1(fail1, efx_rc_t, rc);
471 __checkReturn efx_rc_t
474 __in efx_bist_type_t type,
475 __out efx_bist_result_t *resultp,
476 __out_opt uint32_t *value_maskp,
477 __out_ecount_opt(count) unsigned long *valuesp,
480 efx_port_t *epp = &(enp->en_port);
481 const efx_phy_ops_t *epop = epp->ep_epop;
484 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
486 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
487 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
488 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
490 EFSYS_ASSERT(epop->epo_bist_poll != NULL);
491 if (epop->epo_bist_poll == NULL) {
496 if ((rc = epop->epo_bist_poll(enp, type, resultp, value_maskp,
497 valuesp, count)) != 0)
505 EFSYS_PROBE1(fail1, efx_rc_t, rc);
513 __in efx_bist_type_t type)
515 efx_port_t *epp = &(enp->en_port);
516 const efx_phy_ops_t *epop = epp->ep_epop;
518 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
520 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
521 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
522 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
524 EFSYS_ASSERT(epop->epo_bist_stop != NULL);
526 if (epop->epo_bist_stop != NULL)
527 epop->epo_bist_stop(enp, type);
529 epp->ep_current_bist = EFX_BIST_TYPE_UNKNOWN;
532 #endif /* EFSYS_OPT_BIST */
537 efx_port_t *epp = &(enp->en_port);
539 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
543 epp->ep_adv_cap_mask = 0;
546 epp->ep_phy_type = 0;