2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
37 static __checkReturn efx_rc_t
45 #if EFSYS_OPT_RX_SCATTER
46 static __checkReturn efx_rc_t
47 siena_rx_scatter_enable(
49 __in unsigned int buf_size);
50 #endif /* EFSYS_OPT_RX_SCATTER */
52 #if EFSYS_OPT_RX_SCALE
53 static __checkReturn efx_rc_t
54 siena_rx_scale_mode_set(
56 __in efx_rx_hash_alg_t alg,
57 __in efx_rx_hash_type_t type,
58 __in boolean_t insert);
60 static __checkReturn efx_rc_t
61 siena_rx_scale_key_set(
63 __in_ecount(n) uint8_t *key,
66 static __checkReturn efx_rc_t
67 siena_rx_scale_tbl_set(
69 __in_ecount(n) unsigned int *table,
72 static __checkReturn uint32_t
75 __in efx_rx_hash_alg_t func,
76 __in uint8_t *buffer);
78 #endif /* EFSYS_OPT_RX_SCALE */
80 static __checkReturn efx_rc_t
81 siena_rx_prefix_pktlen(
84 __out uint16_t *lengthp);
89 __in_ecount(n) efsys_dma_addr_t *addrp,
92 __in unsigned int completed,
93 __in unsigned int added);
98 __in unsigned int added,
99 __inout unsigned int *pushedp);
101 #if EFSYS_OPT_RX_PACKED_STREAM
103 siena_rx_qps_update_credits(
104 __in efx_rxq_t *erp);
106 static __checkReturn uint8_t *
107 siena_rx_qps_packet_info(
109 __in uint8_t *buffer,
110 __in uint32_t buffer_length,
111 __in uint32_t current_offset,
112 __out uint16_t *lengthp,
113 __out uint32_t *next_offsetp,
114 __out uint32_t *timestamp);
117 static __checkReturn efx_rc_t
119 __in efx_rxq_t *erp);
123 __in efx_rxq_t *erp);
125 static __checkReturn efx_rc_t
128 __in unsigned int index,
129 __in unsigned int label,
130 __in efx_rxq_type_t type,
131 __in efsys_mem_t *esmp,
135 __in efx_rxq_t *erp);
139 __in efx_rxq_t *erp);
141 #endif /* EFSYS_OPT_SIENA */
145 static const efx_rx_ops_t __efx_rx_siena_ops = {
146 siena_rx_init, /* erxo_init */
147 siena_rx_fini, /* erxo_fini */
148 #if EFSYS_OPT_RX_SCATTER
149 siena_rx_scatter_enable, /* erxo_scatter_enable */
151 #if EFSYS_OPT_RX_SCALE
152 siena_rx_scale_mode_set, /* erxo_scale_mode_set */
153 siena_rx_scale_key_set, /* erxo_scale_key_set */
154 siena_rx_scale_tbl_set, /* erxo_scale_tbl_set */
155 siena_rx_prefix_hash, /* erxo_prefix_hash */
157 siena_rx_prefix_pktlen, /* erxo_prefix_pktlen */
158 siena_rx_qpost, /* erxo_qpost */
159 siena_rx_qpush, /* erxo_qpush */
160 #if EFSYS_OPT_RX_PACKED_STREAM
161 siena_rx_qps_update_credits, /* erxo_qps_update_credits */
162 siena_rx_qps_packet_info, /* erxo_qps_packet_info */
164 siena_rx_qflush, /* erxo_qflush */
165 siena_rx_qenable, /* erxo_qenable */
166 siena_rx_qcreate, /* erxo_qcreate */
167 siena_rx_qdestroy, /* erxo_qdestroy */
169 #endif /* EFSYS_OPT_SIENA */
171 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
172 static const efx_rx_ops_t __efx_rx_ef10_ops = {
173 ef10_rx_init, /* erxo_init */
174 ef10_rx_fini, /* erxo_fini */
175 #if EFSYS_OPT_RX_SCATTER
176 ef10_rx_scatter_enable, /* erxo_scatter_enable */
178 #if EFSYS_OPT_RX_SCALE
179 ef10_rx_scale_mode_set, /* erxo_scale_mode_set */
180 ef10_rx_scale_key_set, /* erxo_scale_key_set */
181 ef10_rx_scale_tbl_set, /* erxo_scale_tbl_set */
182 ef10_rx_prefix_hash, /* erxo_prefix_hash */
184 ef10_rx_prefix_pktlen, /* erxo_prefix_pktlen */
185 ef10_rx_qpost, /* erxo_qpost */
186 ef10_rx_qpush, /* erxo_qpush */
187 #if EFSYS_OPT_RX_PACKED_STREAM
188 ef10_rx_qps_update_credits, /* erxo_qps_update_credits */
189 ef10_rx_qps_packet_info, /* erxo_qps_packet_info */
191 ef10_rx_qflush, /* erxo_qflush */
192 ef10_rx_qenable, /* erxo_qenable */
193 ef10_rx_qcreate, /* erxo_qcreate */
194 ef10_rx_qdestroy, /* erxo_qdestroy */
196 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
199 __checkReturn efx_rc_t
201 __inout efx_nic_t *enp)
203 const efx_rx_ops_t *erxop;
206 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
207 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
209 if (!(enp->en_mod_flags & EFX_MOD_EV)) {
214 if (enp->en_mod_flags & EFX_MOD_RX) {
219 switch (enp->en_family) {
221 case EFX_FAMILY_SIENA:
222 erxop = &__efx_rx_siena_ops;
224 #endif /* EFSYS_OPT_SIENA */
226 #if EFSYS_OPT_HUNTINGTON
227 case EFX_FAMILY_HUNTINGTON:
228 erxop = &__efx_rx_ef10_ops;
230 #endif /* EFSYS_OPT_HUNTINGTON */
232 #if EFSYS_OPT_MEDFORD
233 case EFX_FAMILY_MEDFORD:
234 erxop = &__efx_rx_ef10_ops;
236 #endif /* EFSYS_OPT_MEDFORD */
244 if ((rc = erxop->erxo_init(enp)) != 0)
247 enp->en_erxop = erxop;
248 enp->en_mod_flags |= EFX_MOD_RX;
258 EFSYS_PROBE1(fail1, efx_rc_t, rc);
260 enp->en_erxop = NULL;
261 enp->en_mod_flags &= ~EFX_MOD_RX;
269 const efx_rx_ops_t *erxop = enp->en_erxop;
271 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
272 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
273 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
274 EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
276 erxop->erxo_fini(enp);
278 enp->en_erxop = NULL;
279 enp->en_mod_flags &= ~EFX_MOD_RX;
282 #if EFSYS_OPT_RX_SCATTER
283 __checkReturn efx_rc_t
284 efx_rx_scatter_enable(
286 __in unsigned int buf_size)
288 const efx_rx_ops_t *erxop = enp->en_erxop;
291 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
292 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
294 if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
300 EFSYS_PROBE1(fail1, efx_rc_t, rc);
303 #endif /* EFSYS_OPT_RX_SCATTER */
305 #if EFSYS_OPT_RX_SCALE
306 __checkReturn efx_rc_t
307 efx_rx_hash_support_get(
309 __out efx_rx_hash_support_t *supportp)
313 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
314 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
316 if (supportp == NULL) {
321 /* Report if resources are available to insert RX hash value */
322 *supportp = enp->en_hash_support;
327 EFSYS_PROBE1(fail1, efx_rc_t, rc);
332 __checkReturn efx_rc_t
333 efx_rx_scale_support_get(
335 __out efx_rx_scale_support_t *supportp)
339 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
340 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
342 if (supportp == NULL) {
347 /* Report if resources are available to support RSS */
348 *supportp = enp->en_rss_support;
353 EFSYS_PROBE1(fail1, efx_rc_t, rc);
358 __checkReturn efx_rc_t
359 efx_rx_scale_mode_set(
361 __in efx_rx_hash_alg_t alg,
362 __in efx_rx_hash_type_t type,
363 __in boolean_t insert)
365 const efx_rx_ops_t *erxop = enp->en_erxop;
368 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
369 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
371 if (erxop->erxo_scale_mode_set != NULL) {
372 if ((rc = erxop->erxo_scale_mode_set(enp, alg,
380 EFSYS_PROBE1(fail1, efx_rc_t, rc);
383 #endif /* EFSYS_OPT_RX_SCALE */
385 #if EFSYS_OPT_RX_SCALE
386 __checkReturn efx_rc_t
387 efx_rx_scale_key_set(
389 __in_ecount(n) uint8_t *key,
392 const efx_rx_ops_t *erxop = enp->en_erxop;
395 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
396 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
398 if ((rc = erxop->erxo_scale_key_set(enp, key, n)) != 0)
404 EFSYS_PROBE1(fail1, efx_rc_t, rc);
408 #endif /* EFSYS_OPT_RX_SCALE */
410 #if EFSYS_OPT_RX_SCALE
411 __checkReturn efx_rc_t
412 efx_rx_scale_tbl_set(
414 __in_ecount(n) unsigned int *table,
417 const efx_rx_ops_t *erxop = enp->en_erxop;
420 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
421 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
423 if ((rc = erxop->erxo_scale_tbl_set(enp, table, n)) != 0)
429 EFSYS_PROBE1(fail1, efx_rc_t, rc);
433 #endif /* EFSYS_OPT_RX_SCALE */
438 __in_ecount(n) efsys_dma_addr_t *addrp,
441 __in unsigned int completed,
442 __in unsigned int added)
444 efx_nic_t *enp = erp->er_enp;
445 const efx_rx_ops_t *erxop = enp->en_erxop;
447 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
449 erxop->erxo_qpost(erp, addrp, size, n, completed, added);
452 #if EFSYS_OPT_RX_PACKED_STREAM
455 efx_rx_qps_update_credits(
458 efx_nic_t *enp = erp->er_enp;
459 const efx_rx_ops_t *erxop = enp->en_erxop;
461 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
463 erxop->erxo_qps_update_credits(erp);
466 __checkReturn uint8_t *
467 efx_rx_qps_packet_info(
469 __in uint8_t *buffer,
470 __in uint32_t buffer_length,
471 __in uint32_t current_offset,
472 __out uint16_t *lengthp,
473 __out uint32_t *next_offsetp,
474 __out uint32_t *timestamp)
476 efx_nic_t *enp = erp->er_enp;
477 const efx_rx_ops_t *erxop = enp->en_erxop;
479 return (erxop->erxo_qps_packet_info(erp, buffer,
480 buffer_length, current_offset, lengthp,
481 next_offsetp, timestamp));
484 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
489 __in unsigned int added,
490 __inout unsigned int *pushedp)
492 efx_nic_t *enp = erp->er_enp;
493 const efx_rx_ops_t *erxop = enp->en_erxop;
495 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
497 erxop->erxo_qpush(erp, added, pushedp);
500 __checkReturn efx_rc_t
504 efx_nic_t *enp = erp->er_enp;
505 const efx_rx_ops_t *erxop = enp->en_erxop;
508 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
510 if ((rc = erxop->erxo_qflush(erp)) != 0)
516 EFSYS_PROBE1(fail1, efx_rc_t, rc);
525 efx_nic_t *enp = erp->er_enp;
526 const efx_rx_ops_t *erxop = enp->en_erxop;
528 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
530 erxop->erxo_qenable(erp);
533 __checkReturn efx_rc_t
536 __in unsigned int index,
537 __in unsigned int label,
538 __in efx_rxq_type_t type,
539 __in efsys_mem_t *esmp,
543 __deref_out efx_rxq_t **erpp)
545 const efx_rx_ops_t *erxop = enp->en_erxop;
549 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
550 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
552 /* Allocate an RXQ object */
553 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
560 erp->er_magic = EFX_RXQ_MAGIC;
562 erp->er_index = index;
563 erp->er_mask = n - 1;
566 if ((rc = erxop->erxo_qcreate(enp, index, label, type, esmp, n, id,
578 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
580 EFSYS_PROBE1(fail1, efx_rc_t, rc);
589 efx_nic_t *enp = erp->er_enp;
590 const efx_rx_ops_t *erxop = enp->en_erxop;
592 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
594 erxop->erxo_qdestroy(erp);
597 __checkReturn efx_rc_t
598 efx_pseudo_hdr_pkt_length_get(
600 __in uint8_t *buffer,
601 __out uint16_t *lengthp)
603 efx_nic_t *enp = erp->er_enp;
604 const efx_rx_ops_t *erxop = enp->en_erxop;
606 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
608 return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
611 #if EFSYS_OPT_RX_SCALE
612 __checkReturn uint32_t
613 efx_pseudo_hdr_hash_get(
615 __in efx_rx_hash_alg_t func,
616 __in uint8_t *buffer)
618 efx_nic_t *enp = erp->er_enp;
619 const efx_rx_ops_t *erxop = enp->en_erxop;
621 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
623 EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE);
624 return (erxop->erxo_prefix_hash(enp, func, buffer));
626 #endif /* EFSYS_OPT_RX_SCALE */
630 static __checkReturn efx_rc_t
637 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
639 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
640 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
641 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
642 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
643 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
644 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
645 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
647 /* Zero the RSS table */
648 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
650 EFX_ZERO_OWORD(oword);
651 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
652 index, &oword, B_TRUE);
655 #if EFSYS_OPT_RX_SCALE
656 /* The RSS key and indirection table are writable. */
657 enp->en_rss_support = EFX_RX_SCALE_EXCLUSIVE;
659 /* Hardware can insert RX hash with/without RSS */
660 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
661 #endif /* EFSYS_OPT_RX_SCALE */
666 #if EFSYS_OPT_RX_SCATTER
667 static __checkReturn efx_rc_t
668 siena_rx_scatter_enable(
670 __in unsigned int buf_size)
676 nbuf32 = buf_size / 32;
678 (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
679 ((buf_size % 32) != 0)) {
684 if (enp->en_rx_qcount > 0) {
689 /* Set scatter buffer size */
690 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
691 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
692 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
694 /* Enable scatter for packets not matching a filter */
695 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
696 EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
697 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
704 EFSYS_PROBE1(fail1, efx_rc_t, rc);
708 #endif /* EFSYS_OPT_RX_SCATTER */
711 #define EFX_RX_LFSR_HASH(_enp, _insert) \
715 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
716 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); \
717 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); \
718 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); \
719 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
720 (_insert) ? 1 : 0); \
721 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
723 if ((_enp)->en_family == EFX_FAMILY_SIENA) { \
724 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
726 EFX_SET_OWORD_FIELD(oword, \
727 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0); \
728 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
732 _NOTE(CONSTANTCONDITION) \
735 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp) \
739 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
740 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1); \
741 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, \
743 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, \
745 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
746 (_insert) ? 1 : 0); \
747 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
749 _NOTE(CONSTANTCONDITION) \
752 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc) \
756 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
757 EFX_SET_OWORD_FIELD(oword, \
758 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1); \
759 EFX_SET_OWORD_FIELD(oword, \
760 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
761 EFX_SET_OWORD_FIELD(oword, \
762 FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1); \
763 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
767 _NOTE(CONSTANTCONDITION) \
771 #if EFSYS_OPT_RX_SCALE
773 static __checkReturn efx_rc_t
774 siena_rx_scale_mode_set(
776 __in efx_rx_hash_alg_t alg,
777 __in efx_rx_hash_type_t type,
778 __in boolean_t insert)
783 case EFX_RX_HASHALG_LFSR:
784 EFX_RX_LFSR_HASH(enp, insert);
787 case EFX_RX_HASHALG_TOEPLITZ:
788 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert,
789 type & EFX_RX_HASH_IPV4,
790 type & EFX_RX_HASH_TCPIPV4);
792 EFX_RX_TOEPLITZ_IPV6_HASH(enp,
793 type & EFX_RX_HASH_IPV6,
794 type & EFX_RX_HASH_TCPIPV6,
811 EFSYS_PROBE1(fail1, efx_rc_t, rc);
813 EFX_RX_LFSR_HASH(enp, B_FALSE);
819 #if EFSYS_OPT_RX_SCALE
820 static __checkReturn efx_rc_t
821 siena_rx_scale_key_set(
823 __in_ecount(n) uint8_t *key,
833 /* Write Toeplitz IPv4 hash key */
834 EFX_ZERO_OWORD(oword);
835 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
836 offset > 0 && byte < n;
838 oword.eo_u8[offset - 1] = key[byte++];
840 EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
844 /* Verify Toeplitz IPv4 hash key */
845 EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
846 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
847 offset > 0 && byte < n;
849 if (oword.eo_u8[offset - 1] != key[byte++]) {
855 if ((enp->en_features & EFX_FEATURE_IPV6) == 0)
860 /* Write Toeplitz IPv6 hash key 3 */
861 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
862 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
863 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
864 offset > 0 && byte < n;
866 oword.eo_u8[offset - 1] = key[byte++];
868 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
870 /* Write Toeplitz IPv6 hash key 2 */
871 EFX_ZERO_OWORD(oword);
872 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
873 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
874 offset > 0 && byte < n;
876 oword.eo_u8[offset - 1] = key[byte++];
878 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
880 /* Write Toeplitz IPv6 hash key 1 */
881 EFX_ZERO_OWORD(oword);
882 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
883 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
884 offset > 0 && byte < n;
886 oword.eo_u8[offset - 1] = key[byte++];
888 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
892 /* Verify Toeplitz IPv6 hash key 3 */
893 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
894 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
895 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
896 offset > 0 && byte < n;
898 if (oword.eo_u8[offset - 1] != key[byte++]) {
904 /* Verify Toeplitz IPv6 hash key 2 */
905 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
906 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
907 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
908 offset > 0 && byte < n;
910 if (oword.eo_u8[offset - 1] != key[byte++]) {
916 /* Verify Toeplitz IPv6 hash key 1 */
917 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
918 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
919 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
920 offset > 0 && byte < n;
922 if (oword.eo_u8[offset - 1] != key[byte++]) {
938 EFSYS_PROBE1(fail1, efx_rc_t, rc);
944 #if EFSYS_OPT_RX_SCALE
945 static __checkReturn efx_rc_t
946 siena_rx_scale_tbl_set(
948 __in_ecount(n) unsigned int *table,
955 EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
956 EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
958 if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) {
963 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) {
966 /* Calculate the entry to place in the table */
967 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
969 EFSYS_PROBE2(table, int, index, uint32_t, byte);
971 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte);
973 /* Write the table */
974 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
975 index, &oword, B_TRUE);
978 for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) {
981 /* Determine if we're starting a new batch */
982 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
985 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL,
986 index, &oword, B_TRUE);
988 /* Verify the entry */
989 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) {
1000 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1007 * Falcon/Siena pseudo-header
1008 * --------------------------
1010 * Receive packets are prefixed by an optional 16 byte pseudo-header.
1011 * The pseudo-header is a byte array of one of the forms:
1013 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1014 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
1015 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
1018 * TT.TT.TT.TT Toeplitz hash (32-bit big-endian)
1019 * LL.LL LFSR hash (16-bit big-endian)
1022 #if EFSYS_OPT_RX_SCALE
1023 static __checkReturn uint32_t
1024 siena_rx_prefix_hash(
1025 __in efx_nic_t *enp,
1026 __in efx_rx_hash_alg_t func,
1027 __in uint8_t *buffer)
1029 _NOTE(ARGUNUSED(enp))
1032 case EFX_RX_HASHALG_TOEPLITZ:
1033 return ((buffer[12] << 24) |
1034 (buffer[13] << 16) |
1038 case EFX_RX_HASHALG_LFSR:
1039 return ((buffer[14] << 8) | buffer[15]);
1046 #endif /* EFSYS_OPT_RX_SCALE */
1048 static __checkReturn efx_rc_t
1049 siena_rx_prefix_pktlen(
1050 __in efx_nic_t *enp,
1051 __in uint8_t *buffer,
1052 __out uint16_t *lengthp)
1054 _NOTE(ARGUNUSED(enp, buffer, lengthp))
1056 /* Not supported by Falcon/Siena hardware */
1064 __in efx_rxq_t *erp,
1065 __in_ecount(n) efsys_dma_addr_t *addrp,
1067 __in unsigned int n,
1068 __in unsigned int completed,
1069 __in unsigned int added)
1073 unsigned int offset;
1076 /* The client driver must not overfill the queue */
1077 EFSYS_ASSERT3U(added - completed + n, <=,
1078 EFX_RXQ_LIMIT(erp->er_mask + 1));
1080 id = added & (erp->er_mask);
1081 for (i = 0; i < n; i++) {
1082 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
1083 unsigned int, id, efsys_dma_addr_t, addrp[i],
1086 EFX_POPULATE_QWORD_3(qword,
1087 FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
1088 FSF_AZ_RX_KER_BUF_ADDR_DW0,
1089 (uint32_t)(addrp[i] & 0xffffffff),
1090 FSF_AZ_RX_KER_BUF_ADDR_DW1,
1091 (uint32_t)(addrp[i] >> 32));
1093 offset = id * sizeof (efx_qword_t);
1094 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
1096 id = (id + 1) & (erp->er_mask);
1102 __in efx_rxq_t *erp,
1103 __in unsigned int added,
1104 __inout unsigned int *pushedp)
1106 efx_nic_t *enp = erp->er_enp;
1107 unsigned int pushed = *pushedp;
1112 /* All descriptors are pushed */
1115 /* Push the populated descriptors out */
1116 wptr = added & erp->er_mask;
1118 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
1120 /* Only write the third DWORD */
1121 EFX_POPULATE_DWORD_1(dword,
1122 EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
1124 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1125 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
1126 wptr, pushed & erp->er_mask);
1127 EFSYS_PIO_WRITE_BARRIER();
1128 EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
1129 erp->er_index, &dword, B_FALSE);
1132 #if EFSYS_OPT_RX_PACKED_STREAM
1134 siena_rx_qps_update_credits(
1135 __in efx_rxq_t *erp)
1137 /* Not supported by Siena hardware */
1142 siena_rx_qps_packet_info(
1143 __in efx_rxq_t *erp,
1144 __in uint8_t *buffer,
1145 __in uint32_t buffer_length,
1146 __in uint32_t current_offset,
1147 __out uint16_t *lengthp,
1148 __out uint32_t *next_offsetp,
1149 __out uint32_t *timestamp)
1151 /* Not supported by Siena hardware */
1156 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1158 static __checkReturn efx_rc_t
1160 __in efx_rxq_t *erp)
1162 efx_nic_t *enp = erp->er_enp;
1166 label = erp->er_index;
1168 /* Flush the queue */
1169 EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
1170 FRF_AZ_RX_FLUSH_DESCQ, label);
1171 EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
1178 __in efx_rxq_t *erp)
1180 efx_nic_t *enp = erp->er_enp;
1183 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1185 EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
1186 erp->er_index, &oword, B_TRUE);
1188 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
1189 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
1190 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
1192 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1193 erp->er_index, &oword, B_TRUE);
1196 static __checkReturn efx_rc_t
1198 __in efx_nic_t *enp,
1199 __in unsigned int index,
1200 __in unsigned int label,
1201 __in efx_rxq_type_t type,
1202 __in efsys_mem_t *esmp,
1205 __in efx_evq_t *eep,
1206 __in efx_rxq_t *erp)
1208 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1214 _NOTE(ARGUNUSED(esmp))
1216 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1217 (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
1218 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1219 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1221 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
1222 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
1224 if (!ISP2(n) || (n < EFX_RXQ_MINNDESCS) || (n > EFX_RXQ_MAXNDESCS)) {
1228 if (index >= encp->enc_rxq_limit) {
1232 for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);
1234 if ((1 << size) == (int)(n / EFX_RXQ_MINNDESCS))
1236 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1242 case EFX_RXQ_TYPE_DEFAULT:
1246 #if EFSYS_OPT_RX_SCATTER
1247 case EFX_RXQ_TYPE_SCATTER:
1248 if (enp->en_family < EFX_FAMILY_SIENA) {
1254 #endif /* EFSYS_OPT_RX_SCATTER */
1261 /* Set up the new descriptor queue */
1262 EFX_POPULATE_OWORD_7(oword,
1263 FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
1264 FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
1265 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
1266 FRF_AZ_RX_DESCQ_LABEL, label,
1267 FRF_AZ_RX_DESCQ_SIZE, size,
1268 FRF_AZ_RX_DESCQ_TYPE, 0,
1269 FRF_AZ_RX_DESCQ_JUMBO, jumbo);
1271 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1272 erp->er_index, &oword, B_TRUE);
1283 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1290 __in efx_rxq_t *erp)
1292 efx_nic_t *enp = erp->er_enp;
1295 EFSYS_ASSERT(enp->en_rx_qcount != 0);
1296 --enp->en_rx_qcount;
1298 /* Purge descriptor queue */
1299 EFX_ZERO_OWORD(oword);
1301 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1302 erp->er_index, &oword, B_TRUE);
1304 /* Free the RXQ object */
1305 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1310 __in efx_nic_t *enp)
1312 _NOTE(ARGUNUSED(enp))
1315 #endif /* EFSYS_OPT_SIENA */