2 * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written consent.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGE.
47 /***********************************************************/
48 /* CLC Call backs functions */
49 /***********************************************************/
50 /* CLC device structure */
53 extern uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr);
54 extern void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val);
56 /* mode - 0( LOW ) /1(HIGH)*/
57 extern uint8_t elink_cb_gpio_write(struct bnx2x_softc *sc,
59 uint8_t mode, uint8_t port);
60 extern uint8_t elink_cb_gpio_mult_write(struct bnx2x_softc *sc,
64 extern uint32_t elink_cb_gpio_read(struct bnx2x_softc *sc, uint16_t gpio_num, uint8_t port);
65 extern uint8_t elink_cb_gpio_int_write(struct bnx2x_softc *sc,
67 uint8_t mode, uint8_t port);
69 extern uint32_t elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param);
71 /* This function is called every 1024 bytes downloading of phy firmware.
72 Driver can use it to print to screen indication for download progress */
73 extern void elink_cb_download_progress(struct bnx2x_softc *sc, uint32_t cur, uint32_t total);
75 /* Each log type has its own parameters */
76 typedef enum elink_log_id {
77 ELINK_LOG_ID_UNQUAL_IO_MODULE = 0, /* uint8_t port, const char* vendor_name, const char* vendor_pn */
78 ELINK_LOG_ID_OVER_CURRENT = 1, /* uint8_t port */
79 ELINK_LOG_ID_PHY_UNINITIALIZED = 2, /* uint8_t port */
80 ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT= 3, /* No params */
81 ELINK_LOG_ID_NON_10G_MODULE = 4, /* uint8_t port */
84 typedef enum elink_status {
89 ELINK_STATUS_INVALID_IMAGE,
90 ELINK_OP_NOT_SUPPORTED = 122
92 extern void elink_cb_event_log(struct bnx2x_softc *sc, const elink_log_id_t log_id, ...);
93 extern void elink_cb_load_warpcore_microcode(void);
95 extern void elink_cb_notify_link_changed(struct bnx2x_softc *sc);
97 #define ELINK_EVENT_LOG_LEVEL_ERROR 1
98 #define ELINK_EVENT_LOG_LEVEL_WARNING 2
99 #define ELINK_EVENT_ID_SFP_UNQUALIFIED_MODULE 1
100 #define ELINK_EVENT_ID_SFP_POWER_FAULT 2
102 #define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
105 /***********************************************************/
107 /***********************************************************/
108 #define ELINK_DEFAULT_PHY_DEV_ADDR 3
109 #define ELINK_E2_DEFAULT_PHY_DEV_ADDR 5
112 #define DUPLEX_FULL 1
113 #define DUPLEX_HALF 2
115 #define ELINK_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
116 #define ELINK_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
117 #define ELINK_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
118 #define ELINK_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
119 #define ELINK_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
121 #define ELINK_NET_SERDES_IF_XFI 1
122 #define ELINK_NET_SERDES_IF_SFI 2
123 #define ELINK_NET_SERDES_IF_KR 3
124 #define ELINK_NET_SERDES_IF_DXGXS 4
126 #define ELINK_SPEED_AUTO_NEG 0
127 #define ELINK_SPEED_10 10
128 #define ELINK_SPEED_100 100
129 #define ELINK_SPEED_1000 1000
130 #define ELINK_SPEED_2500 2500
131 #define ELINK_SPEED_10000 10000
132 #define ELINK_SPEED_20000 20000
134 #define ELINK_I2C_DEV_ADDR_A0 0xa0
135 #define ELINK_I2C_DEV_ADDR_A2 0xa2
137 #define ELINK_SFP_EEPROM_PAGE_SIZE 16
138 #define ELINK_SFP_EEPROM_VENDOR_NAME_ADDR 0x14
139 #define ELINK_SFP_EEPROM_VENDOR_NAME_SIZE 16
140 #define ELINK_SFP_EEPROM_VENDOR_OUI_ADDR 0x25
141 #define ELINK_SFP_EEPROM_VENDOR_OUI_SIZE 3
142 #define ELINK_SFP_EEPROM_PART_NO_ADDR 0x28
143 #define ELINK_SFP_EEPROM_PART_NO_SIZE 16
144 #define ELINK_SFP_EEPROM_REVISION_ADDR 0x38
145 #define ELINK_SFP_EEPROM_REVISION_SIZE 4
146 #define ELINK_SFP_EEPROM_SERIAL_ADDR 0x44
147 #define ELINK_SFP_EEPROM_SERIAL_SIZE 16
148 #define ELINK_SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */
149 #define ELINK_SFP_EEPROM_DATE_SIZE 6
150 #define ELINK_SFP_EEPROM_DIAG_TYPE_ADDR 0x5c
151 #define ELINK_SFP_EEPROM_DIAG_TYPE_SIZE 1
152 #define ELINK_SFP_EEPROM_DIAG_ADDR_CHANGE_REQ (1<<2)
153 #define ELINK_SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e
154 #define ELINK_SFP_EEPROM_SFF_8472_COMP_SIZE 1
156 #define ELINK_SFP_EEPROM_A2_CHECKSUM_RANGE 0x5e
157 #define ELINK_SFP_EEPROM_A2_CC_DMI_ADDR 0x5f
159 #define ELINK_PWR_FLT_ERR_MSG_LEN 250
161 #define ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config) \
162 ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
163 #define ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config) \
164 (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
165 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
166 #define ELINK_SERDES_EXT_PHY_TYPE(ext_phy_config) \
167 ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
169 /* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
170 #define ELINK_SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1)
171 /* Single Media board contains single external phy */
172 #define ELINK_SINGLE_MEDIA(params) (params->num_phys == 2)
173 /* Dual Media board contains two external phy with different media */
174 #define ELINK_DUAL_MEDIA(params) (params->num_phys == 3)
176 #define ELINK_FW_PARAM_PHY_ADDR_MASK 0x000000FF
177 #define ELINK_FW_PARAM_PHY_TYPE_MASK 0x0000FF00
178 #define ELINK_FW_PARAM_MDIO_CTRL_MASK 0xFFFF0000
179 #define ELINK_FW_PARAM_MDIO_CTRL_OFFSET 16
180 #define ELINK_FW_PARAM_PHY_ADDR(fw_param) (fw_param & \
181 ELINK_FW_PARAM_PHY_ADDR_MASK)
182 #define ELINK_FW_PARAM_PHY_TYPE(fw_param) (fw_param & \
183 ELINK_FW_PARAM_PHY_TYPE_MASK)
184 #define ELINK_FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \
185 ELINK_FW_PARAM_MDIO_CTRL_MASK) >> \
186 ELINK_FW_PARAM_MDIO_CTRL_OFFSET)
187 #define ELINK_FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
188 (phy_addr | phy_type | mdio_access << ELINK_FW_PARAM_MDIO_CTRL_OFFSET)
191 #define ELINK_PFC_BRB_FULL_LB_XOFF_THRESHOLD 170
192 #define ELINK_PFC_BRB_FULL_LB_XON_THRESHOLD 250
194 #define ELINK_MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
196 #define ELINK_BMAC_CONTROL_RX_ENABLE 2
197 /***********************************************************/
199 /***********************************************************/
200 #define ELINK_INT_PHY 0
201 #define ELINK_EXT_PHY1 1
202 #define ELINK_EXT_PHY2 2
203 #define ELINK_MAX_PHYS 3
205 /* Same configuration is shared between the XGXS and the first external phy */
206 #define ELINK_LINK_CONFIG_SIZE (ELINK_MAX_PHYS - 1)
207 #define ELINK_LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == ELINK_INT_PHY) ? \
209 /***********************************************************/
210 /* elink_phy struct */
211 /* Defines the required arguments and function per phy */
212 /***********************************************************/
217 typedef uint8_t (*config_init_t)(struct elink_phy *phy, struct elink_params *params,
218 struct elink_vars *vars);
219 typedef uint8_t (*read_status_t)(struct elink_phy *phy, struct elink_params *params,
220 struct elink_vars *vars);
221 typedef void (*link_reset_t)(struct elink_phy *phy,
222 struct elink_params *params);
223 typedef void (*config_loopback_t)(struct elink_phy *phy,
224 struct elink_params *params);
225 typedef uint8_t (*format_fw_ver_t)(uint32_t raw, uint8_t *str, uint16_t *len);
226 typedef void (*hw_reset_t)(struct elink_phy *phy, struct elink_params *params);
227 typedef void (*set_link_led_t)(struct elink_phy *phy,
228 struct elink_params *params, uint8_t mode);
229 typedef void (*phy_specific_func_t)(struct elink_phy *phy,
230 struct elink_params *params, uint32_t action);
231 struct elink_reg_set {
240 /* Loaded during init */
242 uint8_t def_md_devad;
244 /* No Over-Current detection */
245 #define ELINK_FLAGS_NOC (1<<1)
246 /* Fan failure detection required */
247 #define ELINK_FLAGS_FAN_FAILURE_DET_REQ (1<<2)
248 /* Initialize first the XGXS and only then the phy itself */
249 #define ELINK_FLAGS_INIT_XGXS_FIRST (1<<3)
250 #define ELINK_FLAGS_WC_DUAL_MODE (1<<4)
251 #define ELINK_FLAGS_4_PORT_MODE (1<<5)
252 #define ELINK_FLAGS_REARM_LATCH_SIGNAL (1<<6)
253 #define ELINK_FLAGS_SFP_NOT_APPROVED (1<<7)
254 #define ELINK_FLAGS_MDC_MDIO_WA (1<<8)
255 #define ELINK_FLAGS_DUMMY_READ (1<<9)
256 #define ELINK_FLAGS_MDC_MDIO_WA_B0 (1<<10)
257 #define ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC (1<<11)
258 #define ELINK_FLAGS_TX_ERROR_CHECK (1<<12)
259 #define ELINK_FLAGS_EEE (1<<13)
260 #define ELINK_FLAGS_TEMPERATURE (1<<14)
261 #define ELINK_FLAGS_MDC_MDIO_WA_G (1<<15)
263 /* preemphasis values for the rx side */
264 uint16_t rx_preemphasis[4];
266 /* preemphasis values for the tx side */
267 uint16_t tx_preemphasis[4];
269 /* EMAC address for access MDIO */
273 #define ELINK_SUPPORTED_10baseT_Half (1<<0)
274 #define ELINK_SUPPORTED_10baseT_Full (1<<1)
275 #define ELINK_SUPPORTED_100baseT_Half (1<<2)
276 #define ELINK_SUPPORTED_100baseT_Full (1<<3)
277 #define ELINK_SUPPORTED_1000baseT_Full (1<<4)
278 #define ELINK_SUPPORTED_2500baseX_Full (1<<5)
279 #define ELINK_SUPPORTED_10000baseT_Full (1<<6)
280 #define ELINK_SUPPORTED_TP (1<<7)
281 #define ELINK_SUPPORTED_FIBRE (1<<8)
282 #define ELINK_SUPPORTED_Autoneg (1<<9)
283 #define ELINK_SUPPORTED_Pause (1<<10)
284 #define ELINK_SUPPORTED_Asym_Pause (1<<11)
285 #define ELINK_SUPPORTED_20000baseMLD2_Full (1<<21)
286 #define ELINK_SUPPORTED_20000baseKR2_Full (1<<22)
289 #define ELINK_ETH_PHY_UNSPECIFIED 0x0
290 #define ELINK_ETH_PHY_SFPP_10G_FIBER 0x1
291 #define ELINK_ETH_PHY_XFP_FIBER 0x2
292 #define ELINK_ETH_PHY_DA_TWINAX 0x3
293 #define ELINK_ETH_PHY_BASE_T 0x4
294 #define ELINK_ETH_PHY_SFP_1G_FIBER 0x5
295 #define ELINK_ETH_PHY_KR 0xf0
296 #define ELINK_ETH_PHY_CX4 0xf1
297 #define ELINK_ETH_PHY_NOT_PRESENT 0xff
299 /* The address in which version is located*/
302 uint16_t req_flow_ctrl;
304 uint16_t req_line_speed;
306 uint32_t speed_cap_mask;
310 /* Called per phy/port init, and it configures LASI, speed, autoneg,
311 duplex, flow control negotiation, etc. */
312 config_init_t config_init;
314 /* Called due to interrupt. It determines the link, speed */
315 read_status_t read_status;
317 /* Called when driver is unloading. Should reset the phy */
318 link_reset_t link_reset;
320 /* Set the loopback configuration for the phy */
321 config_loopback_t config_loopback;
323 /* Format the given raw number into str up to len */
324 format_fw_ver_t format_fw_ver;
326 /* Reset the phy (both ports) */
329 /* Set link led mode (on/off/oper)*/
330 set_link_led_t set_link_led;
332 /* PHY Specific tasks */
333 phy_specific_func_t phy_specific_func;
334 #define ELINK_DISABLE_TX 1
335 #define ELINK_ENABLE_TX 2
336 #define ELINK_PHY_INIT 3
339 /* Inputs parameters to the CLC */
340 struct elink_params {
344 /* Default / User Configuration */
345 uint8_t loopback_mode;
346 #define ELINK_LOOPBACK_NONE 0
347 #define ELINK_LOOPBACK_EMAC 1
348 #define ELINK_LOOPBACK_BMAC 2
349 #define ELINK_LOOPBACK_XGXS 3
350 #define ELINK_LOOPBACK_EXT_PHY 4
351 #define ELINK_LOOPBACK_EXT 5
352 #define ELINK_LOOPBACK_UMAC 6
353 #define ELINK_LOOPBACK_XMAC 7
355 /* Device parameters */
358 uint16_t req_duplex[ELINK_LINK_CONFIG_SIZE];
359 uint16_t req_flow_ctrl[ELINK_LINK_CONFIG_SIZE];
361 uint16_t req_line_speed[ELINK_LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
363 /* shmem parameters */
365 uint32_t shmem2_base;
366 uint32_t speed_cap_mask[ELINK_LINK_CONFIG_SIZE];
368 #define ELINK_SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
369 #define ELINK_SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
370 #define ELINK_SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
372 uint32_t lane_config;
374 /* Phy register parameter */
378 uint32_t feature_config_flags;
379 #define ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
380 #define ELINK_FEATURE_CONFIG_PFC_ENABLED (1<<1)
381 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
382 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3)
383 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC (1<<4)
384 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC (1<<5)
385 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC (1<<6)
386 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC (1<<7)
387 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX (1<<8)
388 #define ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED (1<<9)
389 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1<<10)
390 #define ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET (1<<11)
391 #define ELINK_FEATURE_CONFIG_IEEE_PHY_TEST (1<<12)
392 #define ELINK_FEATURE_CONFIG_MT_SUPPORT (1<<13)
393 #define ELINK_FEATURE_CONFIG_BOOT_FROM_SAN (1<<14)
395 /* Will be populated during common init */
396 struct elink_phy phy[ELINK_MAX_PHYS];
398 /* Will be populated during common init */
403 /* Used to configure the EEE Tx LPI timer, has several modes of
404 * operation, according to bits 29:28 -
405 * 2'b00: Timer will be configured by nvram, output will be the value
407 * 2'b01: Timer will be configured by nvram, output will be in
409 * 2'b10: bits 1:0 contain an nvram value which will be used instead
410 * of the one located in the nvram. Output will be that value.
411 * 2'b11: bits 19:0 contain the idle timer in microseconds; output
412 * will be in microseconds.
413 * Bits 31:30 should be 2'b11 in order for EEE to be enabled.
416 #define ELINK_EEE_MODE_NVRAM_BALANCED_TIME (0xa00)
417 #define ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME (0x100)
418 #define ELINK_EEE_MODE_NVRAM_LATENCY_TIME (0x6000)
419 #define ELINK_EEE_MODE_NVRAM_MASK (0x3)
420 #define ELINK_EEE_MODE_TIMER_MASK (0xfffff)
421 #define ELINK_EEE_MODE_OUTPUT_TIME (1<<28)
422 #define ELINK_EEE_MODE_OVERRIDE_NVRAM (1<<29)
423 #define ELINK_EEE_MODE_ENABLE_LPI (1<<30)
424 #define ELINK_EEE_MODE_ADV_LPI (1<<31)
426 uint16_t hw_led_mode; /* part of the hw_config read from the shmem */
427 uint32_t multi_phy_config;
429 /* Device pointer passed to all callback functions */
430 struct bnx2x_softc *sc;
431 uint16_t req_fc_auto_adv; /* Should be set to TX / BOTH when
432 req_flow_ctrl is set to AUTO */
434 #define ELINK_LINK_FLAGS_INT_DISABLED (1<<0)
435 #define ELINK_PHY_INITIALIZED (1<<1)
439 /* Output parameters */
442 #define PHY_XGXS_FLAG (1<<0)
443 #define PHY_SGMII_FLAG (1<<1)
444 #define PHY_PHYSICAL_LINK_FLAG (1<<2)
445 #define PHY_HALF_OPEN_CONN_FLAG (1<<3)
446 #define PHY_OVER_CURRENT_FLAG (1<<4)
447 #define PHY_SFP_TX_FAULT_FLAG (1<<5)
450 #define ELINK_MAC_TYPE_NONE 0
451 #define ELINK_MAC_TYPE_EMAC 1
452 #define ELINK_MAC_TYPE_BMAC 2
453 #define ELINK_MAC_TYPE_UMAC 3
454 #define ELINK_MAC_TYPE_XMAC 4
456 uint8_t phy_link_up; /* internal phy link indication */
465 /* The same definitions as the shmem parameter */
466 uint32_t link_status;
468 uint8_t fault_detected;
469 uint8_t check_kr2_recovery_cnt;
470 #define ELINK_CHECK_KR2_RECOVERY_CNT 5
471 uint16_t periodic_flags;
472 #define ELINK_PERIODIC_FLAGS_LINK_EVENT 0x0001
474 uint32_t aeu_int_mask;
475 uint8_t rx_tx_asic_rst;
476 uint8_t turn_to_run_wc_rt;
478 /* The same definitions as the shmem2 parameter */
479 uint32_t link_attr_sync;
482 /***********************************************************/
484 /***********************************************************/
485 elink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars);
487 /* Reset the link. Should be called when driver or interface goes down
488 Before calling phy firmware upgrade, the reset_ext_phy should be set
490 elink_status_t elink_lfa_reset(struct elink_params *params, struct elink_vars *vars);
491 /* elink_link_update should be called upon link interrupt */
492 elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars);
494 /* Reads the link_status from the shmem,
495 and update the link vars accordingly */
496 void elink_link_status_update(struct elink_params *input,
497 struct elink_vars *output);
500 Basically, the CLC takes care of the led for the link, but in case one needs
501 to set/unset the led unnaturally, set the "mode" to ELINK_LED_MODE_OPER to
502 blink the led, and ELINK_LED_MODE_OFF to set the led off.*/
503 elink_status_t elink_set_led(struct elink_params *params,
504 struct elink_vars *vars, uint8_t mode, uint32_t speed);
505 #define ELINK_LED_MODE_OFF 0
506 #define ELINK_LED_MODE_ON 1
507 #define ELINK_LED_MODE_OPER 2
508 #define ELINK_LED_MODE_FRONT_PANEL_OFF 3
510 /* elink_handle_module_detect_int should be called upon module detection
512 void elink_handle_module_detect_int(struct elink_params *params);
514 /* One-time initialization for external phy after power up */
515 elink_status_t elink_common_init_phy(struct bnx2x_softc *sc, uint32_t shmem_base_path[],
516 uint32_t shmem2_base_path[], uint32_t chip_id, uint8_t one_port_enabled);
518 void elink_hw_reset_phy(struct elink_params *params);
520 /* Check swap bit and adjust PHY order */
521 uint32_t elink_phy_selection(struct elink_params *params);
523 /* Probe the phys on board, and populate them in "params" */
524 elink_status_t elink_phy_probe(struct elink_params *params);
526 /* Checks if fan failure detection is required on one of the phys on board */
527 uint8_t elink_fan_failure_det_req(struct bnx2x_softc *sc, uint32_t shmem_base,
528 uint32_t shmem2_base, uint8_t port);
530 /* Open / close the gate between the NIG and the BRB */
531 void elink_set_rx_filter(struct elink_params *params, uint8_t en);
535 /* Number of maximum COS per chip */
536 #define ELINK_DCBX_E2E3_MAX_NUM_COS (2)
537 #define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0 (6)
538 #define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 (3)
539 #define ELINK_DCBX_E3B0_MAX_NUM_COS ( \
540 ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0, \
541 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1))
543 #define ELINK_DCBX_MAX_NUM_COS ( \
544 ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS, \
545 ELINK_DCBX_E2E3_MAX_NUM_COS))
547 /* PFC port configuration params */
548 struct elink_nig_brb_pfc_port_params {
550 uint32_t pause_enable;
551 uint32_t llfc_out_en;
552 uint32_t llfc_enable;
553 uint32_t pkt_priority_to_cos;
554 uint8_t num_of_rx_cos_priority_mask;
555 uint32_t rx_cos_priority_mask[ELINK_DCBX_MAX_NUM_COS];
556 uint32_t llfc_high_priority_classes;
557 uint32_t llfc_low_priority_classes;
561 /* ETS port configuration params */
562 struct elink_ets_bw_params {
566 struct elink_ets_sp_params {
568 * valid values are 0 - 5. 0 is highest strict priority.
569 * There can't be two COS's with the same pri.
574 enum elink_cos_state {
575 elink_cos_state_strict = 0,
576 elink_cos_state_bw = 1,
579 struct elink_ets_cos_params {
580 enum elink_cos_state state ;
582 struct elink_ets_bw_params bw_params;
583 struct elink_ets_sp_params sp_params;
587 struct elink_ets_params {
588 uint8_t num_of_cos; /* Number of valid COS entries*/
589 struct elink_ets_cos_params cos[ELINK_DCBX_MAX_NUM_COS];
592 /* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
593 * when link is already up
595 elink_status_t elink_update_pfc(struct elink_params *params,
596 struct elink_vars *vars,
597 struct elink_nig_brb_pfc_port_params *pfc_params);
599 void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,
600 uint32_t chip_id, uint32_t shmem_base, uint32_t shmem2_base,
603 void elink_period_func(struct elink_params *params, struct elink_vars *vars);
605 void elink_enable_pmd_tx(struct elink_params *params);