1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
9 #define ENA_ADMIN_EXTRA_PROPERTIES_STRING_LEN 32
10 #define ENA_ADMIN_EXTRA_PROPERTIES_COUNT 32
12 enum ena_admin_aq_opcode {
13 ENA_ADMIN_CREATE_SQ = 1,
14 ENA_ADMIN_DESTROY_SQ = 2,
15 ENA_ADMIN_CREATE_CQ = 3,
16 ENA_ADMIN_DESTROY_CQ = 4,
17 ENA_ADMIN_GET_FEATURE = 8,
18 ENA_ADMIN_SET_FEATURE = 9,
19 ENA_ADMIN_GET_STATS = 11,
22 enum ena_admin_aq_completion_status {
23 ENA_ADMIN_SUCCESS = 0,
24 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1,
25 ENA_ADMIN_BAD_OPCODE = 2,
26 ENA_ADMIN_UNSUPPORTED_OPCODE = 3,
27 ENA_ADMIN_MALFORMED_REQUEST = 4,
28 /* Additional status is provided in ACQ entry extended_status */
29 ENA_ADMIN_ILLEGAL_PARAMETER = 5,
30 ENA_ADMIN_UNKNOWN_ERROR = 6,
31 ENA_ADMIN_RESOURCE_BUSY = 7,
34 enum ena_admin_aq_feature_id {
35 ENA_ADMIN_DEVICE_ATTRIBUTES = 1,
36 ENA_ADMIN_MAX_QUEUES_NUM = 2,
37 ENA_ADMIN_HW_HINTS = 3,
39 ENA_ADMIN_EXTRA_PROPERTIES_STRINGS = 5,
40 ENA_ADMIN_EXTRA_PROPERTIES_FLAGS = 6,
41 ENA_ADMIN_MAX_QUEUES_EXT = 7,
42 ENA_ADMIN_RSS_HASH_FUNCTION = 10,
43 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11,
44 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG = 12,
46 ENA_ADMIN_RSS_HASH_INPUT = 18,
47 ENA_ADMIN_INTERRUPT_MODERATION = 20,
48 ENA_ADMIN_AENQ_CONFIG = 26,
49 ENA_ADMIN_LINK_CONFIG = 27,
50 ENA_ADMIN_HOST_ATTR_CONFIG = 28,
51 ENA_ADMIN_FEATURES_OPCODE_NUM = 32,
54 enum ena_admin_placement_policy_type {
55 /* descriptors and headers are in host memory */
56 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1,
57 /* descriptors and headers are in device memory (a.k.a Low Latency
60 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3,
63 enum ena_admin_link_types {
64 ENA_ADMIN_LINK_SPEED_1G = 0x1,
65 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2,
66 ENA_ADMIN_LINK_SPEED_5G = 0x4,
67 ENA_ADMIN_LINK_SPEED_10G = 0x8,
68 ENA_ADMIN_LINK_SPEED_25G = 0x10,
69 ENA_ADMIN_LINK_SPEED_40G = 0x20,
70 ENA_ADMIN_LINK_SPEED_50G = 0x40,
71 ENA_ADMIN_LINK_SPEED_100G = 0x80,
72 ENA_ADMIN_LINK_SPEED_200G = 0x100,
73 ENA_ADMIN_LINK_SPEED_400G = 0x200,
76 enum ena_admin_completion_policy_type {
77 /* completion queue entry for each sq descriptor */
78 ENA_ADMIN_COMPLETION_POLICY_DESC = 0,
79 /* completion queue entry upon request in sq descriptor */
80 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1,
81 /* current queue head pointer is updated in OS memory upon sq
84 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2,
85 /* current queue head pointer is updated in OS memory for each sq
88 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3,
91 /* basic stats return ena_admin_basic_stats while extanded stats return a
92 * buffer (string format) with additional statistics per queue and per
95 enum ena_admin_get_stats_type {
96 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0,
97 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1,
100 enum ena_admin_get_stats_scope {
101 ENA_ADMIN_SPECIFIC_QUEUE = 0,
102 ENA_ADMIN_ETH_TRAFFIC = 1,
105 struct ena_admin_aq_common_desc {
111 /* as appears in ena_admin_aq_opcode */
115 * 1 : ctrl_data - control buffer address valid
116 * 2 : ctrl_data_indirect - control buffer address
117 * points to list of pages with addresses of control
124 /* used in ena_admin_aq_entry. Can point directly to control data, or to a
125 * page list chunk. Used also at the end of indirect mode page list chunks,
128 struct ena_admin_ctrl_buff_info {
131 struct ena_common_mem_addr address;
134 struct ena_admin_sq {
138 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
145 struct ena_admin_aq_entry {
146 struct ena_admin_aq_common_desc aq_common_descriptor;
149 uint32_t inline_data_w1[3];
151 struct ena_admin_ctrl_buff_info control_buffer;
154 uint32_t inline_data_w4[12];
157 struct ena_admin_acq_common_desc {
158 /* command identifier to associate it with the aq descriptor
171 uint16_t extended_status;
173 /* indicates to the driver which AQ entry has been consumed by the
174 * device and could be reused
176 uint16_t sq_head_indx;
179 struct ena_admin_acq_entry {
180 struct ena_admin_acq_common_desc acq_common_descriptor;
182 uint32_t response_specific_data[14];
185 struct ena_admin_aq_create_sq_cmd {
186 struct ena_admin_aq_common_desc aq_common_descriptor;
188 /* 4:0 : reserved0_w1
189 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx
193 uint8_t reserved8_w1;
195 /* 3:0 : placement_policy - Describing where the SQ
196 * descriptor ring and the SQ packet headers reside:
197 * 0x1 - descriptors and headers are in OS memory,
198 * 0x3 - descriptors and headers in device memory
199 * (a.k.a Low Latency Queue)
200 * 6:4 : completion_policy - Describing what policy
201 * to use for generation completion entry (cqe) in
202 * the CQ associated with this SQ: 0x0 - cqe for each
203 * sq descriptor, 0x1 - cqe upon request in sq
204 * descriptor, 0x2 - current queue head pointer is
205 * updated in OS memory upon sq descriptor request
206 * 0x3 - current queue head pointer is updated in OS
207 * memory for each sq descriptor
212 /* 0 : is_physically_contiguous - Described if the
213 * queue ring memory is allocated in physical
214 * contiguous pages or split.
215 * 7:1 : reserved17_w1
219 /* associated completion queue id. This CQ must be created prior to
224 /* submission queue depth in entries */
227 /* SQ physical base address in OS memory. This field should not be
228 * used for Low Latency queues. Has to be page aligned.
230 struct ena_common_mem_addr sq_ba;
232 /* specifies queue head writeback location in OS memory. Valid if
233 * completion_policy is set to completion_policy_head_on_demand or
234 * completion_policy_head. Has to be cache aligned
236 struct ena_common_mem_addr sq_head_writeback;
238 uint32_t reserved0_w7;
240 uint32_t reserved0_w8;
243 enum ena_admin_sq_direction {
244 ENA_ADMIN_SQ_DIRECTION_TX = 1,
245 ENA_ADMIN_SQ_DIRECTION_RX = 2,
248 struct ena_admin_acq_create_sq_resp_desc {
249 struct ena_admin_acq_common_desc acq_common_desc;
255 /* queue doorbell address as an offset to PCIe MMIO REG BAR */
256 uint32_t sq_doorbell_offset;
258 /* low latency queue ring base address as an offset to PCIe MMIO
261 uint32_t llq_descriptors_offset;
263 /* low latency queue headers' memory as an offset to PCIe MMIO
266 uint32_t llq_headers_offset;
269 struct ena_admin_aq_destroy_sq_cmd {
270 struct ena_admin_aq_common_desc aq_common_descriptor;
272 struct ena_admin_sq sq;
275 struct ena_admin_acq_destroy_sq_resp_desc {
276 struct ena_admin_acq_common_desc acq_common_desc;
279 struct ena_admin_aq_create_cq_cmd {
280 struct ena_admin_aq_common_desc aq_common_descriptor;
283 * 5 : interrupt_mode_enabled - if set, cq operates
284 * in interrupt mode, otherwise - polling
289 /* 4:0 : cq_entry_size_words - size of CQ entry in
290 * 32-bit words, valid values: 4, 8.
295 /* completion queue depth in # of entries. must be power of 2 */
298 /* msix vector assigned to this cq */
299 uint32_t msix_vector;
301 /* cq physical base address in OS memory. CQ must be physically
304 struct ena_common_mem_addr cq_ba;
307 struct ena_admin_acq_create_cq_resp_desc {
308 struct ena_admin_acq_common_desc acq_common_desc;
312 /* actual cq depth in number of entries */
313 uint16_t cq_actual_depth;
315 uint32_t numa_node_register_offset;
317 uint32_t cq_head_db_register_offset;
319 uint32_t cq_interrupt_unmask_register_offset;
322 struct ena_admin_aq_destroy_cq_cmd {
323 struct ena_admin_aq_common_desc aq_common_descriptor;
330 struct ena_admin_acq_destroy_cq_resp_desc {
331 struct ena_admin_acq_common_desc acq_common_desc;
334 /* ENA AQ Get Statistics command. Extended statistics are placed in control
335 * buffer pointed by AQ entry
337 struct ena_admin_aq_get_stats_cmd {
338 struct ena_admin_aq_common_desc aq_common_descriptor;
341 /* command specific inline data */
342 uint32_t inline_data_w1[3];
344 struct ena_admin_ctrl_buff_info control_buffer;
347 /* stats type as defined in enum ena_admin_get_stats_type */
350 /* stats scope defined in enum ena_admin_get_stats_scope */
355 /* queue id. used when scope is specific_queue */
358 /* device id, value 0xFFFF means mine. only privileged device can get
359 * stats of other device
364 /* Basic Statistics Command. */
365 struct ena_admin_basic_stats {
366 uint32_t tx_bytes_low;
368 uint32_t tx_bytes_high;
370 uint32_t tx_pkts_low;
372 uint32_t tx_pkts_high;
374 uint32_t rx_bytes_low;
376 uint32_t rx_bytes_high;
378 uint32_t rx_pkts_low;
380 uint32_t rx_pkts_high;
382 uint32_t rx_drops_low;
384 uint32_t rx_drops_high;
386 uint32_t tx_drops_low;
388 uint32_t tx_drops_high;
391 struct ena_admin_acq_get_stats_resp {
392 struct ena_admin_acq_common_desc acq_common_desc;
394 struct ena_admin_basic_stats basic_stats;
397 struct ena_admin_get_set_feature_common_desc {
398 /* 1:0 : select - 0x1 - current value; 0x3 - default
404 /* as appears in ena_admin_aq_feature_id */
407 /* The driver specifies the max feature version it supports and the
408 * device responds with the currently supported feature version. The
409 * field is zero based
411 uint8_t feature_version;
416 struct ena_admin_device_attr_feature_desc {
419 uint32_t device_version;
421 /* bitmap of ena_admin_aq_feature_id */
422 uint32_t supported_features;
426 /* Indicates how many bits are used physical address access. */
427 uint32_t phys_addr_width;
429 /* Indicates how many bits are used virtual address access. */
430 uint32_t virt_addr_width;
432 /* unicast MAC address (in Network byte order) */
435 uint8_t reserved7[2];
440 enum ena_admin_llq_header_location {
441 /* header is in descriptor list */
442 ENA_ADMIN_INLINE_HEADER = 1,
443 /* header in a separate ring, implies 16B descriptor list entry */
444 ENA_ADMIN_HEADER_RING = 2,
447 enum ena_admin_llq_ring_entry_size {
448 ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1,
449 ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2,
450 ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4,
453 enum ena_admin_llq_num_descs_before_header {
454 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0,
455 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1,
456 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2,
457 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4,
458 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8,
461 /* packet descriptor list entry always starts with one or more descriptors,
462 * followed by a header. The rest of the descriptors are located in the
463 * beginning of the subsequent entry. Stride refers to how the rest of the
464 * descriptors are placed. This field is relevant only for inline header
467 enum ena_admin_llq_stride_ctrl {
468 ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1,
469 ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2,
472 enum ena_admin_accel_mode_feat {
473 ENA_ADMIN_DISABLE_META_CACHING = 0,
474 ENA_ADMIN_LIMIT_TX_BURST = 1,
477 struct ena_admin_accel_mode_get {
478 /* bit field of enum ena_admin_accel_mode_feat */
479 uint16_t supported_flags;
481 /* maximum burst size between two doorbells. The size is in bytes */
482 uint16_t max_tx_burst_size;
485 struct ena_admin_accel_mode_set {
486 /* bit field of enum ena_admin_accel_mode_feat */
487 uint16_t enabled_flags;
492 struct ena_admin_accel_mode_req {
496 struct ena_admin_accel_mode_get get;
498 struct ena_admin_accel_mode_set set;
502 struct ena_admin_feature_llq_desc {
503 uint32_t max_llq_num;
505 uint32_t max_llq_depth;
507 /* specify the header locations the device supports. bitfield of
508 * enum ena_admin_llq_header_location.
510 uint16_t header_location_ctrl_supported;
512 /* the header location the driver selected to use. */
513 uint16_t header_location_ctrl_enabled;
515 /* if inline header is specified - this is the size of descriptor
516 * list entry. If header in a separate ring is specified - this is
517 * the size of header ring entry. bitfield of enum
518 * ena_admin_llq_ring_entry_size. specify the entry sizes the device
521 uint16_t entry_size_ctrl_supported;
523 /* the entry size the driver selected to use. */
524 uint16_t entry_size_ctrl_enabled;
526 /* valid only if inline header is specified. First entry associated
527 * with the packet includes descriptors and header. Rest of the
528 * entries occupied by descriptors. This parameter defines the max
529 * number of descriptors precedding the header in the first entry.
530 * The field is bitfield of enum
531 * ena_admin_llq_num_descs_before_header and specify the values the
534 uint16_t desc_num_before_header_supported;
536 /* the desire field the driver selected to use */
537 uint16_t desc_num_before_header_enabled;
539 /* valid only if inline was chosen. bitfield of enum
540 * ena_admin_llq_stride_ctrl
542 uint16_t descriptors_stride_ctrl_supported;
544 /* the stride control the driver selected to use */
545 uint16_t descriptors_stride_ctrl_enabled;
550 /* accelerated low latency queues requirement. Driver needs to
551 * support those requirements in order to use accelerated LLQ
553 struct ena_admin_accel_mode_req accel_mode;
556 struct ena_admin_queue_ext_feature_fields {
557 uint32_t max_tx_sq_num;
559 uint32_t max_tx_cq_num;
561 uint32_t max_rx_sq_num;
563 uint32_t max_rx_cq_num;
565 uint32_t max_tx_sq_depth;
567 uint32_t max_tx_cq_depth;
569 uint32_t max_rx_sq_depth;
571 uint32_t max_rx_cq_depth;
573 uint32_t max_tx_header_size;
575 /* Maximum Descriptors number, including meta descriptor, allowed for
578 uint16_t max_per_packet_tx_descs;
580 /* Maximum Descriptors number allowed for a single Rx packet */
581 uint16_t max_per_packet_rx_descs;
584 struct ena_admin_queue_feature_desc {
587 uint32_t max_sq_depth;
591 uint32_t max_cq_depth;
593 uint32_t max_legacy_llq_num;
595 uint32_t max_legacy_llq_depth;
597 uint32_t max_header_size;
599 /* Maximum Descriptors number, including meta descriptor, allowed for
602 uint16_t max_packet_tx_descs;
604 /* Maximum Descriptors number allowed for a single Rx packet */
605 uint16_t max_packet_rx_descs;
608 struct ena_admin_set_feature_mtu_desc {
613 struct ena_admin_get_extra_properties_strings_desc {
617 struct ena_admin_get_extra_properties_flags_desc {
621 struct ena_admin_set_feature_host_attr_desc {
622 /* host OS info base address in OS memory. host info is 4KB of
623 * physically contiguous
625 struct ena_common_mem_addr os_info_ba;
627 /* host debug area base address in OS memory. debug area must be
628 * physically contiguous
630 struct ena_common_mem_addr debug_ba;
632 /* debug area size */
633 uint32_t debug_area_size;
636 struct ena_admin_feature_intr_moder_desc {
637 /* interrupt delay granularity in usec */
638 uint16_t intr_delay_resolution;
643 struct ena_admin_get_feature_link_desc {
644 /* Link speed in Mb */
647 /* bit field of enum ena_admin_link types */
651 * 1 : duplex - Full Duplex
657 struct ena_admin_feature_aenq_desc {
658 /* bitmask for AENQ groups the device can report */
659 uint32_t supported_groups;
661 /* bitmask for AENQ groups to report */
662 uint32_t enabled_groups;
665 struct ena_admin_feature_offload_desc {
666 /* 0 : TX_L3_csum_ipv4
667 * 1 : TX_L4_ipv4_csum_part - The checksum field
668 * should be initialized with pseudo header checksum
669 * 2 : TX_L4_ipv4_csum_full
670 * 3 : TX_L4_ipv6_csum_part - The checksum field
671 * should be initialized with pseudo header checksum
672 * 4 : TX_L4_ipv6_csum_full
679 /* Receive side supported stateless offload
680 * 0 : RX_L3_csum_ipv4 - IPv4 checksum
681 * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum
682 * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum
683 * 3 : RX_hash - Hash calculation
685 uint32_t rx_supported;
690 enum ena_admin_hash_functions {
691 ENA_ADMIN_TOEPLITZ = 1,
695 struct ena_admin_feature_rss_flow_hash_control {
703 struct ena_admin_feature_rss_flow_hash_function {
704 /* 7:0 : funcs - bitmask of ena_admin_hash_functions */
705 uint32_t supported_func;
707 /* 7:0 : selected_func - bitmask of
708 * ena_admin_hash_functions
710 uint32_t selected_func;
716 /* RSS flow hash protocols */
717 enum ena_admin_flow_hash_proto {
718 ENA_ADMIN_RSS_TCP4 = 0,
719 ENA_ADMIN_RSS_UDP4 = 1,
720 ENA_ADMIN_RSS_TCP6 = 2,
721 ENA_ADMIN_RSS_UDP6 = 3,
722 ENA_ADMIN_RSS_IP4 = 4,
723 ENA_ADMIN_RSS_IP6 = 5,
724 ENA_ADMIN_RSS_IP4_FRAG = 6,
725 ENA_ADMIN_RSS_NOT_IP = 7,
726 /* TCPv6 with extension header */
727 ENA_ADMIN_RSS_TCP6_EX = 8,
728 /* IPv6 with extension header */
729 ENA_ADMIN_RSS_IP6_EX = 9,
730 ENA_ADMIN_RSS_PROTO_NUM = 16,
733 /* RSS flow hash fields */
734 enum ena_admin_flow_hash_fields {
735 /* Ethernet Dest Addr */
736 ENA_ADMIN_RSS_L2_DA = BIT(0),
737 /* Ethernet Src Addr */
738 ENA_ADMIN_RSS_L2_SA = BIT(1),
739 /* ipv4/6 Dest Addr */
740 ENA_ADMIN_RSS_L3_DA = BIT(2),
741 /* ipv4/6 Src Addr */
742 ENA_ADMIN_RSS_L3_SA = BIT(3),
743 /* tcp/udp Dest Port */
744 ENA_ADMIN_RSS_L4_DP = BIT(4),
745 /* tcp/udp Src Port */
746 ENA_ADMIN_RSS_L4_SP = BIT(5),
749 struct ena_admin_proto_input {
750 /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */
756 struct ena_admin_feature_rss_hash_control {
757 struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM];
759 struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM];
761 struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM];
763 struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM];
766 struct ena_admin_feature_rss_flow_hash_input {
767 /* supported hash input sorting
768 * 1 : L3_sort - support swap L3 addresses if DA is
770 * 2 : L4_sort - support swap L4 ports if DP smaller
773 uint16_t supported_input_sort;
775 /* enabled hash input sorting
776 * 1 : enable_L3_sort - enable swap L3 addresses if
778 * 2 : enable_L4_sort - enable swap L4 ports if DP
781 uint16_t enabled_input_sort;
784 enum ena_admin_os_type {
785 ENA_ADMIN_OS_LINUX = 1,
786 ENA_ADMIN_OS_WIN = 2,
787 ENA_ADMIN_OS_DPDK = 3,
788 ENA_ADMIN_OS_FREEBSD = 4,
789 ENA_ADMIN_OS_IPXE = 5,
790 ENA_ADMIN_OS_ESXI = 6,
791 ENA_ADMIN_OS_GROUPS_NUM = 6,
794 struct ena_admin_host_info {
795 /* defined in enum ena_admin_os_type */
798 /* os distribution string format */
799 uint8_t os_dist_str[128];
801 /* OS distribution numeric format */
804 /* kernel version string format */
805 uint8_t kernel_ver_str[32];
807 /* Kernel version numeric format */
813 * 31:24 : module_type
815 uint32_t driver_version;
817 /* features bitmap */
818 uint32_t supported_network_features[2];
820 /* ENA spec version of driver */
821 uint16_t ena_spec_version;
823 /* ENA device's Bus, Device and Function
835 /* 0 : mutable_rss_table_size
837 * 2 : interrupt_moderation
838 * 3 : map_rx_buf_bidirectional
841 uint32_t driver_supported_features;
844 struct ena_admin_rss_ind_table_entry {
850 struct ena_admin_feature_rss_ind_table {
851 /* min supported table size (2^min_size) */
854 /* max supported table size (2^max_size) */
857 /* table size (2^size) */
860 /* 0 : one_entry_update - The ENA device supports
861 * setting a single RSS table entry
867 /* index of the inline entry. 0xFFFFFFFF means invalid */
868 uint32_t inline_index;
870 /* used for updating single entry, ignored when setting the entire
871 * table through the control buffer.
873 struct ena_admin_rss_ind_table_entry inline_entry;
876 /* When hint value is 0, driver should use it's own predefined value */
877 struct ena_admin_ena_hw_hints {
879 uint16_t mmio_read_timeout;
882 uint16_t driver_watchdog_timeout;
884 /* Per packet tx completion timeout. value in ms */
885 uint16_t missing_tx_completion_timeout;
887 uint16_t missed_tx_completion_count_threshold_to_reset;
890 uint16_t admin_completion_tx_timeout;
892 uint16_t netdev_wd_timeout;
894 uint16_t max_tx_sgl_size;
896 uint16_t max_rx_sgl_size;
898 uint16_t reserved[8];
901 struct ena_admin_get_feat_cmd {
902 struct ena_admin_aq_common_desc aq_common_descriptor;
904 struct ena_admin_ctrl_buff_info control_buffer;
906 struct ena_admin_get_set_feature_common_desc feat_common;
911 struct ena_admin_queue_ext_feature_desc {
915 uint8_t reserved1[3];
918 struct ena_admin_queue_ext_feature_fields max_queue_ext;
924 struct ena_admin_get_feat_resp {
925 struct ena_admin_acq_common_desc acq_common_desc;
930 struct ena_admin_device_attr_feature_desc dev_attr;
932 struct ena_admin_feature_llq_desc llq;
934 struct ena_admin_queue_feature_desc max_queue;
936 struct ena_admin_queue_ext_feature_desc max_queue_ext;
938 struct ena_admin_feature_aenq_desc aenq;
940 struct ena_admin_get_feature_link_desc link;
942 struct ena_admin_feature_offload_desc offload;
944 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
946 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
948 struct ena_admin_feature_rss_ind_table ind_table;
950 struct ena_admin_feature_intr_moder_desc intr_moderation;
952 struct ena_admin_ena_hw_hints hw_hints;
954 struct ena_admin_get_extra_properties_strings_desc extra_properties_strings;
956 struct ena_admin_get_extra_properties_flags_desc extra_properties_flags;
960 struct ena_admin_set_feat_cmd {
961 struct ena_admin_aq_common_desc aq_common_descriptor;
963 struct ena_admin_ctrl_buff_info control_buffer;
965 struct ena_admin_get_set_feature_common_desc feat_common;
971 struct ena_admin_set_feature_mtu_desc mtu;
973 /* host attributes */
974 struct ena_admin_set_feature_host_attr_desc host_attr;
976 /* AENQ configuration */
977 struct ena_admin_feature_aenq_desc aenq;
979 /* rss flow hash function */
980 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
982 /* rss flow hash input */
983 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
985 /* rss indirection table */
986 struct ena_admin_feature_rss_ind_table ind_table;
988 /* LLQ configuration */
989 struct ena_admin_feature_llq_desc llq;
993 struct ena_admin_set_feat_resp {
994 struct ena_admin_acq_common_desc acq_common_desc;
1001 struct ena_admin_aenq_common_desc {
1007 * 7:1 : reserved - MBZ
1011 uint8_t reserved1[3];
1013 uint32_t timestamp_low;
1015 uint32_t timestamp_high;
1018 /* asynchronous event notification groups */
1019 enum ena_admin_aenq_group {
1020 ENA_ADMIN_LINK_CHANGE = 0,
1021 ENA_ADMIN_FATAL_ERROR = 1,
1022 ENA_ADMIN_WARNING = 2,
1023 ENA_ADMIN_NOTIFICATION = 3,
1024 ENA_ADMIN_KEEP_ALIVE = 4,
1025 ENA_ADMIN_AENQ_GROUPS_NUM = 5,
1028 enum ena_admin_aenq_notification_syndrom {
1029 ENA_ADMIN_SUSPEND = 0,
1030 ENA_ADMIN_RESUME = 1,
1031 ENA_ADMIN_UPDATE_HINTS = 2,
1034 struct ena_admin_aenq_entry {
1035 struct ena_admin_aenq_common_desc aenq_common_desc;
1037 /* command specific inline data */
1038 uint32_t inline_data_w4[12];
1041 struct ena_admin_aenq_link_change_desc {
1042 struct ena_admin_aenq_common_desc aenq_common_desc;
1044 /* 0 : link_status */
1048 struct ena_admin_aenq_keep_alive_desc {
1049 struct ena_admin_aenq_common_desc aenq_common_desc;
1051 uint32_t rx_drops_low;
1053 uint32_t rx_drops_high;
1055 uint32_t tx_drops_low;
1057 uint32_t tx_drops_high;
1060 struct ena_admin_ena_mmio_req_read_less_resp {
1065 /* value is valid when poll is cleared */
1069 /* aq_common_desc */
1070 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1071 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)
1072 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1
1073 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)
1074 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2
1075 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)
1078 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5
1079 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
1081 /* acq_common_desc */
1082 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1083 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)
1085 /* aq_create_sq_cmd */
1086 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5
1087 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
1088 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
1089 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4
1090 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
1091 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)
1093 /* aq_create_cq_cmd */
1094 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5
1095 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
1096 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
1098 /* get_set_feature_common_desc */
1099 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
1101 /* get_feature_link_desc */
1102 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0)
1103 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1
1104 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1)
1106 /* feature_offload_desc */
1107 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)
1108 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1
1109 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1)
1110 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2
1111 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)
1112 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3
1113 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
1114 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4
1115 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
1116 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5
1117 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5)
1118 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6
1119 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6)
1120 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7
1121 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7)
1122 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)
1123 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1
1124 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)
1125 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2
1126 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)
1127 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3
1128 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3)
1130 /* feature_rss_flow_hash_function */
1131 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
1132 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)
1134 /* feature_rss_flow_hash_input */
1135 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
1136 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1)
1137 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2
1138 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2)
1139 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1
1140 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)
1141 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2
1142 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)
1145 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)
1146 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8
1147 #define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8)
1148 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16
1149 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16)
1150 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24
1151 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24)
1152 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0)
1153 #define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3
1154 #define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3)
1155 #define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8
1156 #define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8)
1157 #define ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK BIT(0)
1158 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT 1
1159 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1)
1160 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2
1161 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2)
1162 #define ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT 3
1163 #define ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK BIT(3)
1165 /* feature_rss_ind_table */
1166 #define ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK BIT(0)
1168 /* aenq_common_desc */
1169 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)
1171 /* aenq_link_change_desc */
1172 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0)
1174 #if !defined(DEFS_LINUX_MAINLINE)
1175 static inline uint16_t get_ena_admin_aq_common_desc_command_id(const struct ena_admin_aq_common_desc *p)
1177 return p->command_id & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1180 static inline void set_ena_admin_aq_common_desc_command_id(struct ena_admin_aq_common_desc *p, uint16_t val)
1182 p->command_id |= val & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1185 static inline uint8_t get_ena_admin_aq_common_desc_phase(const struct ena_admin_aq_common_desc *p)
1187 return p->flags & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1190 static inline void set_ena_admin_aq_common_desc_phase(struct ena_admin_aq_common_desc *p, uint8_t val)
1192 p->flags |= val & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1195 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data(const struct ena_admin_aq_common_desc *p)
1197 return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT;
1200 static inline void set_ena_admin_aq_common_desc_ctrl_data(struct ena_admin_aq_common_desc *p, uint8_t val)
1202 p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK;
1205 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data_indirect(const struct ena_admin_aq_common_desc *p)
1207 return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT;
1210 static inline void set_ena_admin_aq_common_desc_ctrl_data_indirect(struct ena_admin_aq_common_desc *p, uint8_t val)
1212 p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1215 static inline uint8_t get_ena_admin_sq_sq_direction(const struct ena_admin_sq *p)
1217 return (p->sq_identity & ENA_ADMIN_SQ_SQ_DIRECTION_MASK) >> ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT;
1220 static inline void set_ena_admin_sq_sq_direction(struct ena_admin_sq *p, uint8_t val)
1222 p->sq_identity |= (val << ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
1225 static inline uint16_t get_ena_admin_acq_common_desc_command_id(const struct ena_admin_acq_common_desc *p)
1227 return p->command & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1230 static inline void set_ena_admin_acq_common_desc_command_id(struct ena_admin_acq_common_desc *p, uint16_t val)
1232 p->command |= val & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1235 static inline uint8_t get_ena_admin_acq_common_desc_phase(const struct ena_admin_acq_common_desc *p)
1237 return p->flags & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1240 static inline void set_ena_admin_acq_common_desc_phase(struct ena_admin_acq_common_desc *p, uint8_t val)
1242 p->flags |= val & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1245 static inline uint8_t get_ena_admin_aq_create_sq_cmd_sq_direction(const struct ena_admin_aq_create_sq_cmd *p)
1247 return (p->sq_identity & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT;
1250 static inline void set_ena_admin_aq_create_sq_cmd_sq_direction(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1252 p->sq_identity |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1255 static inline uint8_t get_ena_admin_aq_create_sq_cmd_placement_policy(const struct ena_admin_aq_create_sq_cmd *p)
1257 return p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1260 static inline void set_ena_admin_aq_create_sq_cmd_placement_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1262 p->sq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1265 static inline uint8_t get_ena_admin_aq_create_sq_cmd_completion_policy(const struct ena_admin_aq_create_sq_cmd *p)
1267 return (p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT;
1270 static inline void set_ena_admin_aq_create_sq_cmd_completion_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1272 p->sq_caps_2 |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1275 static inline uint8_t get_ena_admin_aq_create_sq_cmd_is_physically_contiguous(const struct ena_admin_aq_create_sq_cmd *p)
1277 return p->sq_caps_3 & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1280 static inline void set_ena_admin_aq_create_sq_cmd_is_physically_contiguous(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1282 p->sq_caps_3 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1285 static inline uint8_t get_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(const struct ena_admin_aq_create_cq_cmd *p)
1287 return (p->cq_caps_1 & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK) >> ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT;
1290 static inline void set_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1292 p->cq_caps_1 |= (val << ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT) & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1295 static inline uint8_t get_ena_admin_aq_create_cq_cmd_cq_entry_size_words(const struct ena_admin_aq_create_cq_cmd *p)
1297 return p->cq_caps_2 & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1300 static inline void set_ena_admin_aq_create_cq_cmd_cq_entry_size_words(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1302 p->cq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1305 static inline uint8_t get_ena_admin_get_set_feature_common_desc_select(const struct ena_admin_get_set_feature_common_desc *p)
1307 return p->flags & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1310 static inline void set_ena_admin_get_set_feature_common_desc_select(struct ena_admin_get_set_feature_common_desc *p, uint8_t val)
1312 p->flags |= val & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1315 static inline uint32_t get_ena_admin_get_feature_link_desc_autoneg(const struct ena_admin_get_feature_link_desc *p)
1317 return p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1320 static inline void set_ena_admin_get_feature_link_desc_autoneg(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1322 p->flags |= val & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1325 static inline uint32_t get_ena_admin_get_feature_link_desc_duplex(const struct ena_admin_get_feature_link_desc *p)
1327 return (p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK) >> ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT;
1330 static inline void set_ena_admin_get_feature_link_desc_duplex(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1332 p->flags |= (val << ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT) & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK;
1335 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1337 return p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1340 static inline void set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1342 p->tx |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1345 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(const struct ena_admin_feature_offload_desc *p)
1347 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT;
1350 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1352 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK;
1355 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(const struct ena_admin_feature_offload_desc *p)
1357 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT;
1360 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1362 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK;
1365 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(const struct ena_admin_feature_offload_desc *p)
1367 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT;
1370 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1372 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK;
1375 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(const struct ena_admin_feature_offload_desc *p)
1377 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT;
1380 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1382 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK;
1385 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv4(const struct ena_admin_feature_offload_desc *p)
1387 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT;
1390 static inline void set_ena_admin_feature_offload_desc_tso_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1392 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1395 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv6(const struct ena_admin_feature_offload_desc *p)
1397 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT;
1400 static inline void set_ena_admin_feature_offload_desc_tso_ipv6(struct ena_admin_feature_offload_desc *p, uint32_t val)
1402 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK;
1405 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ecn(const struct ena_admin_feature_offload_desc *p)
1407 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT;
1410 static inline void set_ena_admin_feature_offload_desc_tso_ecn(struct ena_admin_feature_offload_desc *p, uint32_t val)
1412 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK;
1415 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1417 return p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1420 static inline void set_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1422 p->rx_supported |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1425 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(const struct ena_admin_feature_offload_desc *p)
1427 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT;
1430 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1432 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK;
1435 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(const struct ena_admin_feature_offload_desc *p)
1437 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT;
1440 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1442 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK;
1445 static inline uint32_t get_ena_admin_feature_offload_desc_RX_hash(const struct ena_admin_feature_offload_desc *p)
1447 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT;
1450 static inline void set_ena_admin_feature_offload_desc_RX_hash(struct ena_admin_feature_offload_desc *p, uint32_t val)
1452 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK;
1455 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_funcs(const struct ena_admin_feature_rss_flow_hash_function *p)
1457 return p->supported_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1460 static inline void set_ena_admin_feature_rss_flow_hash_function_funcs(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1462 p->supported_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1465 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_selected_func(const struct ena_admin_feature_rss_flow_hash_function *p)
1467 return p->selected_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1470 static inline void set_ena_admin_feature_rss_flow_hash_function_selected_func(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1472 p->selected_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1475 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1477 return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT;
1480 static inline void set_ena_admin_feature_rss_flow_hash_input_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1482 p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK;
1485 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1487 return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT;
1490 static inline void set_ena_admin_feature_rss_flow_hash_input_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1492 p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
1495 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1497 return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT;
1500 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1502 p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK;
1505 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1507 return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT;
1510 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1512 p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK;
1515 static inline uint32_t get_ena_admin_host_info_major(const struct ena_admin_host_info *p)
1517 return p->driver_version & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1520 static inline void set_ena_admin_host_info_major(struct ena_admin_host_info *p, uint32_t val)
1522 p->driver_version |= val & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1525 static inline uint32_t get_ena_admin_host_info_minor(const struct ena_admin_host_info *p)
1527 return (p->driver_version & ENA_ADMIN_HOST_INFO_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_MINOR_SHIFT;
1530 static inline void set_ena_admin_host_info_minor(struct ena_admin_host_info *p, uint32_t val)
1532 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_MINOR_MASK;
1535 static inline uint32_t get_ena_admin_host_info_sub_minor(const struct ena_admin_host_info *p)
1537 return (p->driver_version & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT;
1540 static inline void set_ena_admin_host_info_sub_minor(struct ena_admin_host_info *p, uint32_t val)
1542 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK;
1545 static inline uint32_t get_ena_admin_host_info_module_type(const struct ena_admin_host_info *p)
1547 return (p->driver_version & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK) >> ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT;
1550 static inline void set_ena_admin_host_info_module_type(struct ena_admin_host_info *p, uint32_t val)
1552 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT) & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK;
1555 static inline uint16_t get_ena_admin_host_info_function(const struct ena_admin_host_info *p)
1557 return p->bdf & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1560 static inline void set_ena_admin_host_info_function(struct ena_admin_host_info *p, uint16_t val)
1562 p->bdf |= val & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1565 static inline uint16_t get_ena_admin_host_info_device(const struct ena_admin_host_info *p)
1567 return (p->bdf & ENA_ADMIN_HOST_INFO_DEVICE_MASK) >> ENA_ADMIN_HOST_INFO_DEVICE_SHIFT;
1570 static inline void set_ena_admin_host_info_device(struct ena_admin_host_info *p, uint16_t val)
1572 p->bdf |= (val << ENA_ADMIN_HOST_INFO_DEVICE_SHIFT) & ENA_ADMIN_HOST_INFO_DEVICE_MASK;
1575 static inline uint16_t get_ena_admin_host_info_bus(const struct ena_admin_host_info *p)
1577 return (p->bdf & ENA_ADMIN_HOST_INFO_BUS_MASK) >> ENA_ADMIN_HOST_INFO_BUS_SHIFT;
1580 static inline void set_ena_admin_host_info_bus(struct ena_admin_host_info *p, uint16_t val)
1582 p->bdf |= (val << ENA_ADMIN_HOST_INFO_BUS_SHIFT) & ENA_ADMIN_HOST_INFO_BUS_MASK;
1585 static inline uint32_t get_ena_admin_host_info_mutable_rss_table_size(const struct ena_admin_host_info *p)
1587 return p->driver_supported_features & ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK;
1590 static inline void set_ena_admin_host_info_mutable_rss_table_size(struct ena_admin_host_info *p, uint32_t val)
1592 p->driver_supported_features |= val & ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK;
1595 static inline uint32_t get_ena_admin_host_info_rx_offset(const struct ena_admin_host_info *p)
1597 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK) >> ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT;
1600 static inline void set_ena_admin_host_info_rx_offset(struct ena_admin_host_info *p, uint32_t val)
1602 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT) & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
1605 static inline uint32_t get_ena_admin_host_info_interrupt_moderation(const struct ena_admin_host_info *p)
1607 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK) >> ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT;
1610 static inline void set_ena_admin_host_info_interrupt_moderation(struct ena_admin_host_info *p, uint32_t val)
1612 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT) & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK;
1615 static inline uint32_t get_ena_admin_host_info_map_rx_buf_bidirectional(const struct ena_admin_host_info *p)
1617 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK) >> ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT;
1620 static inline void set_ena_admin_host_info_map_rx_buf_bidirectional(struct ena_admin_host_info *p, uint32_t val)
1622 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT) & ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK;
1625 static inline uint8_t get_ena_admin_feature_rss_ind_table_one_entry_update(const struct ena_admin_feature_rss_ind_table *p)
1627 return p->flags & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1630 static inline void set_ena_admin_feature_rss_ind_table_one_entry_update(struct ena_admin_feature_rss_ind_table *p, uint8_t val)
1632 p->flags |= val & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1635 static inline uint8_t get_ena_admin_aenq_common_desc_phase(const struct ena_admin_aenq_common_desc *p)
1637 return p->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1640 static inline void set_ena_admin_aenq_common_desc_phase(struct ena_admin_aenq_common_desc *p, uint8_t val)
1642 p->flags |= val & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1645 static inline uint32_t get_ena_admin_aenq_link_change_desc_link_status(const struct ena_admin_aenq_link_change_desc *p)
1647 return p->flags & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1650 static inline void set_ena_admin_aenq_link_change_desc_link_status(struct ena_admin_aenq_link_change_desc *p, uint32_t val)
1652 p->flags |= val & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1655 #endif /* !defined(DEFS_LINUX_MAINLINE) */
1656 #endif /* _ENA_ADMIN_H_ */