1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
8 /*****************************************************************************/
9 /*****************************************************************************/
11 /* Timeout in micro-sec */
12 #define ADMIN_CMD_TIMEOUT_US (3000000)
14 #define ENA_ASYNC_QUEUE_DEPTH 16
15 #define ENA_ADMIN_QUEUE_DEPTH 32
17 #define ENA_CTRL_MAJOR 0
18 #define ENA_CTRL_MINOR 0
19 #define ENA_CTRL_SUB_MINOR 1
21 #define MIN_ENA_CTRL_VER \
22 (((ENA_CTRL_MAJOR) << \
23 (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
24 ((ENA_CTRL_MINOR) << \
25 (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
28 #define ENA_DMA_ADDR_TO_UINT32_LOW(x) ((u32)((u64)(x)))
29 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x) ((u32)(((u64)(x)) >> 32))
31 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
33 #define ENA_COM_BOUNCE_BUFFER_CNTRL_CNT 4
35 #define ENA_REGS_ADMIN_INTR_MASK 1
39 /*****************************************************************************/
40 /*****************************************************************************/
41 /*****************************************************************************/
46 /* Abort - canceled by the driver */
51 ena_wait_event_t wait_event;
52 struct ena_admin_acq_entry *user_cqe;
54 enum ena_cmd_status status;
55 /* status from the device */
61 struct ena_com_stats_ctx {
62 struct ena_admin_aq_get_stats_cmd get_cmd;
63 struct ena_admin_acq_get_stats_resp get_resp;
66 static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,
67 struct ena_common_mem_addr *ena_addr,
70 if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {
71 ena_trc_err("dma address has more bits that the device supports\n");
75 ena_addr->mem_addr_low = lower_32_bits(addr);
76 ena_addr->mem_addr_high = (u16)upper_32_bits(addr);
81 static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue)
83 struct ena_com_admin_sq *sq = &queue->sq;
84 u16 size = ADMIN_SQ_SIZE(queue->q_depth);
86 ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, sq->entries, sq->dma_addr,
90 ena_trc_err("memory allocation failed\n");
91 return ENA_COM_NO_MEM;
103 static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue)
105 struct ena_com_admin_cq *cq = &queue->cq;
106 u16 size = ADMIN_CQ_SIZE(queue->q_depth);
108 ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, cq->entries, cq->dma_addr,
112 ena_trc_err("memory allocation failed\n");
113 return ENA_COM_NO_MEM;
122 static int ena_com_admin_init_aenq(struct ena_com_dev *dev,
123 struct ena_aenq_handlers *aenq_handlers)
125 struct ena_com_aenq *aenq = &dev->aenq;
126 u32 addr_low, addr_high, aenq_caps;
129 dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;
130 size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH);
131 ENA_MEM_ALLOC_COHERENT(dev->dmadev, size,
136 if (!aenq->entries) {
137 ena_trc_err("memory allocation failed\n");
138 return ENA_COM_NO_MEM;
141 aenq->head = aenq->q_depth;
144 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
145 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
147 ENA_REG_WRITE32(dev->bus, addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);
148 ENA_REG_WRITE32(dev->bus, addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);
151 aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
152 aenq_caps |= (sizeof(struct ena_admin_aenq_entry) <<
153 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
154 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
155 ENA_REG_WRITE32(dev->bus, aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);
157 if (unlikely(!aenq_handlers)) {
158 ena_trc_err("aenq handlers pointer is NULL\n");
159 return ENA_COM_INVAL;
162 aenq->aenq_handlers = aenq_handlers;
167 static void comp_ctxt_release(struct ena_com_admin_queue *queue,
168 struct ena_comp_ctx *comp_ctx)
170 comp_ctx->occupied = false;
171 ATOMIC32_DEC(&queue->outstanding_cmds);
174 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue,
175 u16 command_id, bool capture)
177 if (unlikely(command_id >= queue->q_depth)) {
178 ena_trc_err("command id is larger than the queue size. cmd_id: %u queue size %d\n",
179 command_id, queue->q_depth);
183 if (unlikely(!queue->comp_ctx)) {
184 ena_trc_err("Completion context is NULL\n");
188 if (unlikely(queue->comp_ctx[command_id].occupied && capture)) {
189 ena_trc_err("Completion context is occupied\n");
194 ATOMIC32_INC(&queue->outstanding_cmds);
195 queue->comp_ctx[command_id].occupied = true;
198 return &queue->comp_ctx[command_id];
201 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
202 struct ena_admin_aq_entry *cmd,
203 size_t cmd_size_in_bytes,
204 struct ena_admin_acq_entry *comp,
205 size_t comp_size_in_bytes)
207 struct ena_comp_ctx *comp_ctx;
208 u16 tail_masked, cmd_id;
212 queue_size_mask = admin_queue->q_depth - 1;
214 tail_masked = admin_queue->sq.tail & queue_size_mask;
216 /* In case of queue FULL */
217 cnt = (u16)ATOMIC32_READ(&admin_queue->outstanding_cmds);
218 if (cnt >= admin_queue->q_depth) {
219 ena_trc_dbg("admin queue is full.\n");
220 admin_queue->stats.out_of_space++;
221 return ERR_PTR(ENA_COM_NO_SPACE);
224 cmd_id = admin_queue->curr_cmd_id;
226 cmd->aq_common_descriptor.flags |= admin_queue->sq.phase &
227 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
229 cmd->aq_common_descriptor.command_id |= cmd_id &
230 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
232 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true);
233 if (unlikely(!comp_ctx))
234 return ERR_PTR(ENA_COM_INVAL);
236 comp_ctx->status = ENA_CMD_SUBMITTED;
237 comp_ctx->comp_size = (u32)comp_size_in_bytes;
238 comp_ctx->user_cqe = comp;
239 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
241 ENA_WAIT_EVENT_CLEAR(comp_ctx->wait_event);
243 memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes);
245 admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) &
248 admin_queue->sq.tail++;
249 admin_queue->stats.submitted_cmd++;
251 if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0))
252 admin_queue->sq.phase = !admin_queue->sq.phase;
254 ENA_DB_SYNC(&admin_queue->sq.mem_handle);
255 ENA_REG_WRITE32(admin_queue->bus, admin_queue->sq.tail,
256 admin_queue->sq.db_addr);
261 static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue)
263 size_t size = queue->q_depth * sizeof(struct ena_comp_ctx);
264 struct ena_comp_ctx *comp_ctx;
267 queue->comp_ctx = ENA_MEM_ALLOC(queue->q_dmadev, size);
268 if (unlikely(!queue->comp_ctx)) {
269 ena_trc_err("memory allocation failed\n");
270 return ENA_COM_NO_MEM;
273 for (i = 0; i < queue->q_depth; i++) {
274 comp_ctx = get_comp_ctxt(queue, i, false);
276 ENA_WAIT_EVENT_INIT(comp_ctx->wait_event);
282 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
283 struct ena_admin_aq_entry *cmd,
284 size_t cmd_size_in_bytes,
285 struct ena_admin_acq_entry *comp,
286 size_t comp_size_in_bytes)
288 unsigned long flags = 0;
289 struct ena_comp_ctx *comp_ctx;
291 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
292 if (unlikely(!admin_queue->running_state)) {
293 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
294 return ERR_PTR(ENA_COM_NO_DEVICE);
296 comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd,
300 if (IS_ERR(comp_ctx))
301 admin_queue->running_state = false;
302 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
307 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
308 struct ena_com_create_io_ctx *ctx,
309 struct ena_com_io_sq *io_sq)
314 memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr));
316 io_sq->dma_addr_bits = (u8)ena_dev->dma_addr_bits;
317 io_sq->desc_entry_size =
318 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
319 sizeof(struct ena_eth_io_tx_desc) :
320 sizeof(struct ena_eth_io_rx_desc);
322 size = io_sq->desc_entry_size * io_sq->q_depth;
323 io_sq->bus = ena_dev->bus;
325 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
326 ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
328 io_sq->desc_addr.virt_addr,
329 io_sq->desc_addr.phys_addr,
330 io_sq->desc_addr.mem_handle,
333 if (!io_sq->desc_addr.virt_addr) {
334 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
336 io_sq->desc_addr.virt_addr,
337 io_sq->desc_addr.phys_addr,
338 io_sq->desc_addr.mem_handle);
341 if (!io_sq->desc_addr.virt_addr) {
342 ena_trc_err("memory allocation failed\n");
343 return ENA_COM_NO_MEM;
347 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
348 /* Allocate bounce buffers */
349 io_sq->bounce_buf_ctrl.buffer_size =
350 ena_dev->llq_info.desc_list_entry_size;
351 io_sq->bounce_buf_ctrl.buffers_num =
352 ENA_COM_BOUNCE_BUFFER_CNTRL_CNT;
353 io_sq->bounce_buf_ctrl.next_to_use = 0;
355 size = io_sq->bounce_buf_ctrl.buffer_size *
356 io_sq->bounce_buf_ctrl.buffers_num;
358 ENA_MEM_ALLOC_NODE(ena_dev->dmadev,
360 io_sq->bounce_buf_ctrl.base_buffer,
363 if (!io_sq->bounce_buf_ctrl.base_buffer)
364 io_sq->bounce_buf_ctrl.base_buffer = ENA_MEM_ALLOC(ena_dev->dmadev, size);
366 if (!io_sq->bounce_buf_ctrl.base_buffer) {
367 ena_trc_err("bounce buffer memory allocation failed\n");
368 return ENA_COM_NO_MEM;
371 memcpy(&io_sq->llq_info, &ena_dev->llq_info,
372 sizeof(io_sq->llq_info));
374 /* Initiate the first bounce buffer */
375 io_sq->llq_buf_ctrl.curr_bounce_buf =
376 ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
377 memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
378 0x0, io_sq->llq_info.desc_list_entry_size);
379 io_sq->llq_buf_ctrl.descs_left_in_line =
380 io_sq->llq_info.descs_num_before_header;
381 io_sq->disable_meta_caching =
382 io_sq->llq_info.disable_meta_caching;
384 if (io_sq->llq_info.max_entries_in_tx_burst > 0)
385 io_sq->entries_in_tx_burst_left =
386 io_sq->llq_info.max_entries_in_tx_burst;
390 io_sq->next_to_comp = 0;
396 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
397 struct ena_com_create_io_ctx *ctx,
398 struct ena_com_io_cq *io_cq)
403 memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr));
405 /* Use the basic completion descriptor for Rx */
406 io_cq->cdesc_entry_size_in_bytes =
407 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
408 sizeof(struct ena_eth_io_tx_cdesc) :
409 sizeof(struct ena_eth_io_rx_cdesc_base);
411 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
412 io_cq->bus = ena_dev->bus;
414 ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
416 io_cq->cdesc_addr.virt_addr,
417 io_cq->cdesc_addr.phys_addr,
418 io_cq->cdesc_addr.mem_handle,
421 if (!io_cq->cdesc_addr.virt_addr) {
422 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
424 io_cq->cdesc_addr.virt_addr,
425 io_cq->cdesc_addr.phys_addr,
426 io_cq->cdesc_addr.mem_handle);
429 if (!io_cq->cdesc_addr.virt_addr) {
430 ena_trc_err("memory allocation failed\n");
431 return ENA_COM_NO_MEM;
440 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,
441 struct ena_admin_acq_entry *cqe)
443 struct ena_comp_ctx *comp_ctx;
446 cmd_id = cqe->acq_common_descriptor.command &
447 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
449 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false);
450 if (unlikely(!comp_ctx)) {
451 ena_trc_err("comp_ctx is NULL. Changing the admin queue running state\n");
452 admin_queue->running_state = false;
456 comp_ctx->status = ENA_CMD_COMPLETED;
457 comp_ctx->comp_status = cqe->acq_common_descriptor.status;
459 if (comp_ctx->user_cqe)
460 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size);
462 if (!admin_queue->polling)
463 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
466 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)
468 struct ena_admin_acq_entry *cqe = NULL;
473 head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1);
474 phase = admin_queue->cq.phase;
476 cqe = &admin_queue->cq.entries[head_masked];
478 /* Go over all the completions */
479 while ((READ_ONCE8(cqe->acq_common_descriptor.flags) &
480 ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
481 /* Do not read the rest of the completion entry before the
482 * phase bit was validated
485 ena_com_handle_single_admin_completion(admin_queue, cqe);
489 if (unlikely(head_masked == admin_queue->q_depth)) {
494 cqe = &admin_queue->cq.entries[head_masked];
497 admin_queue->cq.head += comp_num;
498 admin_queue->cq.phase = phase;
499 admin_queue->sq.head += comp_num;
500 admin_queue->stats.completed_cmd += comp_num;
503 static int ena_com_comp_status_to_errno(u8 comp_status)
505 if (unlikely(comp_status != 0))
506 ena_trc_err("admin command failed[%u]\n", comp_status);
508 switch (comp_status) {
509 case ENA_ADMIN_SUCCESS:
511 case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
512 return ENA_COM_NO_MEM;
513 case ENA_ADMIN_UNSUPPORTED_OPCODE:
514 return ENA_COM_UNSUPPORTED;
515 case ENA_ADMIN_BAD_OPCODE:
516 case ENA_ADMIN_MALFORMED_REQUEST:
517 case ENA_ADMIN_ILLEGAL_PARAMETER:
518 case ENA_ADMIN_UNKNOWN_ERROR:
519 return ENA_COM_INVAL;
522 return ENA_COM_INVAL;
525 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,
526 struct ena_com_admin_queue *admin_queue)
528 unsigned long flags = 0;
532 timeout = ENA_GET_SYSTEM_TIMEOUT(admin_queue->completion_timeout);
535 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
536 ena_com_handle_admin_completion(admin_queue);
537 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
539 if (comp_ctx->status != ENA_CMD_SUBMITTED)
542 if (ENA_TIME_EXPIRE(timeout)) {
543 ena_trc_err("Wait for completion (polling) timeout\n");
544 /* ENA didn't have any completion */
545 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
546 admin_queue->stats.no_completion++;
547 admin_queue->running_state = false;
548 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
550 ret = ENA_COM_TIMER_EXPIRED;
554 ENA_MSLEEP(ENA_POLL_MS);
557 if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {
558 ena_trc_err("Command was aborted\n");
559 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
560 admin_queue->stats.aborted_cmd++;
561 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
562 ret = ENA_COM_NO_DEVICE;
566 ENA_WARN(comp_ctx->status != ENA_CMD_COMPLETED,
567 "Invalid comp status %d\n", comp_ctx->status);
569 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
571 comp_ctxt_release(admin_queue, comp_ctx);
576 * Set the LLQ configurations of the firmware
578 * The driver provides only the enabled feature values to the device,
579 * which in turn, checks if they are supported.
581 static int ena_com_set_llq(struct ena_com_dev *ena_dev)
583 struct ena_com_admin_queue *admin_queue;
584 struct ena_admin_set_feat_cmd cmd;
585 struct ena_admin_set_feat_resp resp;
586 struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
589 memset(&cmd, 0x0, sizeof(cmd));
590 admin_queue = &ena_dev->admin_queue;
592 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
593 cmd.feat_common.feature_id = ENA_ADMIN_LLQ;
595 cmd.u.llq.header_location_ctrl_enabled = llq_info->header_location_ctrl;
596 cmd.u.llq.entry_size_ctrl_enabled = llq_info->desc_list_entry_size_ctrl;
597 cmd.u.llq.desc_num_before_header_enabled = llq_info->descs_num_before_header;
598 cmd.u.llq.descriptors_stride_ctrl_enabled = llq_info->desc_stride_ctrl;
600 if (llq_info->disable_meta_caching)
601 cmd.u.llq.accel_mode.u.set.enabled_flags |=
602 BIT(ENA_ADMIN_DISABLE_META_CACHING);
604 if (llq_info->max_entries_in_tx_burst)
605 cmd.u.llq.accel_mode.u.set.enabled_flags |=
606 BIT(ENA_ADMIN_LIMIT_TX_BURST);
608 ret = ena_com_execute_admin_command(admin_queue,
609 (struct ena_admin_aq_entry *)&cmd,
611 (struct ena_admin_acq_entry *)&resp,
615 ena_trc_err("Failed to set LLQ configurations: %d\n", ret);
620 static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,
621 struct ena_admin_feature_llq_desc *llq_features,
622 struct ena_llq_configurations *llq_default_cfg)
624 struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
628 memset(llq_info, 0, sizeof(*llq_info));
630 supported_feat = llq_features->header_location_ctrl_supported;
632 if (likely(supported_feat & llq_default_cfg->llq_header_location)) {
633 llq_info->header_location_ctrl =
634 llq_default_cfg->llq_header_location;
636 ena_trc_err("Invalid header location control, supported: 0x%x\n",
641 if (likely(llq_info->header_location_ctrl == ENA_ADMIN_INLINE_HEADER)) {
642 supported_feat = llq_features->descriptors_stride_ctrl_supported;
643 if (likely(supported_feat & llq_default_cfg->llq_stride_ctrl)) {
644 llq_info->desc_stride_ctrl = llq_default_cfg->llq_stride_ctrl;
646 if (supported_feat & ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY) {
647 llq_info->desc_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
648 } else if (supported_feat & ENA_ADMIN_SINGLE_DESC_PER_ENTRY) {
649 llq_info->desc_stride_ctrl = ENA_ADMIN_SINGLE_DESC_PER_ENTRY;
651 ena_trc_err("Invalid desc_stride_ctrl, supported: 0x%x\n",
656 ena_trc_err("Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
657 llq_default_cfg->llq_stride_ctrl,
659 llq_info->desc_stride_ctrl);
662 llq_info->desc_stride_ctrl = 0;
665 supported_feat = llq_features->entry_size_ctrl_supported;
666 if (likely(supported_feat & llq_default_cfg->llq_ring_entry_size)) {
667 llq_info->desc_list_entry_size_ctrl = llq_default_cfg->llq_ring_entry_size;
668 llq_info->desc_list_entry_size = llq_default_cfg->llq_ring_entry_size_value;
670 if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_128B) {
671 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
672 llq_info->desc_list_entry_size = 128;
673 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_192B) {
674 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_192B;
675 llq_info->desc_list_entry_size = 192;
676 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_256B) {
677 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_256B;
678 llq_info->desc_list_entry_size = 256;
680 ena_trc_err("Invalid entry_size_ctrl, supported: 0x%x\n", supported_feat);
684 ena_trc_err("Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
685 llq_default_cfg->llq_ring_entry_size,
687 llq_info->desc_list_entry_size);
689 if (unlikely(llq_info->desc_list_entry_size & 0x7)) {
690 /* The desc list entry size should be whole multiply of 8
691 * This requirement comes from __iowrite64_copy()
693 ena_trc_err("illegal entry size %d\n",
694 llq_info->desc_list_entry_size);
698 if (llq_info->desc_stride_ctrl == ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY)
699 llq_info->descs_per_entry = llq_info->desc_list_entry_size /
700 sizeof(struct ena_eth_io_tx_desc);
702 llq_info->descs_per_entry = 1;
704 supported_feat = llq_features->desc_num_before_header_supported;
705 if (likely(supported_feat & llq_default_cfg->llq_num_decs_before_header)) {
706 llq_info->descs_num_before_header = llq_default_cfg->llq_num_decs_before_header;
708 if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2) {
709 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
710 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1) {
711 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1;
712 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4) {
713 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4;
714 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8) {
715 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8;
717 ena_trc_err("Invalid descs_num_before_header, supported: 0x%x\n",
722 ena_trc_err("Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
723 llq_default_cfg->llq_num_decs_before_header,
725 llq_info->descs_num_before_header);
727 /* Check for accelerated queue supported */
728 llq_info->disable_meta_caching =
729 llq_features->accel_mode.u.get.supported_flags &
730 BIT(ENA_ADMIN_DISABLE_META_CACHING);
732 if (llq_features->accel_mode.u.get.supported_flags & BIT(ENA_ADMIN_LIMIT_TX_BURST))
733 llq_info->max_entries_in_tx_burst =
734 llq_features->accel_mode.u.get.max_tx_burst_size /
735 llq_default_cfg->llq_ring_entry_size_value;
737 rc = ena_com_set_llq(ena_dev);
739 ena_trc_err("Cannot set LLQ configuration: %d\n", rc);
744 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx,
745 struct ena_com_admin_queue *admin_queue)
747 unsigned long flags = 0;
750 ENA_WAIT_EVENT_WAIT(comp_ctx->wait_event,
751 admin_queue->completion_timeout);
753 /* In case the command wasn't completed find out the root cause.
754 * There might be 2 kinds of errors
755 * 1) No completion (timeout reached)
756 * 2) There is completion but the device didn't get any msi-x interrupt.
758 if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) {
759 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
760 ena_com_handle_admin_completion(admin_queue);
761 admin_queue->stats.no_completion++;
762 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
764 if (comp_ctx->status == ENA_CMD_COMPLETED) {
765 ena_trc_err("The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d), autopolling mode is %s\n",
766 comp_ctx->cmd_opcode, admin_queue->auto_polling ? "ON" : "OFF");
767 /* Check if fallback to polling is enabled */
768 if (admin_queue->auto_polling)
769 admin_queue->polling = true;
771 ena_trc_err("The ena device didn't send a completion for the admin cmd %d status %d\n",
772 comp_ctx->cmd_opcode, comp_ctx->status);
774 /* Check if shifted to polling mode.
775 * This will happen if there is a completion without an interrupt
776 * and autopolling mode is enabled. Continuing normal execution in such case
778 if (!admin_queue->polling) {
779 admin_queue->running_state = false;
780 ret = ENA_COM_TIMER_EXPIRED;
785 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
787 comp_ctxt_release(admin_queue, comp_ctx);
791 /* This method read the hardware device register through posting writes
792 * and waiting for response
793 * On timeout the function will return ENA_MMIO_READ_TIMEOUT
795 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
797 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
798 volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp =
799 mmio_read->read_resp;
800 u32 mmio_read_reg, ret, i;
801 unsigned long flags = 0;
802 u32 timeout = mmio_read->reg_read_to;
807 timeout = ENA_REG_READ_TIMEOUT;
809 /* If readless is disabled, perform regular read */
810 if (!mmio_read->readless_supported)
811 return ENA_REG_READ32(ena_dev->bus, ena_dev->reg_bar + offset);
813 ENA_SPINLOCK_LOCK(mmio_read->lock, flags);
814 mmio_read->seq_num++;
816 read_resp->req_id = mmio_read->seq_num + 0xDEAD;
817 mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
818 ENA_REGS_MMIO_REG_READ_REG_OFF_MASK;
819 mmio_read_reg |= mmio_read->seq_num &
820 ENA_REGS_MMIO_REG_READ_REQ_ID_MASK;
822 ENA_REG_WRITE32(ena_dev->bus, mmio_read_reg,
823 ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
825 for (i = 0; i < timeout; i++) {
826 if (READ_ONCE16(read_resp->req_id) == mmio_read->seq_num)
832 if (unlikely(i == timeout)) {
833 ena_trc_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n",
838 ret = ENA_MMIO_READ_TIMEOUT;
842 if (read_resp->reg_off != offset) {
843 ena_trc_err("Read failure: wrong offset provided\n");
844 ret = ENA_MMIO_READ_TIMEOUT;
846 ret = read_resp->reg_val;
849 ENA_SPINLOCK_UNLOCK(mmio_read->lock, flags);
854 /* There are two types to wait for completion.
855 * Polling mode - wait until the completion is available.
856 * Async mode - wait on wait queue until the completion is ready
857 * (or the timeout expired).
858 * It is expected that the IRQ called ena_com_handle_admin_completion
859 * to mark the completions.
861 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx,
862 struct ena_com_admin_queue *admin_queue)
864 if (admin_queue->polling)
865 return ena_com_wait_and_process_admin_cq_polling(comp_ctx,
868 return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx,
872 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,
873 struct ena_com_io_sq *io_sq)
875 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
876 struct ena_admin_aq_destroy_sq_cmd destroy_cmd;
877 struct ena_admin_acq_destroy_sq_resp_desc destroy_resp;
881 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
883 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
884 direction = ENA_ADMIN_SQ_DIRECTION_TX;
886 direction = ENA_ADMIN_SQ_DIRECTION_RX;
888 destroy_cmd.sq.sq_identity |= (direction <<
889 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) &
890 ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
892 destroy_cmd.sq.sq_idx = io_sq->idx;
893 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ;
895 ret = ena_com_execute_admin_command(admin_queue,
896 (struct ena_admin_aq_entry *)&destroy_cmd,
898 (struct ena_admin_acq_entry *)&destroy_resp,
899 sizeof(destroy_resp));
901 if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
902 ena_trc_err("failed to destroy io sq error: %d\n", ret);
907 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,
908 struct ena_com_io_sq *io_sq,
909 struct ena_com_io_cq *io_cq)
913 if (io_cq->cdesc_addr.virt_addr) {
914 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
916 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
918 io_cq->cdesc_addr.virt_addr,
919 io_cq->cdesc_addr.phys_addr,
920 io_cq->cdesc_addr.mem_handle);
922 io_cq->cdesc_addr.virt_addr = NULL;
925 if (io_sq->desc_addr.virt_addr) {
926 size = io_sq->desc_entry_size * io_sq->q_depth;
928 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
930 io_sq->desc_addr.virt_addr,
931 io_sq->desc_addr.phys_addr,
932 io_sq->desc_addr.mem_handle);
934 io_sq->desc_addr.virt_addr = NULL;
937 if (io_sq->bounce_buf_ctrl.base_buffer) {
938 ENA_MEM_FREE(ena_dev->dmadev,
939 io_sq->bounce_buf_ctrl.base_buffer,
940 (io_sq->llq_info.desc_list_entry_size * ENA_COM_BOUNCE_BUFFER_CNTRL_CNT));
941 io_sq->bounce_buf_ctrl.base_buffer = NULL;
945 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,
950 /* Convert timeout from resolution of 100ms to ENA_POLL_MS */
951 timeout = (timeout * 100) / ENA_POLL_MS;
953 for (i = 0; i < timeout; i++) {
954 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
956 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) {
957 ena_trc_err("Reg read timeout occurred\n");
958 return ENA_COM_TIMER_EXPIRED;
961 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
965 ENA_MSLEEP(ENA_POLL_MS);
968 return ENA_COM_TIMER_EXPIRED;
971 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,
972 enum ena_admin_aq_feature_id feature_id)
974 u32 feature_mask = 1 << feature_id;
976 /* Device attributes is always supported */
977 if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) &&
978 !(ena_dev->supported_features & feature_mask))
984 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
985 struct ena_admin_get_feat_resp *get_resp,
986 enum ena_admin_aq_feature_id feature_id,
987 dma_addr_t control_buf_dma_addr,
988 u32 control_buff_size,
991 struct ena_com_admin_queue *admin_queue;
992 struct ena_admin_get_feat_cmd get_cmd;
995 if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) {
996 ena_trc_dbg("Feature %d isn't supported\n", feature_id);
997 return ENA_COM_UNSUPPORTED;
1000 memset(&get_cmd, 0x0, sizeof(get_cmd));
1001 admin_queue = &ena_dev->admin_queue;
1003 get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE;
1005 if (control_buff_size)
1006 get_cmd.aq_common_descriptor.flags =
1007 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1009 get_cmd.aq_common_descriptor.flags = 0;
1011 ret = ena_com_mem_addr_set(ena_dev,
1012 &get_cmd.control_buffer.address,
1013 control_buf_dma_addr);
1014 if (unlikely(ret)) {
1015 ena_trc_err("memory address set failed\n");
1019 get_cmd.control_buffer.length = control_buff_size;
1020 get_cmd.feat_common.feature_version = feature_ver;
1021 get_cmd.feat_common.feature_id = feature_id;
1023 ret = ena_com_execute_admin_command(admin_queue,
1024 (struct ena_admin_aq_entry *)
1027 (struct ena_admin_acq_entry *)
1032 ena_trc_err("Failed to submit get_feature command %d error: %d\n",
1038 static int ena_com_get_feature(struct ena_com_dev *ena_dev,
1039 struct ena_admin_get_feat_resp *get_resp,
1040 enum ena_admin_aq_feature_id feature_id,
1043 return ena_com_get_feature_ex(ena_dev,
1051 static void ena_com_hash_key_fill_default_key(struct ena_com_dev *ena_dev)
1053 struct ena_admin_feature_rss_flow_hash_control *hash_key =
1054 (ena_dev->rss).hash_key;
1056 ENA_RSS_FILL_KEY(&hash_key->key, sizeof(hash_key->key));
1057 /* The key is stored in the device in uint32_t array
1058 * as well as the API requires the key to be passed in this
1059 * format. Thus the size of our array should be divided by 4
1061 hash_key->keys_num = sizeof(hash_key->key) / sizeof(uint32_t);
1064 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev)
1066 struct ena_rss *rss = &ena_dev->rss;
1068 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1069 sizeof(*rss->hash_key),
1071 rss->hash_key_dma_addr,
1072 rss->hash_key_mem_handle);
1074 if (unlikely(!rss->hash_key))
1075 return ENA_COM_NO_MEM;
1080 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
1082 struct ena_rss *rss = &ena_dev->rss;
1085 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1086 sizeof(*rss->hash_key),
1088 rss->hash_key_dma_addr,
1089 rss->hash_key_mem_handle);
1090 rss->hash_key = NULL;
1093 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev)
1095 struct ena_rss *rss = &ena_dev->rss;
1097 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1098 sizeof(*rss->hash_ctrl),
1100 rss->hash_ctrl_dma_addr,
1101 rss->hash_ctrl_mem_handle);
1103 if (unlikely(!rss->hash_ctrl))
1104 return ENA_COM_NO_MEM;
1109 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
1111 struct ena_rss *rss = &ena_dev->rss;
1114 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1115 sizeof(*rss->hash_ctrl),
1117 rss->hash_ctrl_dma_addr,
1118 rss->hash_ctrl_mem_handle);
1119 rss->hash_ctrl = NULL;
1122 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
1125 struct ena_rss *rss = &ena_dev->rss;
1126 struct ena_admin_get_feat_resp get_resp;
1130 ret = ena_com_get_feature(ena_dev, &get_resp,
1131 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0);
1135 if ((get_resp.u.ind_table.min_size > log_size) ||
1136 (get_resp.u.ind_table.max_size < log_size)) {
1137 ena_trc_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n",
1139 1 << get_resp.u.ind_table.min_size,
1140 1 << get_resp.u.ind_table.max_size);
1141 return ENA_COM_INVAL;
1144 tbl_size = (1ULL << log_size) *
1145 sizeof(struct ena_admin_rss_ind_table_entry);
1147 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1150 rss->rss_ind_tbl_dma_addr,
1151 rss->rss_ind_tbl_mem_handle);
1152 if (unlikely(!rss->rss_ind_tbl))
1155 tbl_size = (1ULL << log_size) * sizeof(u16);
1156 rss->host_rss_ind_tbl =
1157 ENA_MEM_ALLOC(ena_dev->dmadev, tbl_size);
1158 if (unlikely(!rss->host_rss_ind_tbl))
1161 rss->tbl_log_size = log_size;
1166 tbl_size = (1ULL << log_size) *
1167 sizeof(struct ena_admin_rss_ind_table_entry);
1169 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1172 rss->rss_ind_tbl_dma_addr,
1173 rss->rss_ind_tbl_mem_handle);
1174 rss->rss_ind_tbl = NULL;
1176 rss->tbl_log_size = 0;
1177 return ENA_COM_NO_MEM;
1180 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
1182 struct ena_rss *rss = &ena_dev->rss;
1183 size_t tbl_size = (1ULL << rss->tbl_log_size) *
1184 sizeof(struct ena_admin_rss_ind_table_entry);
1186 if (rss->rss_ind_tbl)
1187 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1190 rss->rss_ind_tbl_dma_addr,
1191 rss->rss_ind_tbl_mem_handle);
1192 rss->rss_ind_tbl = NULL;
1194 if (rss->host_rss_ind_tbl)
1195 ENA_MEM_FREE(ena_dev->dmadev,
1196 rss->host_rss_ind_tbl,
1197 ((1ULL << rss->tbl_log_size) * sizeof(u16)));
1198 rss->host_rss_ind_tbl = NULL;
1201 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,
1202 struct ena_com_io_sq *io_sq, u16 cq_idx)
1204 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1205 struct ena_admin_aq_create_sq_cmd create_cmd;
1206 struct ena_admin_acq_create_sq_resp_desc cmd_completion;
1210 memset(&create_cmd, 0x0, sizeof(create_cmd));
1212 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ;
1214 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1215 direction = ENA_ADMIN_SQ_DIRECTION_TX;
1217 direction = ENA_ADMIN_SQ_DIRECTION_RX;
1219 create_cmd.sq_identity |= (direction <<
1220 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) &
1221 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1223 create_cmd.sq_caps_2 |= io_sq->mem_queue_type &
1224 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1226 create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC <<
1227 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) &
1228 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1230 create_cmd.sq_caps_3 |=
1231 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1233 create_cmd.cq_idx = cq_idx;
1234 create_cmd.sq_depth = io_sq->q_depth;
1236 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
1237 ret = ena_com_mem_addr_set(ena_dev,
1239 io_sq->desc_addr.phys_addr);
1240 if (unlikely(ret)) {
1241 ena_trc_err("memory address set failed\n");
1246 ret = ena_com_execute_admin_command(admin_queue,
1247 (struct ena_admin_aq_entry *)&create_cmd,
1249 (struct ena_admin_acq_entry *)&cmd_completion,
1250 sizeof(cmd_completion));
1251 if (unlikely(ret)) {
1252 ena_trc_err("Failed to create IO SQ. error: %d\n", ret);
1256 io_sq->idx = cmd_completion.sq_idx;
1258 io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1259 (uintptr_t)cmd_completion.sq_doorbell_offset);
1261 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1262 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar
1263 + cmd_completion.llq_headers_offset);
1265 io_sq->desc_addr.pbuf_dev_addr =
1266 (u8 __iomem *)((uintptr_t)ena_dev->mem_bar +
1267 cmd_completion.llq_descriptors_offset);
1270 ena_trc_dbg("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth);
1275 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev)
1277 struct ena_rss *rss = &ena_dev->rss;
1278 struct ena_com_io_sq *io_sq;
1282 for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1283 qid = rss->host_rss_ind_tbl[i];
1284 if (qid >= ENA_TOTAL_NUM_QUEUES)
1285 return ENA_COM_INVAL;
1287 io_sq = &ena_dev->io_sq_queues[qid];
1289 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX)
1290 return ENA_COM_INVAL;
1292 rss->rss_ind_tbl[i].cq_idx = io_sq->idx;
1298 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,
1299 u16 intr_delay_resolution)
1301 u16 prev_intr_delay_resolution = ena_dev->intr_delay_resolution;
1303 if (unlikely(!intr_delay_resolution)) {
1304 ena_trc_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n");
1305 intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION;
1309 ena_dev->intr_moder_rx_interval =
1310 ena_dev->intr_moder_rx_interval *
1311 prev_intr_delay_resolution /
1312 intr_delay_resolution;
1315 ena_dev->intr_moder_tx_interval =
1316 ena_dev->intr_moder_tx_interval *
1317 prev_intr_delay_resolution /
1318 intr_delay_resolution;
1320 ena_dev->intr_delay_resolution = intr_delay_resolution;
1323 /*****************************************************************************/
1324 /******************************* API ******************************/
1325 /*****************************************************************************/
1327 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
1328 struct ena_admin_aq_entry *cmd,
1330 struct ena_admin_acq_entry *comp,
1333 struct ena_comp_ctx *comp_ctx;
1336 comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,
1338 if (IS_ERR(comp_ctx)) {
1339 if (comp_ctx == ERR_PTR(ENA_COM_NO_DEVICE))
1340 ena_trc_dbg("Failed to submit command [%ld]\n",
1343 ena_trc_err("Failed to submit command [%ld]\n",
1346 return PTR_ERR(comp_ctx);
1349 ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue);
1350 if (unlikely(ret)) {
1351 if (admin_queue->running_state)
1352 ena_trc_err("Failed to process command. ret = %d\n",
1355 ena_trc_dbg("Failed to process command. ret = %d\n",
1361 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
1362 struct ena_com_io_cq *io_cq)
1364 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1365 struct ena_admin_aq_create_cq_cmd create_cmd;
1366 struct ena_admin_acq_create_cq_resp_desc cmd_completion;
1369 memset(&create_cmd, 0x0, sizeof(create_cmd));
1371 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ;
1373 create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) &
1374 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1375 create_cmd.cq_caps_1 |=
1376 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1378 create_cmd.msix_vector = io_cq->msix_vector;
1379 create_cmd.cq_depth = io_cq->q_depth;
1381 ret = ena_com_mem_addr_set(ena_dev,
1383 io_cq->cdesc_addr.phys_addr);
1384 if (unlikely(ret)) {
1385 ena_trc_err("memory address set failed\n");
1389 ret = ena_com_execute_admin_command(admin_queue,
1390 (struct ena_admin_aq_entry *)&create_cmd,
1392 (struct ena_admin_acq_entry *)&cmd_completion,
1393 sizeof(cmd_completion));
1394 if (unlikely(ret)) {
1395 ena_trc_err("Failed to create IO CQ. error: %d\n", ret);
1399 io_cq->idx = cmd_completion.cq_idx;
1401 io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1402 cmd_completion.cq_interrupt_unmask_register_offset);
1404 if (cmd_completion.cq_head_db_register_offset)
1405 io_cq->cq_head_db_reg =
1406 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1407 cmd_completion.cq_head_db_register_offset);
1409 if (cmd_completion.numa_node_register_offset)
1410 io_cq->numa_node_cfg_reg =
1411 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1412 cmd_completion.numa_node_register_offset);
1414 ena_trc_dbg("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth);
1419 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
1420 struct ena_com_io_sq **io_sq,
1421 struct ena_com_io_cq **io_cq)
1423 if (qid >= ENA_TOTAL_NUM_QUEUES) {
1424 ena_trc_err("Invalid queue number %d but the max is %d\n",
1425 qid, ENA_TOTAL_NUM_QUEUES);
1426 return ENA_COM_INVAL;
1429 *io_sq = &ena_dev->io_sq_queues[qid];
1430 *io_cq = &ena_dev->io_cq_queues[qid];
1435 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev)
1437 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1438 struct ena_comp_ctx *comp_ctx;
1441 if (!admin_queue->comp_ctx)
1444 for (i = 0; i < admin_queue->q_depth; i++) {
1445 comp_ctx = get_comp_ctxt(admin_queue, i, false);
1446 if (unlikely(!comp_ctx))
1449 comp_ctx->status = ENA_CMD_ABORTED;
1451 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
1455 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)
1457 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1458 unsigned long flags = 0;
1460 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1461 while (ATOMIC32_READ(&admin_queue->outstanding_cmds) != 0) {
1462 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1463 ENA_MSLEEP(ENA_POLL_MS);
1464 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1466 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1469 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
1470 struct ena_com_io_cq *io_cq)
1472 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1473 struct ena_admin_aq_destroy_cq_cmd destroy_cmd;
1474 struct ena_admin_acq_destroy_cq_resp_desc destroy_resp;
1477 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
1479 destroy_cmd.cq_idx = io_cq->idx;
1480 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ;
1482 ret = ena_com_execute_admin_command(admin_queue,
1483 (struct ena_admin_aq_entry *)&destroy_cmd,
1484 sizeof(destroy_cmd),
1485 (struct ena_admin_acq_entry *)&destroy_resp,
1486 sizeof(destroy_resp));
1488 if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
1489 ena_trc_err("Failed to destroy IO CQ. error: %d\n", ret);
1494 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev)
1496 return ena_dev->admin_queue.running_state;
1499 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state)
1501 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1502 unsigned long flags = 0;
1504 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1505 ena_dev->admin_queue.running_state = state;
1506 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1509 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev)
1511 u16 depth = ena_dev->aenq.q_depth;
1513 ENA_WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");
1515 /* Init head_db to mark that all entries in the queue
1516 * are initially available
1518 ENA_REG_WRITE32(ena_dev->bus, depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1521 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)
1523 struct ena_com_admin_queue *admin_queue;
1524 struct ena_admin_set_feat_cmd cmd;
1525 struct ena_admin_set_feat_resp resp;
1526 struct ena_admin_get_feat_resp get_resp;
1529 ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0);
1531 ena_trc_info("Can't get aenq configuration\n");
1535 if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
1536 ena_trc_warn("Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n",
1537 get_resp.u.aenq.supported_groups,
1539 return ENA_COM_UNSUPPORTED;
1542 memset(&cmd, 0x0, sizeof(cmd));
1543 admin_queue = &ena_dev->admin_queue;
1545 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1546 cmd.aq_common_descriptor.flags = 0;
1547 cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG;
1548 cmd.u.aenq.enabled_groups = groups_flag;
1550 ret = ena_com_execute_admin_command(admin_queue,
1551 (struct ena_admin_aq_entry *)&cmd,
1553 (struct ena_admin_acq_entry *)&resp,
1557 ena_trc_err("Failed to config AENQ ret: %d\n", ret);
1562 int ena_com_get_dma_width(struct ena_com_dev *ena_dev)
1564 u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1567 if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) {
1568 ena_trc_err("Reg read timeout occurred\n");
1569 return ENA_COM_TIMER_EXPIRED;
1572 width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1573 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1575 ena_trc_dbg("ENA dma width: %d\n", width);
1577 if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) {
1578 ena_trc_err("DMA width illegal value: %d\n", width);
1579 return ENA_COM_INVAL;
1582 ena_dev->dma_addr_bits = width;
1587 int ena_com_validate_version(struct ena_com_dev *ena_dev)
1591 u32 ctrl_ver_masked;
1593 /* Make sure the ENA version and the controller version are at least
1594 * as the driver expects
1596 ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF);
1597 ctrl_ver = ena_com_reg_bar_read32(ena_dev,
1598 ENA_REGS_CONTROLLER_VERSION_OFF);
1600 if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) ||
1601 (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) {
1602 ena_trc_err("Reg read timeout occurred\n");
1603 return ENA_COM_TIMER_EXPIRED;
1606 ena_trc_info("ena device version: %d.%d\n",
1607 (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >>
1608 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT,
1609 ver & ENA_REGS_VERSION_MINOR_VERSION_MASK);
1611 ena_trc_info("ena controller version: %d.%d.%d implementation version %d\n",
1612 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK)
1613 >> ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
1614 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK)
1615 >> ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
1616 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
1617 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
1618 ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
1621 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
1622 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
1623 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
1625 /* Validate the ctrl version without the implementation ID */
1626 if (ctrl_ver_masked < MIN_ENA_CTRL_VER) {
1627 ena_trc_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n");
1634 void ena_com_admin_destroy(struct ena_com_dev *ena_dev)
1636 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1637 struct ena_com_admin_cq *cq = &admin_queue->cq;
1638 struct ena_com_admin_sq *sq = &admin_queue->sq;
1639 struct ena_com_aenq *aenq = &ena_dev->aenq;
1642 ENA_WAIT_EVENT_DESTROY(admin_queue->comp_ctx->wait_event);
1643 if (admin_queue->comp_ctx)
1644 ENA_MEM_FREE(ena_dev->dmadev,
1645 admin_queue->comp_ctx,
1646 (admin_queue->q_depth * sizeof(struct ena_comp_ctx)));
1647 admin_queue->comp_ctx = NULL;
1648 size = ADMIN_SQ_SIZE(admin_queue->q_depth);
1650 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, sq->entries,
1651 sq->dma_addr, sq->mem_handle);
1654 size = ADMIN_CQ_SIZE(admin_queue->q_depth);
1656 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, cq->entries,
1657 cq->dma_addr, cq->mem_handle);
1660 size = ADMIN_AENQ_SIZE(aenq->q_depth);
1661 if (ena_dev->aenq.entries)
1662 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, aenq->entries,
1663 aenq->dma_addr, aenq->mem_handle);
1664 aenq->entries = NULL;
1665 ENA_SPINLOCK_DESTROY(admin_queue->q_lock);
1668 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling)
1673 mask_value = ENA_REGS_ADMIN_INTR_MASK;
1675 ENA_REG_WRITE32(ena_dev->bus, mask_value,
1676 ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
1677 ena_dev->admin_queue.polling = polling;
1680 bool ena_com_get_admin_polling_mode(struct ena_com_dev * ena_dev)
1682 return ena_dev->admin_queue.polling;
1685 void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev,
1688 ena_dev->admin_queue.auto_polling = polling;
1691 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)
1693 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1695 ENA_SPINLOCK_INIT(mmio_read->lock);
1696 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1697 sizeof(*mmio_read->read_resp),
1698 mmio_read->read_resp,
1699 mmio_read->read_resp_dma_addr,
1700 mmio_read->read_resp_mem_handle);
1701 if (unlikely(!mmio_read->read_resp))
1704 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1706 mmio_read->read_resp->req_id = 0x0;
1707 mmio_read->seq_num = 0x0;
1708 mmio_read->readless_supported = true;
1713 ENA_SPINLOCK_DESTROY(mmio_read->lock);
1714 return ENA_COM_NO_MEM;
1717 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)
1719 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1721 mmio_read->readless_supported = readless_supported;
1724 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev)
1726 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1728 ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1729 ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1731 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1732 sizeof(*mmio_read->read_resp),
1733 mmio_read->read_resp,
1734 mmio_read->read_resp_dma_addr,
1735 mmio_read->read_resp_mem_handle);
1737 mmio_read->read_resp = NULL;
1738 ENA_SPINLOCK_DESTROY(mmio_read->lock);
1741 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev)
1743 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1744 u32 addr_low, addr_high;
1746 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);
1747 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);
1749 ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1750 ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1753 int ena_com_admin_init(struct ena_com_dev *ena_dev,
1754 struct ena_aenq_handlers *aenq_handlers)
1756 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1757 u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;
1760 dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1762 if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) {
1763 ena_trc_err("Reg read timeout occurred\n");
1764 return ENA_COM_TIMER_EXPIRED;
1767 if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) {
1768 ena_trc_err("Device isn't ready, abort com init\n");
1769 return ENA_COM_NO_DEVICE;
1772 admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH;
1774 admin_queue->bus = ena_dev->bus;
1775 admin_queue->q_dmadev = ena_dev->dmadev;
1776 admin_queue->polling = false;
1777 admin_queue->curr_cmd_id = 0;
1779 ATOMIC32_SET(&admin_queue->outstanding_cmds, 0);
1781 ENA_SPINLOCK_INIT(admin_queue->q_lock);
1783 ret = ena_com_init_comp_ctxt(admin_queue);
1787 ret = ena_com_admin_init_sq(admin_queue);
1791 ret = ena_com_admin_init_cq(admin_queue);
1795 admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1796 ENA_REGS_AQ_DB_OFF);
1798 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);
1799 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);
1801 ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);
1802 ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);
1804 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);
1805 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);
1807 ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);
1808 ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);
1811 aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
1812 aq_caps |= (sizeof(struct ena_admin_aq_entry) <<
1813 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
1814 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
1817 acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
1818 acq_caps |= (sizeof(struct ena_admin_acq_entry) <<
1819 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
1820 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
1822 ENA_REG_WRITE32(ena_dev->bus, aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);
1823 ENA_REG_WRITE32(ena_dev->bus, acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);
1824 ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers);
1828 admin_queue->running_state = true;
1832 ena_com_admin_destroy(ena_dev);
1837 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
1838 struct ena_com_create_io_ctx *ctx)
1840 struct ena_com_io_sq *io_sq;
1841 struct ena_com_io_cq *io_cq;
1844 if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {
1845 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1846 ctx->qid, ENA_TOTAL_NUM_QUEUES);
1847 return ENA_COM_INVAL;
1850 io_sq = &ena_dev->io_sq_queues[ctx->qid];
1851 io_cq = &ena_dev->io_cq_queues[ctx->qid];
1853 memset(io_sq, 0x0, sizeof(*io_sq));
1854 memset(io_cq, 0x0, sizeof(*io_cq));
1857 io_cq->q_depth = ctx->queue_size;
1858 io_cq->direction = ctx->direction;
1859 io_cq->qid = ctx->qid;
1861 io_cq->msix_vector = ctx->msix_vector;
1863 io_sq->q_depth = ctx->queue_size;
1864 io_sq->direction = ctx->direction;
1865 io_sq->qid = ctx->qid;
1867 io_sq->mem_queue_type = ctx->mem_queue_type;
1869 if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1870 /* header length is limited to 8 bits */
1871 io_sq->tx_max_header_size =
1872 ENA_MIN32(ena_dev->tx_max_header_size, SZ_256);
1874 ret = ena_com_init_io_sq(ena_dev, ctx, io_sq);
1877 ret = ena_com_init_io_cq(ena_dev, ctx, io_cq);
1881 ret = ena_com_create_io_cq(ena_dev, io_cq);
1885 ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx);
1892 ena_com_destroy_io_cq(ena_dev, io_cq);
1894 ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1898 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)
1900 struct ena_com_io_sq *io_sq;
1901 struct ena_com_io_cq *io_cq;
1903 if (qid >= ENA_TOTAL_NUM_QUEUES) {
1904 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1905 qid, ENA_TOTAL_NUM_QUEUES);
1909 io_sq = &ena_dev->io_sq_queues[qid];
1910 io_cq = &ena_dev->io_cq_queues[qid];
1912 ena_com_destroy_io_sq(ena_dev, io_sq);
1913 ena_com_destroy_io_cq(ena_dev, io_cq);
1915 ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1918 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
1919 struct ena_admin_get_feat_resp *resp)
1921 return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG, 0);
1924 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
1925 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1927 struct ena_admin_get_feat_resp get_resp;
1930 rc = ena_com_get_feature(ena_dev, &get_resp,
1931 ENA_ADMIN_DEVICE_ATTRIBUTES, 0);
1935 memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr,
1936 sizeof(get_resp.u.dev_attr));
1937 ena_dev->supported_features = get_resp.u.dev_attr.supported_features;
1939 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1940 rc = ena_com_get_feature(ena_dev, &get_resp,
1941 ENA_ADMIN_MAX_QUEUES_EXT,
1942 ENA_FEATURE_MAX_QUEUE_EXT_VER);
1946 if (get_resp.u.max_queue_ext.version != ENA_FEATURE_MAX_QUEUE_EXT_VER)
1949 memcpy(&get_feat_ctx->max_queue_ext, &get_resp.u.max_queue_ext,
1950 sizeof(get_resp.u.max_queue_ext));
1951 ena_dev->tx_max_header_size =
1952 get_resp.u.max_queue_ext.max_queue_ext.max_tx_header_size;
1954 rc = ena_com_get_feature(ena_dev, &get_resp,
1955 ENA_ADMIN_MAX_QUEUES_NUM, 0);
1956 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue,
1957 sizeof(get_resp.u.max_queue));
1958 ena_dev->tx_max_header_size =
1959 get_resp.u.max_queue.max_header_size;
1965 rc = ena_com_get_feature(ena_dev, &get_resp,
1966 ENA_ADMIN_AENQ_CONFIG, 0);
1970 memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,
1971 sizeof(get_resp.u.aenq));
1973 rc = ena_com_get_feature(ena_dev, &get_resp,
1974 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
1978 memcpy(&get_feat_ctx->offload, &get_resp.u.offload,
1979 sizeof(get_resp.u.offload));
1981 /* Driver hints isn't mandatory admin command. So in case the
1982 * command isn't supported set driver hints to 0
1984 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS, 0);
1987 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints,
1988 sizeof(get_resp.u.hw_hints));
1989 else if (rc == ENA_COM_UNSUPPORTED)
1990 memset(&get_feat_ctx->hw_hints, 0x0, sizeof(get_feat_ctx->hw_hints));
1994 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ, 0);
1996 memcpy(&get_feat_ctx->llq, &get_resp.u.llq,
1997 sizeof(get_resp.u.llq));
1998 else if (rc == ENA_COM_UNSUPPORTED)
1999 memset(&get_feat_ctx->llq, 0x0, sizeof(get_feat_ctx->llq));
2003 rc = ena_com_get_feature(ena_dev, &get_resp,
2004 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0);
2006 memcpy(&get_feat_ctx->ind_table, &get_resp.u.ind_table,
2007 sizeof(get_resp.u.ind_table));
2008 else if (rc == ENA_COM_UNSUPPORTED)
2009 memset(&get_feat_ctx->ind_table, 0x0,
2010 sizeof(get_feat_ctx->ind_table));
2017 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev)
2019 ena_com_handle_admin_completion(&ena_dev->admin_queue);
2022 /* ena_handle_specific_aenq_event:
2023 * return the handler that is relevant to the specific event group
2025 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev,
2028 struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers;
2030 if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group])
2031 return aenq_handlers->handlers[group];
2033 return aenq_handlers->unimplemented_handler;
2036 /* ena_aenq_intr_handler:
2037 * handles the aenq incoming events.
2038 * pop events from the queue and apply the specific handler
2040 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
2042 struct ena_admin_aenq_entry *aenq_e;
2043 struct ena_admin_aenq_common_desc *aenq_common;
2044 struct ena_com_aenq *aenq = &dev->aenq;
2046 ena_aenq_handler handler_cb;
2047 u16 masked_head, processed = 0;
2050 masked_head = aenq->head & (aenq->q_depth - 1);
2051 phase = aenq->phase;
2052 aenq_e = &aenq->entries[masked_head]; /* Get first entry */
2053 aenq_common = &aenq_e->aenq_common_desc;
2055 /* Go over all the events */
2056 while ((READ_ONCE8(aenq_common->flags) &
2057 ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) {
2058 /* Make sure the phase bit (ownership) is as expected before
2059 * reading the rest of the descriptor.
2063 timestamp = (u64)aenq_common->timestamp_low |
2064 ((u64)aenq_common->timestamp_high << 32);
2065 ENA_TOUCH(timestamp); /* In case debug is disabled */
2066 ena_trc_dbg("AENQ! Group[%x] Syndrom[%x] timestamp: [%" ENA_PRIu64 "s]\n",
2068 aenq_common->syndrom,
2071 /* Handle specific event*/
2072 handler_cb = ena_com_get_specific_aenq_cb(dev,
2073 aenq_common->group);
2074 handler_cb(data, aenq_e); /* call the actual event handler*/
2076 /* Get next event entry */
2080 if (unlikely(masked_head == aenq->q_depth)) {
2084 aenq_e = &aenq->entries[masked_head];
2085 aenq_common = &aenq_e->aenq_common_desc;
2088 aenq->head += processed;
2089 aenq->phase = phase;
2091 /* Don't update aenq doorbell if there weren't any processed events */
2095 /* write the aenq doorbell after all AENQ descriptors were read */
2097 ENA_REG_WRITE32_RELAXED(dev->bus, (u32)aenq->head,
2098 dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
2099 #ifndef MMIOWB_NOT_DEFINED
2104 int ena_com_dev_reset(struct ena_com_dev *ena_dev,
2105 enum ena_regs_reset_reason_types reset_reason)
2107 u32 stat, timeout, cap, reset_val;
2110 stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
2111 cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
2113 if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) ||
2114 (cap == ENA_MMIO_READ_TIMEOUT))) {
2115 ena_trc_err("Reg read32 timeout occurred\n");
2116 return ENA_COM_TIMER_EXPIRED;
2119 if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) {
2120 ena_trc_err("Device isn't ready, can't reset device\n");
2121 return ENA_COM_INVAL;
2124 timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
2125 ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
2127 ena_trc_err("Invalid timeout value\n");
2128 return ENA_COM_INVAL;
2132 reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;
2133 reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
2134 ENA_REGS_DEV_CTL_RESET_REASON_MASK;
2135 ENA_REG_WRITE32(ena_dev->bus, reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2137 /* Write again the MMIO read request address */
2138 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
2140 rc = wait_for_reset_state(ena_dev, timeout,
2141 ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
2143 ena_trc_err("Reset indication didn't turn on\n");
2148 ENA_REG_WRITE32(ena_dev->bus, 0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2149 rc = wait_for_reset_state(ena_dev, timeout, 0);
2151 ena_trc_err("Reset indication didn't turn off\n");
2155 timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
2156 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
2158 /* the resolution of timeout reg is 100ms */
2159 ena_dev->admin_queue.completion_timeout = timeout * 100000;
2161 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US;
2166 static int ena_get_dev_stats(struct ena_com_dev *ena_dev,
2167 struct ena_com_stats_ctx *ctx,
2168 enum ena_admin_get_stats_type type)
2170 struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd;
2171 struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp;
2172 struct ena_com_admin_queue *admin_queue;
2175 admin_queue = &ena_dev->admin_queue;
2177 get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS;
2178 get_cmd->aq_common_descriptor.flags = 0;
2179 get_cmd->type = type;
2181 ret = ena_com_execute_admin_command(admin_queue,
2182 (struct ena_admin_aq_entry *)get_cmd,
2184 (struct ena_admin_acq_entry *)get_resp,
2188 ena_trc_err("Failed to get stats. error: %d\n", ret);
2193 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
2194 struct ena_admin_basic_stats *stats)
2196 struct ena_com_stats_ctx ctx;
2199 memset(&ctx, 0x0, sizeof(ctx));
2200 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC);
2201 if (likely(ret == 0))
2202 memcpy(stats, &ctx.get_resp.basic_stats,
2203 sizeof(ctx.get_resp.basic_stats));
2208 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu)
2210 struct ena_com_admin_queue *admin_queue;
2211 struct ena_admin_set_feat_cmd cmd;
2212 struct ena_admin_set_feat_resp resp;
2215 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) {
2216 ena_trc_dbg("Feature %d isn't supported\n", ENA_ADMIN_MTU);
2217 return ENA_COM_UNSUPPORTED;
2220 memset(&cmd, 0x0, sizeof(cmd));
2221 admin_queue = &ena_dev->admin_queue;
2223 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2224 cmd.aq_common_descriptor.flags = 0;
2225 cmd.feat_common.feature_id = ENA_ADMIN_MTU;
2226 cmd.u.mtu.mtu = mtu;
2228 ret = ena_com_execute_admin_command(admin_queue,
2229 (struct ena_admin_aq_entry *)&cmd,
2231 (struct ena_admin_acq_entry *)&resp,
2235 ena_trc_err("Failed to set mtu %d. error: %d\n", mtu, ret);
2240 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
2241 struct ena_admin_feature_offload_desc *offload)
2244 struct ena_admin_get_feat_resp resp;
2246 ret = ena_com_get_feature(ena_dev, &resp,
2247 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
2248 if (unlikely(ret)) {
2249 ena_trc_err("Failed to get offload capabilities %d\n", ret);
2253 memcpy(offload, &resp.u.offload, sizeof(resp.u.offload));
2258 int ena_com_set_hash_function(struct ena_com_dev *ena_dev)
2260 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2261 struct ena_rss *rss = &ena_dev->rss;
2262 struct ena_admin_set_feat_cmd cmd;
2263 struct ena_admin_set_feat_resp resp;
2264 struct ena_admin_get_feat_resp get_resp;
2267 if (!ena_com_check_supported_feature_id(ena_dev,
2268 ENA_ADMIN_RSS_HASH_FUNCTION)) {
2269 ena_trc_dbg("Feature %d isn't supported\n",
2270 ENA_ADMIN_RSS_HASH_FUNCTION);
2271 return ENA_COM_UNSUPPORTED;
2274 /* Validate hash function is supported */
2275 ret = ena_com_get_feature(ena_dev, &get_resp,
2276 ENA_ADMIN_RSS_HASH_FUNCTION, 0);
2280 if (!(get_resp.u.flow_hash_func.supported_func & BIT(rss->hash_func))) {
2281 ena_trc_err("Func hash %d isn't supported by device, abort\n",
2283 return ENA_COM_UNSUPPORTED;
2286 memset(&cmd, 0x0, sizeof(cmd));
2288 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2289 cmd.aq_common_descriptor.flags =
2290 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2291 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION;
2292 cmd.u.flow_hash_func.init_val = rss->hash_init_val;
2293 cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func;
2295 ret = ena_com_mem_addr_set(ena_dev,
2296 &cmd.control_buffer.address,
2297 rss->hash_key_dma_addr);
2298 if (unlikely(ret)) {
2299 ena_trc_err("memory address set failed\n");
2303 cmd.control_buffer.length = sizeof(*rss->hash_key);
2305 ret = ena_com_execute_admin_command(admin_queue,
2306 (struct ena_admin_aq_entry *)&cmd,
2308 (struct ena_admin_acq_entry *)&resp,
2310 if (unlikely(ret)) {
2311 ena_trc_err("Failed to set hash function %d. error: %d\n",
2312 rss->hash_func, ret);
2313 return ENA_COM_INVAL;
2319 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
2320 enum ena_admin_hash_functions func,
2321 const u8 *key, u16 key_len, u32 init_val)
2323 struct ena_admin_feature_rss_flow_hash_control *hash_key;
2324 struct ena_admin_get_feat_resp get_resp;
2325 enum ena_admin_hash_functions old_func;
2326 struct ena_rss *rss = &ena_dev->rss;
2329 hash_key = rss->hash_key;
2331 /* Make sure size is a mult of DWs */
2332 if (unlikely(key_len & 0x3))
2333 return ENA_COM_INVAL;
2335 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2336 ENA_ADMIN_RSS_HASH_FUNCTION,
2337 rss->hash_key_dma_addr,
2338 sizeof(*rss->hash_key), 0);
2342 if (!(BIT(func) & get_resp.u.flow_hash_func.supported_func)) {
2343 ena_trc_err("Flow hash function %d isn't supported\n", func);
2344 return ENA_COM_UNSUPPORTED;
2348 case ENA_ADMIN_TOEPLITZ:
2350 if (key_len != sizeof(hash_key->key)) {
2351 ena_trc_err("key len (%hu) doesn't equal the supported size (%zu)\n",
2352 key_len, sizeof(hash_key->key));
2353 return ENA_COM_INVAL;
2355 memcpy(hash_key->key, key, key_len);
2356 rss->hash_init_val = init_val;
2357 hash_key->keys_num = key_len / sizeof(u32);
2360 case ENA_ADMIN_CRC32:
2361 rss->hash_init_val = init_val;
2364 ena_trc_err("Invalid hash function (%d)\n", func);
2365 return ENA_COM_INVAL;
2368 old_func = rss->hash_func;
2369 rss->hash_func = func;
2370 rc = ena_com_set_hash_function(ena_dev);
2372 /* Restore the old function */
2374 rss->hash_func = old_func;
2379 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
2380 enum ena_admin_hash_functions *func,
2383 struct ena_rss *rss = &ena_dev->rss;
2384 struct ena_admin_get_feat_resp get_resp;
2385 struct ena_admin_feature_rss_flow_hash_control *hash_key =
2389 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2390 ENA_ADMIN_RSS_HASH_FUNCTION,
2391 rss->hash_key_dma_addr,
2392 sizeof(*rss->hash_key), 0);
2396 /* ENA_FFS returns 1 in case the lsb is set */
2397 rss->hash_func = ENA_FFS(get_resp.u.flow_hash_func.selected_func);
2402 *func = rss->hash_func;
2405 memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2);
2410 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
2411 enum ena_admin_flow_hash_proto proto,
2414 struct ena_rss *rss = &ena_dev->rss;
2415 struct ena_admin_get_feat_resp get_resp;
2418 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2419 ENA_ADMIN_RSS_HASH_INPUT,
2420 rss->hash_ctrl_dma_addr,
2421 sizeof(*rss->hash_ctrl), 0);
2426 *fields = rss->hash_ctrl->selected_fields[proto].fields;
2431 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev)
2433 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2434 struct ena_rss *rss = &ena_dev->rss;
2435 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2436 struct ena_admin_set_feat_cmd cmd;
2437 struct ena_admin_set_feat_resp resp;
2440 if (!ena_com_check_supported_feature_id(ena_dev,
2441 ENA_ADMIN_RSS_HASH_INPUT)) {
2442 ena_trc_dbg("Feature %d isn't supported\n",
2443 ENA_ADMIN_RSS_HASH_INPUT);
2444 return ENA_COM_UNSUPPORTED;
2447 memset(&cmd, 0x0, sizeof(cmd));
2449 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2450 cmd.aq_common_descriptor.flags =
2451 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2452 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT;
2453 cmd.u.flow_hash_input.enabled_input_sort =
2454 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK |
2455 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
2457 ret = ena_com_mem_addr_set(ena_dev,
2458 &cmd.control_buffer.address,
2459 rss->hash_ctrl_dma_addr);
2460 if (unlikely(ret)) {
2461 ena_trc_err("memory address set failed\n");
2464 cmd.control_buffer.length = sizeof(*hash_ctrl);
2466 ret = ena_com_execute_admin_command(admin_queue,
2467 (struct ena_admin_aq_entry *)&cmd,
2469 (struct ena_admin_acq_entry *)&resp,
2472 ena_trc_err("Failed to set hash input. error: %d\n", ret);
2477 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)
2479 struct ena_rss *rss = &ena_dev->rss;
2480 struct ena_admin_feature_rss_hash_control *hash_ctrl =
2482 u16 available_fields = 0;
2485 /* Get the supported hash input */
2486 rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2490 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields =
2491 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2492 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2494 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields =
2495 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2496 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2498 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields =
2499 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2500 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2502 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields =
2503 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2504 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2506 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields =
2507 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2509 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields =
2510 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2512 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =
2513 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2515 hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields =
2516 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA;
2518 for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) {
2519 available_fields = hash_ctrl->selected_fields[i].fields &
2520 hash_ctrl->supported_fields[i].fields;
2521 if (available_fields != hash_ctrl->selected_fields[i].fields) {
2522 ena_trc_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n",
2523 i, hash_ctrl->supported_fields[i].fields,
2524 hash_ctrl->selected_fields[i].fields);
2525 return ENA_COM_UNSUPPORTED;
2529 rc = ena_com_set_hash_ctrl(ena_dev);
2531 /* In case of failure, restore the old hash ctrl */
2533 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2538 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
2539 enum ena_admin_flow_hash_proto proto,
2542 struct ena_rss *rss = &ena_dev->rss;
2543 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2544 u16 supported_fields;
2547 if (proto >= ENA_ADMIN_RSS_PROTO_NUM) {
2548 ena_trc_err("Invalid proto num (%u)\n", proto);
2549 return ENA_COM_INVAL;
2552 /* Get the ctrl table */
2553 rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL);
2557 /* Make sure all the fields are supported */
2558 supported_fields = hash_ctrl->supported_fields[proto].fields;
2559 if ((hash_fields & supported_fields) != hash_fields) {
2560 ena_trc_err("proto %d doesn't support the required fields %x. supports only: %x\n",
2561 proto, hash_fields, supported_fields);
2564 hash_ctrl->selected_fields[proto].fields = hash_fields;
2566 rc = ena_com_set_hash_ctrl(ena_dev);
2568 /* In case of failure, restore the old hash ctrl */
2570 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2575 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
2576 u16 entry_idx, u16 entry_value)
2578 struct ena_rss *rss = &ena_dev->rss;
2580 if (unlikely(entry_idx >= (1 << rss->tbl_log_size)))
2581 return ENA_COM_INVAL;
2583 if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES)))
2584 return ENA_COM_INVAL;
2586 rss->host_rss_ind_tbl[entry_idx] = entry_value;
2591 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)
2593 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2594 struct ena_rss *rss = &ena_dev->rss;
2595 struct ena_admin_set_feat_cmd cmd;
2596 struct ena_admin_set_feat_resp resp;
2599 if (!ena_com_check_supported_feature_id(ena_dev,
2600 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) {
2601 ena_trc_dbg("Feature %d isn't supported\n",
2602 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
2603 return ENA_COM_UNSUPPORTED;
2606 ret = ena_com_ind_tbl_convert_to_device(ena_dev);
2608 ena_trc_err("Failed to convert host indirection table to device table\n");
2612 memset(&cmd, 0x0, sizeof(cmd));
2614 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2615 cmd.aq_common_descriptor.flags =
2616 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2617 cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG;
2618 cmd.u.ind_table.size = rss->tbl_log_size;
2619 cmd.u.ind_table.inline_index = 0xFFFFFFFF;
2621 ret = ena_com_mem_addr_set(ena_dev,
2622 &cmd.control_buffer.address,
2623 rss->rss_ind_tbl_dma_addr);
2624 if (unlikely(ret)) {
2625 ena_trc_err("memory address set failed\n");
2629 cmd.control_buffer.length = (1ULL << rss->tbl_log_size) *
2630 sizeof(struct ena_admin_rss_ind_table_entry);
2632 ret = ena_com_execute_admin_command(admin_queue,
2633 (struct ena_admin_aq_entry *)&cmd,
2635 (struct ena_admin_acq_entry *)&resp,
2639 ena_trc_err("Failed to set indirect table. error: %d\n", ret);
2644 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)
2646 struct ena_rss *rss = &ena_dev->rss;
2647 struct ena_admin_get_feat_resp get_resp;
2651 tbl_size = (1ULL << rss->tbl_log_size) *
2652 sizeof(struct ena_admin_rss_ind_table_entry);
2654 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2655 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG,
2656 rss->rss_ind_tbl_dma_addr,
2664 for (i = 0; i < (1 << rss->tbl_log_size); i++)
2665 ind_tbl[i] = rss->host_rss_ind_tbl[i];
2670 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size)
2674 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2676 rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size);
2680 rc = ena_com_hash_key_allocate(ena_dev);
2684 ena_com_hash_key_fill_default_key(ena_dev);
2686 rc = ena_com_hash_ctrl_init(ena_dev);
2693 ena_com_hash_key_destroy(ena_dev);
2695 ena_com_indirect_table_destroy(ena_dev);
2701 void ena_com_rss_destroy(struct ena_com_dev *ena_dev)
2703 ena_com_indirect_table_destroy(ena_dev);
2704 ena_com_hash_key_destroy(ena_dev);
2705 ena_com_hash_ctrl_destroy(ena_dev);
2707 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2710 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
2712 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2714 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2716 host_attr->host_info,
2717 host_attr->host_info_dma_addr,
2718 host_attr->host_info_dma_handle);
2719 if (unlikely(!host_attr->host_info))
2720 return ENA_COM_NO_MEM;
2722 host_attr->host_info->ena_spec_version = ((ENA_COMMON_SPEC_VERSION_MAJOR <<
2723 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) |
2724 (ENA_COMMON_SPEC_VERSION_MINOR));
2729 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
2730 u32 debug_area_size)
2732 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2734 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2736 host_attr->debug_area_virt_addr,
2737 host_attr->debug_area_dma_addr,
2738 host_attr->debug_area_dma_handle);
2739 if (unlikely(!host_attr->debug_area_virt_addr)) {
2740 host_attr->debug_area_size = 0;
2741 return ENA_COM_NO_MEM;
2744 host_attr->debug_area_size = debug_area_size;
2749 void ena_com_delete_host_info(struct ena_com_dev *ena_dev)
2751 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2753 if (host_attr->host_info) {
2754 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2756 host_attr->host_info,
2757 host_attr->host_info_dma_addr,
2758 host_attr->host_info_dma_handle);
2759 host_attr->host_info = NULL;
2763 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev)
2765 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2767 if (host_attr->debug_area_virt_addr) {
2768 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2769 host_attr->debug_area_size,
2770 host_attr->debug_area_virt_addr,
2771 host_attr->debug_area_dma_addr,
2772 host_attr->debug_area_dma_handle);
2773 host_attr->debug_area_virt_addr = NULL;
2777 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)
2779 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2780 struct ena_com_admin_queue *admin_queue;
2781 struct ena_admin_set_feat_cmd cmd;
2782 struct ena_admin_set_feat_resp resp;
2786 /* Host attribute config is called before ena_com_get_dev_attr_feat
2787 * so ena_com can't check if the feature is supported.
2790 memset(&cmd, 0x0, sizeof(cmd));
2791 admin_queue = &ena_dev->admin_queue;
2793 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2794 cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG;
2796 ret = ena_com_mem_addr_set(ena_dev,
2797 &cmd.u.host_attr.debug_ba,
2798 host_attr->debug_area_dma_addr);
2799 if (unlikely(ret)) {
2800 ena_trc_err("memory address set failed\n");
2804 ret = ena_com_mem_addr_set(ena_dev,
2805 &cmd.u.host_attr.os_info_ba,
2806 host_attr->host_info_dma_addr);
2807 if (unlikely(ret)) {
2808 ena_trc_err("memory address set failed\n");
2812 cmd.u.host_attr.debug_area_size = host_attr->debug_area_size;
2814 ret = ena_com_execute_admin_command(admin_queue,
2815 (struct ena_admin_aq_entry *)&cmd,
2817 (struct ena_admin_acq_entry *)&resp,
2821 ena_trc_err("Failed to set host attributes: %d\n", ret);
2826 /* Interrupt moderation */
2827 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev)
2829 return ena_com_check_supported_feature_id(ena_dev,
2830 ENA_ADMIN_INTERRUPT_MODERATION);
2833 static int ena_com_update_nonadaptive_moderation_interval(u32 coalesce_usecs,
2834 u32 intr_delay_resolution,
2835 u32 *intr_moder_interval)
2837 if (!intr_delay_resolution) {
2838 ena_trc_err("Illegal interrupt delay granularity value\n");
2839 return ENA_COM_FAULT;
2842 *intr_moder_interval = coalesce_usecs / intr_delay_resolution;
2848 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
2849 u32 tx_coalesce_usecs)
2851 return ena_com_update_nonadaptive_moderation_interval(tx_coalesce_usecs,
2852 ena_dev->intr_delay_resolution,
2853 &ena_dev->intr_moder_tx_interval);
2856 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
2857 u32 rx_coalesce_usecs)
2859 return ena_com_update_nonadaptive_moderation_interval(rx_coalesce_usecs,
2860 ena_dev->intr_delay_resolution,
2861 &ena_dev->intr_moder_rx_interval);
2864 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)
2866 struct ena_admin_get_feat_resp get_resp;
2867 u16 delay_resolution;
2870 rc = ena_com_get_feature(ena_dev, &get_resp,
2871 ENA_ADMIN_INTERRUPT_MODERATION, 0);
2874 if (rc == ENA_COM_UNSUPPORTED) {
2875 ena_trc_dbg("Feature %d isn't supported\n",
2876 ENA_ADMIN_INTERRUPT_MODERATION);
2879 ena_trc_err("Failed to get interrupt moderation admin cmd. rc: %d\n",
2883 /* no moderation supported, disable adaptive support */
2884 ena_com_disable_adaptive_moderation(ena_dev);
2888 /* if moderation is supported by device we set adaptive moderation */
2889 delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution;
2890 ena_com_update_intr_delay_resolution(ena_dev, delay_resolution);
2892 /* Disable adaptive moderation by default - can be enabled later */
2893 ena_com_disable_adaptive_moderation(ena_dev);
2898 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev)
2900 return ena_dev->intr_moder_tx_interval;
2903 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev)
2905 return ena_dev->intr_moder_rx_interval;
2908 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
2909 struct ena_admin_feature_llq_desc *llq_features,
2910 struct ena_llq_configurations *llq_default_cfg)
2913 struct ena_com_llq_info *llq_info = &(ena_dev->llq_info);;
2915 if (!llq_features->max_llq_num) {
2916 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
2920 rc = ena_com_config_llq_info(ena_dev, llq_features, llq_default_cfg);
2924 ena_dev->tx_max_header_size = llq_info->desc_list_entry_size -
2925 (llq_info->descs_num_before_header * sizeof(struct ena_eth_io_tx_desc));
2927 if (ena_dev->tx_max_header_size == 0) {
2928 ena_trc_err("the size of the LLQ entry is smaller than needed\n");
2932 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;