1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates.
9 enum ena_regs_reset_reason_types {
10 ENA_REGS_RESET_NORMAL = 0,
11 ENA_REGS_RESET_KEEP_ALIVE_TO = 1,
12 ENA_REGS_RESET_ADMIN_TO = 2,
13 ENA_REGS_RESET_MISS_TX_CMPL = 3,
14 ENA_REGS_RESET_INV_RX_REQ_ID = 4,
15 ENA_REGS_RESET_INV_TX_REQ_ID = 5,
16 ENA_REGS_RESET_TOO_MANY_RX_DESCS = 6,
17 ENA_REGS_RESET_INIT_ERR = 7,
18 ENA_REGS_RESET_DRIVER_INVALID_STATE = 8,
19 ENA_REGS_RESET_OS_TRIGGER = 9,
20 ENA_REGS_RESET_OS_NETDEV_WD = 10,
21 ENA_REGS_RESET_SHUTDOWN = 11,
22 ENA_REGS_RESET_USER_TRIGGER = 12,
23 ENA_REGS_RESET_GENERIC = 13,
24 ENA_REGS_RESET_MISS_INTERRUPT = 14,
28 /* ena_registers offsets */
31 #define ENA_REGS_VERSION_OFF 0x0
32 #define ENA_REGS_CONTROLLER_VERSION_OFF 0x4
33 #define ENA_REGS_CAPS_OFF 0x8
34 #define ENA_REGS_CAPS_EXT_OFF 0xc
35 #define ENA_REGS_AQ_BASE_LO_OFF 0x10
36 #define ENA_REGS_AQ_BASE_HI_OFF 0x14
37 #define ENA_REGS_AQ_CAPS_OFF 0x18
38 #define ENA_REGS_ACQ_BASE_LO_OFF 0x20
39 #define ENA_REGS_ACQ_BASE_HI_OFF 0x24
40 #define ENA_REGS_ACQ_CAPS_OFF 0x28
41 #define ENA_REGS_AQ_DB_OFF 0x2c
42 #define ENA_REGS_ACQ_TAIL_OFF 0x30
43 #define ENA_REGS_AENQ_CAPS_OFF 0x34
44 #define ENA_REGS_AENQ_BASE_LO_OFF 0x38
45 #define ENA_REGS_AENQ_BASE_HI_OFF 0x3c
46 #define ENA_REGS_AENQ_HEAD_DB_OFF 0x40
47 #define ENA_REGS_AENQ_TAIL_OFF 0x44
48 #define ENA_REGS_INTR_MASK_OFF 0x4c
49 #define ENA_REGS_DEV_CTL_OFF 0x54
50 #define ENA_REGS_DEV_STS_OFF 0x58
51 #define ENA_REGS_MMIO_REG_READ_OFF 0x5c
52 #define ENA_REGS_MMIO_RESP_LO_OFF 0x60
53 #define ENA_REGS_MMIO_RESP_HI_OFF 0x64
54 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_OFF 0x68
56 /* version register */
57 #define ENA_REGS_VERSION_MINOR_VERSION_MASK 0xff
58 #define ENA_REGS_VERSION_MAJOR_VERSION_SHIFT 8
59 #define ENA_REGS_VERSION_MAJOR_VERSION_MASK 0xff00
61 /* controller_version register */
62 #define ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK 0xff
63 #define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT 8
64 #define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK 0xff00
65 #define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT 16
66 #define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK 0xff0000
67 #define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT 24
68 #define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK 0xff000000
71 #define ENA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK 0x1
72 #define ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT 1
73 #define ENA_REGS_CAPS_RESET_TIMEOUT_MASK 0x3e
74 #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT 8
75 #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK 0xff00
76 #define ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT 16
77 #define ENA_REGS_CAPS_ADMIN_CMD_TO_MASK 0xf0000
79 /* aq_caps register */
80 #define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK 0xffff
81 #define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT 16
82 #define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK 0xffff0000
84 /* acq_caps register */
85 #define ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK 0xffff
86 #define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT 16
87 #define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK 0xffff0000
89 /* aenq_caps register */
90 #define ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK 0xffff
91 #define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT 16
92 #define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK 0xffff0000
94 /* dev_ctl register */
95 #define ENA_REGS_DEV_CTL_DEV_RESET_MASK 0x1
96 #define ENA_REGS_DEV_CTL_AQ_RESTART_SHIFT 1
97 #define ENA_REGS_DEV_CTL_AQ_RESTART_MASK 0x2
98 #define ENA_REGS_DEV_CTL_QUIESCENT_SHIFT 2
99 #define ENA_REGS_DEV_CTL_QUIESCENT_MASK 0x4
100 #define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT 3
101 #define ENA_REGS_DEV_CTL_IO_RESUME_MASK 0x8
102 #define ENA_REGS_DEV_CTL_RESET_REASON_SHIFT 28
103 #define ENA_REGS_DEV_CTL_RESET_REASON_MASK 0xf0000000
105 /* dev_sts register */
106 #define ENA_REGS_DEV_STS_READY_MASK 0x1
107 #define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT 1
108 #define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK 0x2
109 #define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_SHIFT 2
110 #define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK 0x4
111 #define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_SHIFT 3
112 #define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK 0x8
113 #define ENA_REGS_DEV_STS_RESET_FINISHED_SHIFT 4
114 #define ENA_REGS_DEV_STS_RESET_FINISHED_MASK 0x10
115 #define ENA_REGS_DEV_STS_FATAL_ERROR_SHIFT 5
116 #define ENA_REGS_DEV_STS_FATAL_ERROR_MASK 0x20
117 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_SHIFT 6
118 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK 0x40
119 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_SHIFT 7
120 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK 0x80
122 /* mmio_reg_read register */
123 #define ENA_REGS_MMIO_REG_READ_REQ_ID_MASK 0xffff
124 #define ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT 16
125 #define ENA_REGS_MMIO_REG_READ_REG_OFF_MASK 0xffff0000
127 /* rss_ind_entry_update register */
128 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_INDEX_MASK 0xffff
129 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_SHIFT 16
130 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK 0xffff0000
132 #endif /* _ENA_REGS_H_ */