4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <sys/types.h>
40 #include <sys/queue.h>
45 #include <rte_common.h>
46 #include <rte_byteorder.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
50 #include <rte_tailq.h>
52 #include <rte_per_lcore.h>
53 #include <rte_launch.h>
54 #include <rte_atomic.h>
55 #include <rte_cycles.h>
56 #include <rte_prefetch.h>
57 #include <rte_lcore.h>
58 #include <rte_per_lcore.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_interrupts.h>
62 #include <rte_random.h>
63 #include <rte_debug.h>
64 #include <rte_ether.h>
65 #include <rte_ethdev.h>
67 #include <rte_mempool.h>
70 #include <rte_string_fns.h>
75 #define MBUF_SIZE (2048 + sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM)
76 #define NB_MBUF (32 * 1024)
79 * RX and TX Prefetch, Host, and Write-back threshold values should be
80 * carefully set for optimal performance. Consult the network
81 * controller's datasheet and supporting DPDK documentation for guidance
82 * on how these parameters should be set.
84 #define RX_PTHRESH 8 /**< Default values of RX prefetch threshold reg. */
85 #define RX_HTHRESH 8 /**< Default values of RX host threshold reg. */
86 #define RX_WTHRESH 4 /**< Default values of RX write-back threshold reg. */
89 * These default values are optimized for use with the Intel(R) 82599 10 GbE
90 * Controller and the DPDK ixgbe PMD. Consider using other values for other
91 * network controllers and/or network drivers.
93 #define TX_PTHRESH 36 /**< Default values of TX prefetch threshold reg. */
94 #define TX_HTHRESH 0 /**< Default values of TX host threshold reg. */
95 #define TX_WTHRESH 0 /**< Default values of TX write-back threshold reg. */
97 #define MAX_PKT_BURST 32
98 #define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */
100 #define TX_QUEUE_FLUSH_MASK 0xFFFFFFFF
101 #define TSC_COUNT_LIMIT 1000
103 #define ACTION_ENCRYPT 1
104 #define ACTION_DECRYPT 2
107 * Configurable number of RX/TX ring descriptors
109 #define RTE_TEST_RX_DESC_DEFAULT 128
110 #define RTE_TEST_TX_DESC_DEFAULT 512
111 static uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT;
112 static uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;
114 /* ethernet addresses of ports */
115 static struct ether_addr ports_eth_addr[RTE_MAX_ETHPORTS];
117 /* mask of enabled ports */
118 static unsigned enabled_port_mask = 0;
119 static int promiscuous_on = 1; /**< Ports set in promiscuous mode on by default. */
121 /* list of enabled ports */
122 static uint32_t dst_ports[RTE_MAX_ETHPORTS];
126 struct rte_mbuf *m_table[MAX_PKT_BURST];
129 struct lcore_rx_queue {
134 #define MAX_RX_QUEUE_PER_LCORE 16
136 #define MAX_LCORE_PARAMS 1024
137 struct lcore_params {
143 static struct lcore_params lcore_params_array[MAX_LCORE_PARAMS];
144 static struct lcore_params lcore_params_array_default[] = {
156 static struct lcore_params * lcore_params = lcore_params_array_default;
157 static uint16_t nb_lcore_params = sizeof(lcore_params_array_default) /
158 sizeof(lcore_params_array_default[0]);
160 static struct rte_eth_conf port_conf = {
163 .header_split = 0, /**< Header Split disabled */
164 .hw_ip_checksum = 1, /**< IP checksum offload enabled */
165 .hw_vlan_filter = 0, /**< VLAN filtering disabled */
166 .jumbo_frame = 0, /**< Jumbo Frame Support disabled */
167 .hw_strip_crc = 0, /**< CRC stripped by hardware */
172 .rss_hf = ETH_RSS_IPV4 | ETH_RSS_IPV6,
176 .mq_mode = ETH_MQ_TX_NONE,
180 static const struct rte_eth_rxconf rx_conf = {
182 .pthresh = RX_PTHRESH,
183 .hthresh = RX_HTHRESH,
184 .wthresh = RX_WTHRESH,
188 static const struct rte_eth_txconf tx_conf = {
190 .pthresh = TX_PTHRESH,
191 .hthresh = TX_HTHRESH,
192 .wthresh = TX_WTHRESH,
194 .tx_free_thresh = 0, /* Use PMD default values */
195 .tx_rs_thresh = 0, /* Use PMD default values */
198 static struct rte_mempool * pktmbuf_pool[RTE_MAX_NUMA_NODES];
205 uint16_t rx_queue_list_pos;
206 struct lcore_rx_queue rx_queue_list[MAX_RX_QUEUE_PER_LCORE];
207 uint16_t tx_queue_id[RTE_MAX_ETHPORTS];
208 struct mbuf_table rx_mbuf;
209 uint32_t rx_mbuf_pos;
210 uint32_t rx_curr_queue;
211 struct mbuf_table tx_mbufs[RTE_MAX_ETHPORTS];
212 } __rte_cache_aligned;
214 static struct lcore_conf lcore_conf[RTE_MAX_LCORE];
216 static inline struct rte_mbuf *
217 nic_rx_get_packet(struct lcore_conf *qconf)
219 struct rte_mbuf *pkt;
221 if (unlikely(qconf->n_rx_queue == 0))
224 /* Look for the next queue with packets; return if none */
225 if (unlikely(qconf->rx_mbuf_pos == qconf->rx_mbuf.len)) {
228 qconf->rx_mbuf_pos = 0;
229 for (i = 0; i < qconf->n_rx_queue; i++) {
230 qconf->rx_mbuf.len = rte_eth_rx_burst(
231 qconf->rx_queue_list[qconf->rx_curr_queue].port_id,
232 qconf->rx_queue_list[qconf->rx_curr_queue].queue_id,
233 qconf->rx_mbuf.m_table, MAX_PKT_BURST);
235 qconf->rx_curr_queue++;
236 if (unlikely(qconf->rx_curr_queue == qconf->n_rx_queue))
237 qconf->rx_curr_queue = 0;
238 if (likely(qconf->rx_mbuf.len > 0))
241 if (unlikely(i == qconf->n_rx_queue))
245 /* Get the next packet from the current queue; if last packet, go to next queue */
246 pkt = qconf->rx_mbuf.m_table[qconf->rx_mbuf_pos];
247 qconf->rx_mbuf_pos++;
253 nic_tx_flush_queues(struct lcore_conf *qconf)
257 for (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {
258 struct rte_mbuf **m_table = NULL;
259 uint16_t queueid, len;
262 if (likely((qconf->tx_mask & (1 << portid)) == 0))
265 len = qconf->tx_mbufs[portid].len;
266 if (likely(len == 0))
269 queueid = qconf->tx_queue_id[portid];
270 m_table = qconf->tx_mbufs[portid].m_table;
272 n = rte_eth_tx_burst(portid, queueid, m_table, len);
273 for (i = n; i < len; i++){
274 rte_pktmbuf_free(m_table[i]);
277 qconf->tx_mbufs[portid].len = 0;
280 qconf->tx_mask = TX_QUEUE_FLUSH_MASK;
284 nic_tx_send_packet(struct rte_mbuf *pkt, uint8_t port)
286 struct lcore_conf *qconf;
290 if (unlikely(pkt == NULL)) {
294 lcoreid = rte_lcore_id();
295 qconf = &lcore_conf[lcoreid];
297 len = qconf->tx_mbufs[port].len;
298 qconf->tx_mbufs[port].m_table[len] = pkt;
301 /* enough pkts to be sent */
302 if (unlikely(len == MAX_PKT_BURST)) {
306 queueid = qconf->tx_queue_id[port];
307 n = rte_eth_tx_burst(port, queueid, qconf->tx_mbufs[port].m_table, MAX_PKT_BURST);
308 for (i = n; i < MAX_PKT_BURST; i++){
309 rte_pktmbuf_free(qconf->tx_mbufs[port].m_table[i]);
312 qconf->tx_mask &= ~(1 << port);
316 qconf->tx_mbufs[port].len = len;
319 /* main processing loop */
320 static __attribute__((noreturn)) int
321 main_loop(__attribute__((unused)) void *dummy)
324 struct lcore_conf *qconf;
325 const uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;
327 lcoreid = rte_lcore_id();
328 qconf = &lcore_conf[lcoreid];
330 printf("Thread %u starting...\n", lcoreid);
333 struct rte_mbuf *pkt;
334 uint32_t pkt_from_nic_rx = 0;
337 /* Flush TX queues */
339 if (unlikely(qconf->tsc_count == TSC_COUNT_LIMIT)) {
340 uint64_t tsc, diff_tsc;
344 diff_tsc = tsc - qconf->tsc;
345 if (unlikely(diff_tsc > drain_tsc)) {
346 nic_tx_flush_queues(qconf);
347 crypto_flush_tx_queue(lcoreid);
351 qconf->tsc_count = 0;
355 * Check the Intel QuickAssist queues first
358 pkt = (struct rte_mbuf *) crypto_get_next_response();
360 pkt = nic_rx_get_packet(qconf);
365 /* Send packet to either QAT encrypt, QAT decrypt or NIC TX */
366 if (pkt_from_nic_rx) {
367 struct ipv4_hdr *ip = (struct ipv4_hdr *) (rte_pktmbuf_mtod(pkt, unsigned char *) +
368 sizeof(struct ether_hdr));
369 if (ip->src_addr & rte_cpu_to_be_32(ACTION_ENCRYPT)) {
370 if (CRYPTO_RESULT_FAIL == crypto_encrypt(pkt,
371 (enum cipher_alg)((ip->src_addr >> 16) & 0xFF),
372 (enum hash_alg)((ip->src_addr >> 8) & 0xFF)))
373 rte_pktmbuf_free(pkt);
377 if (ip->src_addr & rte_cpu_to_be_32(ACTION_DECRYPT)) {
378 if(CRYPTO_RESULT_FAIL == crypto_decrypt(pkt,
379 (enum cipher_alg)((ip->src_addr >> 16) & 0xFF),
380 (enum hash_alg)((ip->src_addr >> 8) & 0xFF)))
381 rte_pktmbuf_free(pkt);
386 port = dst_ports[pkt->pkt.in_port];
388 /* Transmit the packet */
389 nic_tx_send_packet(pkt, (uint8_t)port);
393 static inline unsigned
394 get_port_max_rx_queues(uint8_t port_id)
396 struct rte_eth_dev_info dev_info;
398 rte_eth_dev_info_get(port_id, &dev_info);
399 return dev_info.max_rx_queues;
402 static inline unsigned
403 get_port_max_tx_queues(uint8_t port_id)
405 struct rte_eth_dev_info dev_info;
407 rte_eth_dev_info_get(port_id, &dev_info);
408 return dev_info.max_tx_queues;
412 check_lcore_params(void)
416 for (i = 0; i < nb_lcore_params; ++i) {
417 if (lcore_params[i].queue_id >= get_port_max_rx_queues(lcore_params[i].port_id)) {
418 printf("invalid queue number: %hhu\n", lcore_params[i].queue_id);
421 if (!rte_lcore_is_enabled(lcore_params[i].lcore_id)) {
422 printf("error: lcore %hhu is not enabled in lcore mask\n",
423 lcore_params[i].lcore_id);
431 check_port_config(const unsigned nb_ports)
436 for (i = 0; i < nb_lcore_params; ++i) {
437 portid = lcore_params[i].port_id;
438 if ((enabled_port_mask & (1 << portid)) == 0) {
439 printf("port %u is not enabled in port mask\n", portid);
442 if (portid >= nb_ports) {
443 printf("port %u is not present on the board\n", portid);
451 get_port_n_rx_queues(const uint8_t port)
456 for (i = 0; i < nb_lcore_params; ++i) {
457 if (lcore_params[i].port_id == port && lcore_params[i].queue_id > queue)
458 queue = lcore_params[i].queue_id;
460 return (uint8_t)(++queue);
464 init_lcore_rx_queues(void)
466 uint16_t i, nb_rx_queue;
469 for (i = 0; i < nb_lcore_params; ++i) {
470 lcore = lcore_params[i].lcore_id;
471 nb_rx_queue = lcore_conf[lcore].n_rx_queue;
472 if (nb_rx_queue >= MAX_RX_QUEUE_PER_LCORE) {
473 printf("error: too many queues (%u) for lcore: %u\n",
474 (unsigned)nb_rx_queue + 1, (unsigned)lcore);
477 lcore_conf[lcore].rx_queue_list[nb_rx_queue].port_id =
478 lcore_params[i].port_id;
479 lcore_conf[lcore].rx_queue_list[nb_rx_queue].queue_id =
480 lcore_params[i].queue_id;
481 lcore_conf[lcore].n_rx_queue++;
488 print_usage(const char *prgname)
490 printf ("%s [EAL options] -- -p PORTMASK [--no-promisc]"
491 " [--config '(port,queue,lcore)[,(port,queue,lcore)]'\n"
492 " -p PORTMASK: hexadecimal bitmask of ports to configure\n"
493 " --no-promisc: disable promiscuous mode (default is ON)\n"
494 " --config '(port,queue,lcore)': rx queues configuration\n",
499 parse_portmask(const char *portmask)
504 /* parse hexadecimal string */
505 pm = strtoul(portmask, &end, 16);
506 if ((portmask[0] == '\0') || (end == NULL) || (*end != '\0'))
513 parse_config(const char *q_arg)
516 const char *p, *p_end = q_arg;
524 unsigned long int_fld[_NUM_FLD];
525 char *str_fld[_NUM_FLD];
531 while ((p = strchr(p_end,'(')) != NULL) {
532 if (nb_lcore_params >= MAX_LCORE_PARAMS) {
533 printf("exceeded max number of lcore params: %hu\n",
538 if((p_end = strchr(p,')')) == NULL)
542 if(size >= sizeof(s))
545 rte_snprintf(s, sizeof(s), "%.*s", size, p);
546 if (rte_strsplit(s, sizeof(s), str_fld, _NUM_FLD, ',') != _NUM_FLD)
548 for (i = 0; i < _NUM_FLD; i++) {
550 int_fld[i] = strtoul(str_fld[i], &end, 0);
551 if (errno != 0 || end == str_fld[i] || int_fld[i] > 255)
554 lcore_params_array[nb_lcore_params].port_id = (uint8_t)int_fld[FLD_PORT];
555 lcore_params_array[nb_lcore_params].queue_id = (uint8_t)int_fld[FLD_QUEUE];
556 lcore_params_array[nb_lcore_params].lcore_id = (uint8_t)int_fld[FLD_LCORE];
559 lcore_params = lcore_params_array;
563 /* Parse the argument given in the command line of the application */
565 parse_args(int argc, char **argv)
570 char *prgname = argv[0];
571 static struct option lgopts[] = {
573 {"no-promisc", 0, 0, 0},
579 while ((opt = getopt_long(argc, argvopt, "p:",
580 lgopts, &option_index)) != EOF) {
585 enabled_port_mask = parse_portmask(optarg);
586 if (enabled_port_mask == 0) {
587 printf("invalid portmask\n");
588 print_usage(prgname);
595 if (strcmp(lgopts[option_index].name, "config") == 0) {
596 ret = parse_config(optarg);
598 printf("invalid config\n");
599 print_usage(prgname);
603 if (strcmp(lgopts[option_index].name, "no-promisc") == 0) {
604 printf("Promiscuous mode disabled\n");
609 print_usage(prgname);
614 if (enabled_port_mask == 0) {
615 printf("portmask not specified\n");
616 print_usage(prgname);
621 argv[optind-1] = prgname;
624 optind = 0; /* reset getopt lib */
629 print_ethaddr(const char *name, const struct ether_addr *eth_addr)
631 printf ("%s%02X:%02X:%02X:%02X:%02X:%02X", name,
632 eth_addr->addr_bytes[0],
633 eth_addr->addr_bytes[1],
634 eth_addr->addr_bytes[2],
635 eth_addr->addr_bytes[3],
636 eth_addr->addr_bytes[4],
637 eth_addr->addr_bytes[5]);
643 const unsigned flags = 0;
648 RTE_LCORE_FOREACH(lcoreid) {
649 socketid = rte_lcore_to_socket_id(lcoreid);
650 if (socketid >= RTE_MAX_NUMA_NODES) {
651 printf("Socket %d of lcore %u is out of range %d\n",
652 socketid, lcoreid, RTE_MAX_NUMA_NODES);
655 if (pktmbuf_pool[socketid] == NULL) {
656 rte_snprintf(s, sizeof(s), "mbuf_pool_%d", socketid);
657 pktmbuf_pool[socketid] =
658 rte_mempool_create(s, NB_MBUF, MBUF_SIZE, 32,
659 sizeof(struct rte_pktmbuf_pool_private),
660 rte_pktmbuf_pool_init, NULL,
661 rte_pktmbuf_init, NULL,
663 if (pktmbuf_pool[socketid] == NULL) {
664 printf("Cannot init mbuf pool on socket %d\n", socketid);
667 printf("Allocated mbuf pool on socket %d\n", socketid);
674 MAIN(int argc, char **argv)
676 struct lcore_conf *qconf;
677 struct rte_eth_link link;
682 uint32_t nb_tx_queue;
683 uint8_t portid, nb_rx_queue, queue, socketid, last_port;
684 unsigned nb_ports_in_mask = 0;
687 ret = rte_eal_init(argc, argv);
693 /* parse application arguments (after the EAL ones) */
694 ret = parse_args(argc, argv);
699 #ifdef RTE_LIBRTE_IGB_PMD
700 if (rte_igb_pmd_init() < 0)
701 rte_panic("Cannot init igb pmd\n");
703 #ifdef RTE_LIBRTE_IXGBE_PMD
704 if (rte_ixgbe_pmd_init() < 0)
705 rte_panic("Cannot init ixgbe pmd\n");
708 if (rte_eal_pci_probe() < 0)
709 rte_panic("Cannot probe PCI\n");
711 if (check_lcore_params() < 0)
712 rte_panic("check_lcore_params failed\n");
714 ret = init_lcore_rx_queues();
722 nb_ports = rte_eth_dev_count();
723 if (nb_ports > RTE_MAX_ETHPORTS)
724 nb_ports = RTE_MAX_ETHPORTS;
726 if (check_port_config(nb_ports) < 0)
727 rte_panic("check_port_config failed\n");
729 /* reset dst_ports */
730 for (portid = 0; portid < RTE_MAX_ETHPORTS; portid++)
731 dst_ports[portid] = 0;
735 * Each logical core is assigned a dedicated TX queue on each port.
737 for (portid = 0; portid < nb_ports; portid++) {
738 /* skip ports that are not enabled */
739 if ((enabled_port_mask & (1 << portid)) == 0)
742 if (nb_ports_in_mask % 2) {
743 dst_ports[portid] = last_port;
744 dst_ports[last_port] = portid;
751 if (nb_ports_in_mask % 2) {
752 printf("Notice: odd number of ports in portmask.\n");
753 dst_ports[last_port] = last_port;
756 /* initialize all ports */
757 for (portid = 0; portid < nb_ports; portid++) {
758 /* skip ports that are not enabled */
759 if ((enabled_port_mask & (1 << portid)) == 0) {
760 printf("\nSkipping disabled port %d\n", portid);
765 printf("Initializing port %d ... ", portid );
768 nb_rx_queue = get_port_n_rx_queues(portid);
769 if (nb_rx_queue > get_port_max_rx_queues(portid))
770 rte_panic("Number of rx queues %d exceeds max number of rx queues %u"
771 " for port %d\n", nb_rx_queue, get_port_max_rx_queues(portid),
773 nb_tx_queue = rte_lcore_count();
774 if (nb_tx_queue > get_port_max_tx_queues(portid))
775 rte_panic("Number of lcores %u exceeds max number of tx queues %u"
776 " for port %d\n", nb_tx_queue, get_port_max_tx_queues(portid),
778 printf("Creating queues: nb_rxq=%d nb_txq=%u... ",
779 nb_rx_queue, (unsigned)nb_tx_queue );
780 ret = rte_eth_dev_configure(portid, nb_rx_queue,
781 (uint16_t)nb_tx_queue, &port_conf);
783 rte_panic("Cannot configure device: err=%d, port=%d\n",
786 rte_eth_macaddr_get(portid, &ports_eth_addr[portid]);
787 print_ethaddr(" Address:", &ports_eth_addr[portid]);
790 /* init one TX queue per couple (lcore,port) */
792 RTE_LCORE_FOREACH(lcoreid) {
793 socketid = (uint8_t)rte_lcore_to_socket_id(lcoreid);
794 printf("txq=%u,%d,%d ", lcoreid, queueid, socketid);
796 ret = rte_eth_tx_queue_setup(portid, queueid, nb_txd,
799 rte_panic("rte_eth_tx_queue_setup: err=%d, "
800 "port=%d\n", ret, portid);
802 qconf = &lcore_conf[lcoreid];
803 qconf->tx_queue_id[portid] = queueid;
809 RTE_LCORE_FOREACH(lcoreid) {
810 qconf = &lcore_conf[lcoreid];
811 printf("\nInitializing rx queues on lcore %u ... ", lcoreid );
814 for(queue = 0; queue < qconf->n_rx_queue; ++queue) {
815 portid = qconf->rx_queue_list[queue].port_id;
816 queueid = qconf->rx_queue_list[queue].queue_id;
817 socketid = (uint8_t)rte_lcore_to_socket_id(lcoreid);
818 printf("rxq=%d,%d,%d ", portid, queueid, socketid);
821 ret = rte_eth_rx_queue_setup(portid, queueid, nb_rxd,
822 socketid, &rx_conf, pktmbuf_pool[socketid]);
824 rte_panic("rte_eth_rx_queue_setup: err=%d,"
825 "port=%d\n", ret, portid);
832 for (portid = 0; portid < nb_ports; portid++) {
833 if ((enabled_port_mask & (1 << portid)) == 0)
836 ret = rte_eth_dev_start(portid);
838 rte_panic("rte_eth_dev_start: err=%d, port=%d\n",
841 printf("done: Port %d ", portid);
843 /* get link status */
844 rte_eth_link_get(portid, &link);
845 if (link.link_status)
846 printf(" Link Up - speed %u Mbps - %s\n",
847 (unsigned) link.link_speed,
848 (link.link_duplex == ETH_LINK_FULL_DUPLEX) ?
849 ("full-duplex") : ("half-duplex\n"));
851 printf(" Link Down\n");
853 * If enabled, put device in promiscuous mode.
854 * This allows IO forwarding mode to forward packets
855 * to itself through 2 cross-connected ports of the
859 rte_eth_promiscuous_enable(portid);
861 printf("Crypto: Initializing Crypto...\n");
862 if (crypto_init() != 0)
865 RTE_LCORE_FOREACH(lcoreid) {
866 if (per_core_crypto_init(lcoreid) != 0) {
867 printf("Crypto: Cannot init lcore crypto on lcore %u\n", (unsigned)lcoreid);
871 printf("Crypto: Initialization complete\n");
872 /* launch per-lcore init on every lcore */
873 rte_eal_mp_remote_launch(main_loop, NULL, CALL_MASTER);
874 RTE_LCORE_FOREACH_SLAVE(lcoreid) {
875 if (rte_eal_wait_lcore(lcoreid) < 0)