4 * Copyright(c) 2010-2012 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer in
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <sys/types.h>
41 #include <sys/queue.h>
46 #include <rte_common.h>
47 #include <rte_byteorder.h>
49 #include <rte_memory.h>
50 #include <rte_memzone.h>
51 #include <rte_tailq.h>
53 #include <rte_per_lcore.h>
54 #include <rte_launch.h>
55 #include <rte_atomic.h>
56 #include <rte_cycles.h>
57 #include <rte_prefetch.h>
58 #include <rte_lcore.h>
59 #include <rte_per_lcore.h>
60 #include <rte_branch_prediction.h>
61 #include <rte_interrupts.h>
63 #include <rte_random.h>
64 #include <rte_debug.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
68 #include <rte_mempool.h>
71 #include <rte_string_fns.h>
76 #define MBUF_SIZE (2048 + sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM)
77 #define NB_MBUF (32 * 1024)
80 * RX and TX Prefetch, Host, and Write-back threshold values should be
81 * carefully set for optimal performance. Consult the network
82 * controller's datasheet and supporting DPDK documentation for guidance
83 * on how these parameters should be set.
85 #define RX_PTHRESH 8 /**< Default values of RX prefetch threshold reg. */
86 #define RX_HTHRESH 8 /**< Default values of RX host threshold reg. */
87 #define RX_WTHRESH 4 /**< Default values of RX write-back threshold reg. */
90 * These default values are optimized for use with the Intel(R) 82599 10 GbE
91 * Controller and the DPDK ixgbe PMD. Consider using other values for other
92 * network controllers and/or network drivers.
94 #define TX_PTHRESH 36 /**< Default values of TX prefetch threshold reg. */
95 #define TX_HTHRESH 0 /**< Default values of TX host threshold reg. */
96 #define TX_WTHRESH 0 /**< Default values of TX write-back threshold reg. */
98 #define MAX_PKT_BURST 32
99 #define BURST_TX_DRAIN 200000ULL /* around 100us at 2 Ghz */
103 #define TX_QUEUE_FLUSH_MASK 0xFFFFFFFF
104 #define TSC_COUNT_LIMIT 1000
106 #define ACTION_ENCRYPT 1
107 #define ACTION_DECRYPT 2
110 * Configurable number of RX/TX ring descriptors
112 #define RTE_TEST_RX_DESC_DEFAULT 128
113 #define RTE_TEST_TX_DESC_DEFAULT 512
114 static uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT;
115 static uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;
117 /* ethernet addresses of ports */
118 static struct ether_addr ports_eth_addr[RTE_MAX_ETHPORTS];
120 /* mask of enabled ports */
121 static unsigned enabled_port_mask = 0;
122 static int promiscuous_on = 1; /**< Ports set in promiscuous mode on by default. */
126 struct rte_mbuf *m_table[MAX_PKT_BURST];
129 struct lcore_rx_queue {
134 #define MAX_RX_QUEUE_PER_LCORE 16
136 #define MAX_LCORE_PARAMS 1024
137 struct lcore_params {
143 static struct lcore_params lcore_params_array[MAX_LCORE_PARAMS];
144 static struct lcore_params lcore_params_array_default[] = {
156 static struct lcore_params * lcore_params = lcore_params_array_default;
157 static uint16_t nb_lcore_params = sizeof(lcore_params_array_default) /
158 sizeof(lcore_params_array_default[0]);
160 static struct rte_eth_conf port_conf = {
163 .header_split = 0, /**< Header Split disabled */
164 .hw_ip_checksum = 1, /**< IP checksum offload enabled */
165 .hw_vlan_filter = 0, /**< VLAN filtering disabled */
166 .jumbo_frame = 0, /**< Jumbo Frame Support disabled */
167 .hw_strip_crc = 0, /**< CRC stripped by hardware */
172 .rss_hf = ETH_RSS_IPV4,
179 static const struct rte_eth_rxconf rx_conf = {
181 .pthresh = RX_PTHRESH,
182 .hthresh = RX_HTHRESH,
183 .wthresh = RX_WTHRESH,
187 static const struct rte_eth_txconf tx_conf = {
189 .pthresh = TX_PTHRESH,
190 .hthresh = TX_HTHRESH,
191 .wthresh = TX_WTHRESH,
193 .tx_free_thresh = 0, /* Use PMD default values */
194 .tx_rs_thresh = 0, /* Use PMD default values */
197 static struct rte_mempool * pktmbuf_pool[RTE_MAX_NUMA_NODES];
204 uint16_t rx_queue_list_pos;
205 struct lcore_rx_queue rx_queue_list[MAX_RX_QUEUE_PER_LCORE];
206 uint16_t tx_queue_id[RTE_MAX_ETHPORTS];
207 struct mbuf_table rx_mbuf;
208 uint32_t rx_mbuf_pos;
209 uint32_t rx_curr_queue;
210 struct mbuf_table tx_mbufs[RTE_MAX_ETHPORTS];
211 } __rte_cache_aligned;
213 static struct lcore_conf lcore_conf[RTE_MAX_LCORE];
215 static inline struct rte_mbuf *
216 nic_rx_get_packet(struct lcore_conf *qconf)
218 struct rte_mbuf *pkt;
220 if (unlikely(qconf->n_rx_queue == 0))
223 /* Look for the next queue with packets; return if none */
224 if (unlikely(qconf->rx_mbuf_pos == qconf->rx_mbuf.len)) {
227 qconf->rx_mbuf_pos = 0;
228 for (i = 0; i < qconf->n_rx_queue; i++) {
229 qconf->rx_mbuf.len = rte_eth_rx_burst(
230 qconf->rx_queue_list[qconf->rx_curr_queue].port_id,
231 qconf->rx_queue_list[qconf->rx_curr_queue].queue_id,
232 qconf->rx_mbuf.m_table, MAX_PKT_BURST);
234 qconf->rx_curr_queue++;
235 if (unlikely(qconf->rx_curr_queue == qconf->n_rx_queue))
236 qconf->rx_curr_queue = 0;
237 if (likely(qconf->rx_mbuf.len > 0))
240 if (unlikely(i == qconf->n_rx_queue))
244 /* Get the next packet from the current queue; if last packet, go to next queue */
245 pkt = qconf->rx_mbuf.m_table[qconf->rx_mbuf_pos];
246 qconf->rx_mbuf_pos++;
252 nic_tx_flush_queues(struct lcore_conf *qconf)
256 for (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {
257 struct rte_mbuf **m_table = NULL;
258 uint16_t queueid, len;
261 if (likely((qconf->tx_mask & (1 << portid)) == 0))
264 len = qconf->tx_mbufs[portid].len;
265 if (likely(len == 0))
268 queueid = qconf->tx_queue_id[portid];
269 m_table = qconf->tx_mbufs[portid].m_table;
271 n = rte_eth_tx_burst(portid, queueid, m_table, len);
272 for (i = n; i < len; i++){
273 rte_pktmbuf_free(m_table[i]);
276 qconf->tx_mbufs[portid].len = 0;
279 qconf->tx_mask = TX_QUEUE_FLUSH_MASK;
283 nic_tx_send_packet(struct rte_mbuf *pkt, uint8_t port)
285 struct lcore_conf *qconf;
289 if (unlikely(pkt == NULL)) {
293 lcoreid = rte_lcore_id();
294 qconf = &lcore_conf[lcoreid];
296 len = qconf->tx_mbufs[port].len;
297 qconf->tx_mbufs[port].m_table[len] = pkt;
300 /* enough pkts to be sent */
301 if (unlikely(len == MAX_PKT_BURST)) {
305 queueid = qconf->tx_queue_id[port];
306 n = rte_eth_tx_burst(port, queueid, qconf->tx_mbufs[port].m_table, MAX_PKT_BURST);
307 for (i = n; i < MAX_PKT_BURST; i++){
308 rte_pktmbuf_free(qconf->tx_mbufs[port].m_table[i]);
311 qconf->tx_mask &= ~(1 << port);
315 qconf->tx_mbufs[port].len = len;
318 static inline uint8_t
319 get_output_port(uint8_t input_port)
321 return (uint8_t)(input_port ^ 1);
324 /* main processing loop */
325 static __attribute__((noreturn)) int
326 main_loop(__attribute__((unused)) void *dummy)
329 struct lcore_conf *qconf;
331 lcoreid = rte_lcore_id();
332 qconf = &lcore_conf[lcoreid];
334 printf("Thread %u starting...\n", lcoreid);
337 struct rte_mbuf *pkt;
338 uint32_t pkt_from_nic_rx = 0;
341 /* Flush TX queues */
343 if (unlikely(qconf->tsc_count == TSC_COUNT_LIMIT)) {
344 uint64_t tsc, diff_tsc;
348 diff_tsc = tsc - qconf->tsc;
349 if (unlikely(diff_tsc > BURST_TX_DRAIN)) {
350 nic_tx_flush_queues(qconf);
351 crypto_flush_tx_queue(lcoreid);
355 qconf->tsc_count = 0;
359 * Check the Intel QuickAssist queues first
362 pkt = (struct rte_mbuf *) crypto_get_next_response();
364 pkt = nic_rx_get_packet(qconf);
369 /* Send packet to either QAT encrypt, QAT decrypt or NIC TX */
370 if (pkt_from_nic_rx) {
371 struct ipv4_hdr *ip = (struct ipv4_hdr *) (rte_pktmbuf_mtod(pkt, unsigned char *) +
372 sizeof(struct ether_hdr));
373 if (ip->src_addr & rte_cpu_to_be_32(ACTION_ENCRYPT)) {
374 if (CRYPTO_RESULT_FAIL == crypto_encrypt(pkt,
375 (enum cipher_alg)((ip->src_addr >> 16) & 0xFF),
376 (enum hash_alg)((ip->src_addr >> 8) & 0xFF)))
377 rte_pktmbuf_free(pkt);
381 if (ip->src_addr & rte_cpu_to_be_32(ACTION_DECRYPT)) {
382 if(CRYPTO_RESULT_FAIL == crypto_decrypt(pkt,
383 (enum cipher_alg)((ip->src_addr >> 16) & 0xFF),
384 (enum hash_alg)((ip->src_addr >> 8) & 0xFF)))
385 rte_pktmbuf_free(pkt);
390 port = get_output_port(pkt->pkt.in_port);
392 /* Transmit the packet */
393 nic_tx_send_packet(pkt, port);
397 static inline unsigned
398 get_port_max_rx_queues(uint8_t port_id)
400 struct rte_eth_dev_info dev_info;
402 rte_eth_dev_info_get(port_id, &dev_info);
403 return dev_info.max_rx_queues;
406 static inline unsigned
407 get_port_max_tx_queues(uint8_t port_id)
409 struct rte_eth_dev_info dev_info;
411 rte_eth_dev_info_get(port_id, &dev_info);
412 return dev_info.max_tx_queues;
416 check_lcore_params(void)
420 for (i = 0; i < nb_lcore_params; ++i) {
421 if (lcore_params[i].queue_id >= get_port_max_rx_queues(lcore_params[i].port_id)) {
422 printf("invalid queue number: %hhu\n", lcore_params[i].queue_id);
425 if (!rte_lcore_is_enabled(lcore_params[i].lcore_id)) {
426 printf("error: lcore %hhu is not enabled in lcore mask\n",
427 lcore_params[i].lcore_id);
435 check_port_config(const unsigned nb_ports)
440 for (i = 0; i < nb_lcore_params; ++i) {
441 portid = lcore_params[i].port_id;
442 if ((enabled_port_mask & (1 << portid)) == 0) {
443 printf("port %u is not enabled in port mask\n", portid);
446 if (portid >= nb_ports) {
447 printf("port %u is not present on the board\n", portid);
455 get_port_n_rx_queues(const uint8_t port)
460 for (i = 0; i < nb_lcore_params; ++i) {
461 if (lcore_params[i].port_id == port && lcore_params[i].queue_id > queue)
462 queue = lcore_params[i].queue_id;
464 return (uint8_t)(++queue);
468 init_lcore_rx_queues(void)
470 uint16_t i, nb_rx_queue;
473 for (i = 0; i < nb_lcore_params; ++i) {
474 lcore = lcore_params[i].lcore_id;
475 nb_rx_queue = lcore_conf[lcore].n_rx_queue;
476 if (nb_rx_queue >= MAX_RX_QUEUE_PER_LCORE) {
477 printf("error: too many queues (%u) for lcore: %u\n",
478 (unsigned)nb_rx_queue + 1, (unsigned)lcore);
481 lcore_conf[lcore].rx_queue_list[nb_rx_queue].port_id =
482 lcore_params[i].port_id;
483 lcore_conf[lcore].rx_queue_list[nb_rx_queue].queue_id =
484 lcore_params[i].queue_id;
485 lcore_conf[lcore].n_rx_queue++;
492 print_usage(const char *prgname)
494 printf ("%s [EAL options] -- -p PORTMASK [--no-promisc]"
495 " [--config (port,queue,lcore)[,(port,queue,lcore]]\n"
496 " -p PORTMASK: hexadecimal bitmask of ports to configure\n"
497 " --no-promisc: disable promiscuous mode (default is ON)\n"
498 " --config (port,queue,lcore): rx queues configuration\n",
503 parse_portmask(const char *portmask)
508 /* parse hexadecimal string */
509 pm = strtoul(portmask, &end, 16);
510 if ((portmask[0] == '\0') || (end == NULL) || (*end != '\0'))
517 parse_config(const char *q_arg)
520 const char *p, *p_end = q_arg;
528 unsigned long int_fld[_NUM_FLD];
529 char *str_fld[_NUM_FLD];
535 while ((p = strchr(p_end,'(')) != NULL) {
536 if (nb_lcore_params >= MAX_LCORE_PARAMS) {
537 printf("exceeded max number of lcore params: %hu\n",
542 if((p_end = strchr(p,')')) == NULL)
546 if(size >= sizeof(s))
549 rte_snprintf(s, sizeof(s), "%.*s", size, p);
550 if (rte_strsplit(s, sizeof(s), str_fld, _NUM_FLD, ',') != _NUM_FLD)
552 for (i = 0; i < _NUM_FLD; i++) {
554 int_fld[i] = strtoul(str_fld[i], &end, 0);
555 if (errno != 0 || end == str_fld[i] || int_fld[i] > 255)
558 lcore_params_array[nb_lcore_params].port_id = (uint8_t)int_fld[FLD_PORT];
559 lcore_params_array[nb_lcore_params].queue_id = (uint8_t)int_fld[FLD_QUEUE];
560 lcore_params_array[nb_lcore_params].lcore_id = (uint8_t)int_fld[FLD_LCORE];
563 lcore_params = lcore_params_array;
567 /* Parse the argument given in the command line of the application */
569 parse_args(int argc, char **argv)
574 char *prgname = argv[0];
575 static struct option lgopts[] = {
577 {"no-promisc", 0, 0, 0},
583 while ((opt = getopt_long(argc, argvopt, "p:",
584 lgopts, &option_index)) != EOF) {
589 enabled_port_mask = parse_portmask(optarg);
590 if (enabled_port_mask == 0) {
591 printf("invalid portmask\n");
592 print_usage(prgname);
599 if (strcmp(lgopts[option_index].name, "config") == 0) {
600 ret = parse_config(optarg);
602 printf("invalid config\n");
603 print_usage(prgname);
607 if (strcmp(lgopts[option_index].name, "no-promisc") == 0) {
608 printf("Promiscuous mode disabled\n");
613 print_usage(prgname);
618 if (enabled_port_mask == 0) {
619 printf("portmask not specified\n");
620 print_usage(prgname);
625 argv[optind-1] = prgname;
628 optind = 0; /* reset getopt lib */
633 print_ethaddr(const char *name, const struct ether_addr *eth_addr)
635 printf ("%s%02X:%02X:%02X:%02X:%02X:%02X", name,
636 eth_addr->addr_bytes[0],
637 eth_addr->addr_bytes[1],
638 eth_addr->addr_bytes[2],
639 eth_addr->addr_bytes[3],
640 eth_addr->addr_bytes[4],
641 eth_addr->addr_bytes[5]);
647 const unsigned flags = 0;
652 RTE_LCORE_FOREACH(lcoreid) {
653 socketid = rte_lcore_to_socket_id(lcoreid);
654 if (socketid >= RTE_MAX_NUMA_NODES) {
655 printf("Socket %d of lcore %u is out of range %d\n",
656 socketid, lcoreid, RTE_MAX_NUMA_NODES);
659 if (pktmbuf_pool[socketid] == NULL) {
660 rte_snprintf(s, sizeof(s), "mbuf_pool_%d", socketid);
661 pktmbuf_pool[socketid] =
662 rte_mempool_create(s, NB_MBUF, MBUF_SIZE, 32,
663 sizeof(struct rte_pktmbuf_pool_private),
664 rte_pktmbuf_pool_init, NULL,
665 rte_pktmbuf_init, NULL,
667 if (pktmbuf_pool[socketid] == NULL) {
668 printf("Cannot init mbuf pool on socket %d\n", socketid);
671 printf("Allocated mbuf pool on socket %d\n", socketid);
678 MAIN(int argc, char **argv)
680 struct lcore_conf *qconf;
681 struct rte_eth_link link;
686 uint32_t nb_tx_queue;
687 uint8_t portid, nb_rx_queue, queue, socketid;
690 ret = rte_eal_init(argc, argv);
696 /* parse application arguments (after the EAL ones) */
697 ret = parse_args(argc, argv);
702 #ifdef RTE_LIBRTE_IGB_PMD
703 if (rte_igb_pmd_init() < 0)
704 rte_panic("Cannot init igb pmd\n");
706 #ifdef RTE_LIBRTE_IXGBE_PMD
707 if (rte_ixgbe_pmd_init() < 0)
708 rte_panic("Cannot init ixgbe pmd\n");
711 if (rte_eal_pci_probe() < 0)
712 rte_panic("Cannot probe PCI\n");
714 if (check_lcore_params() < 0)
715 rte_panic("check_lcore_params failed\n");
717 ret = init_lcore_rx_queues();
725 nb_ports = rte_eth_dev_count();
726 if (nb_ports > RTE_MAX_ETHPORTS)
727 nb_ports = RTE_MAX_ETHPORTS;
729 if (check_port_config(nb_ports) < 0)
730 rte_panic("check_port_config failed\n");
732 /* initialize all ports */
733 for (portid = 0; portid < nb_ports; portid++) {
734 /* skip ports that are not enabled */
735 if ((enabled_port_mask & (1 << portid)) == 0) {
736 printf("\nSkipping disabled port %d\n", portid);
741 printf("Initializing port %d ... ", portid );
744 nb_rx_queue = get_port_n_rx_queues(portid);
745 if (nb_rx_queue > get_port_max_rx_queues(portid))
746 rte_panic("Number of rx queues %d exceeds max number of rx queues %u"
747 " for port %d\n", nb_rx_queue, get_port_max_rx_queues(portid),
749 nb_tx_queue = rte_lcore_count();
750 if (nb_tx_queue > get_port_max_tx_queues(portid))
751 rte_panic("Number of lcores %u exceeds max number of tx queues %u"
752 " for port %d\n", nb_tx_queue, get_port_max_tx_queues(portid),
754 printf("Creating queues: nb_rxq=%d nb_txq=%u... ",
755 nb_rx_queue, (unsigned)nb_tx_queue );
756 ret = rte_eth_dev_configure(portid, nb_rx_queue,
757 (uint16_t)nb_tx_queue, &port_conf);
759 rte_panic("Cannot configure device: err=%d, port=%d\n",
762 rte_eth_macaddr_get(portid, &ports_eth_addr[portid]);
763 print_ethaddr(" Address:", &ports_eth_addr[portid]);
766 /* init one TX queue per couple (lcore,port) */
768 RTE_LCORE_FOREACH(lcoreid) {
769 socketid = (uint8_t)rte_lcore_to_socket_id(lcoreid);
770 printf("txq=%u,%d,%d ", lcoreid, queueid, socketid);
772 ret = rte_eth_tx_queue_setup(portid, queueid, nb_txd,
775 rte_panic("rte_eth_tx_queue_setup: err=%d, "
776 "port=%d\n", ret, portid);
778 qconf = &lcore_conf[lcoreid];
779 qconf->tx_queue_id[portid] = queueid;
785 RTE_LCORE_FOREACH(lcoreid) {
786 qconf = &lcore_conf[lcoreid];
787 printf("\nInitializing rx queues on lcore %u ... ", lcoreid );
790 for(queue = 0; queue < qconf->n_rx_queue; ++queue) {
791 portid = qconf->rx_queue_list[queue].port_id;
792 queueid = qconf->rx_queue_list[queue].queue_id;
793 socketid = (uint8_t)rte_lcore_to_socket_id(lcoreid);
794 printf("rxq=%d,%d,%d ", portid, queueid, socketid);
797 ret = rte_eth_rx_queue_setup(portid, queueid, nb_rxd,
798 socketid, &rx_conf, pktmbuf_pool[socketid]);
800 rte_panic("rte_eth_rx_queue_setup: err=%d,"
801 "port=%d\n", ret, portid);
808 for (portid = 0; portid < nb_ports; portid++) {
809 if ((enabled_port_mask & (1 << portid)) == 0)
812 ret = rte_eth_dev_start(portid);
814 rte_panic("rte_eth_dev_start: err=%d, port=%d\n",
817 printf("done: Port %d ", portid);
819 /* get link status */
820 rte_eth_link_get(portid, &link);
821 if (link.link_status)
822 printf(" Link Up - speed %u Mbps - %s\n",
823 (unsigned) link.link_speed,
824 (link.link_duplex == ETH_LINK_FULL_DUPLEX) ?
825 ("full-duplex") : ("half-duplex\n"));
827 printf(" Link Down\n");
829 * If enabled, put device in promiscuous mode.
830 * This allows IO forwarding mode to forward packets
831 * to itself through 2 cross-connected ports of the
835 rte_eth_promiscuous_enable(portid);
837 printf("Crypto: Initializing Crypto...\n");
838 if (crypto_init() != 0)
841 RTE_LCORE_FOREACH(lcoreid) {
842 if (per_core_crypto_init(lcoreid) != 0) {
843 printf("Crypto: Cannot init lcore crypto on lcore %u\n", (unsigned)lcoreid);
847 printf("Crypto: Initialization complete\n");
848 /* launch per-lcore init on every lcore */
849 rte_eal_mp_remote_launch(main_loop, NULL, CALL_MASTER);
850 RTE_LCORE_FOREACH_SLAVE(lcoreid) {
851 if (rte_eal_wait_lcore(lcoreid) < 0)