1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2016-2017 Intel Corporation
11 #include "pipeline_common.h"
13 struct fastpath_data *fdata;
15 struct config_data cdata = {
16 .num_packets = (1L << 25), /* do ~32M packets */
18 .queue_type = RTE_SCHED_TYPE_ATOMIC,
26 dump_core_info(unsigned int lcore_id, struct worker_data *data,
27 unsigned int worker_idx)
29 if (fdata->rx_core[lcore_id])
31 "[%s()] lcore %d executing NIC Rx\n",
34 if (fdata->tx_core[lcore_id])
36 "[%s()] lcore %d executing NIC Tx\n",
39 if (fdata->sched_core[lcore_id])
41 "[%s()] lcore %d executing scheduler\n",
44 if (fdata->worker_core[lcore_id])
46 "[%s()] lcore %d executing worker, using eventdev port %u\n",
48 data[worker_idx].port_id);
52 core_in_use(unsigned int lcore_id) {
53 return (fdata->rx_core[lcore_id] || fdata->sched_core[lcore_id] ||
54 fdata->tx_core[lcore_id] || fdata->worker_core[lcore_id]);
58 * Parse the coremask given as argument (hexadecimal string) and fill
59 * the global configuration (core role and core count) with the parsed
62 static int xdigit2val(unsigned char c)
76 parse_coremask(const char *coremask)
79 unsigned int count = 0;
83 const int32_t BITS_HEX = 4;
87 /* Remove all blank characters ahead and after .
88 * Remove 0x/0X if exists.
90 while (isblank(*coremask))
92 if (coremask[0] == '0' && ((coremask[1] == 'x')
93 || (coremask[1] == 'X')))
96 while ((i > 0) && isblank(coremask[i - 1]))
101 for (i = i - 1; i >= 0 && idx < MAX_NUM_CORE; i--) {
103 if (isxdigit(c) == 0) {
104 /* invalid characters */
108 for (j = 0; j < BITS_HEX && idx < MAX_NUM_CORE; j++, idx++) {
109 if ((1 << j) & val) {
110 mask |= (1ULL << idx);
116 if (coremask[i] != '0')
123 static struct option long_options[] = {
124 {"workers", required_argument, 0, 'w'},
125 {"packets", required_argument, 0, 'n'},
126 {"atomic-flows", required_argument, 0, 'f'},
127 {"num_stages", required_argument, 0, 's'},
128 {"rx-mask", required_argument, 0, 'r'},
129 {"tx-mask", required_argument, 0, 't'},
130 {"sched-mask", required_argument, 0, 'e'},
131 {"cq-depth", required_argument, 0, 'c'},
132 {"work-cycles", required_argument, 0, 'W'},
133 {"mempool-size", required_argument, 0, 'm'},
134 {"queue-priority", no_argument, 0, 'P'},
135 {"parallel", no_argument, 0, 'p'},
136 {"ordered", no_argument, 0, 'o'},
137 {"quiet", no_argument, 0, 'q'},
138 {"use-atq", no_argument, 0, 'a'},
139 {"dump", no_argument, 0, 'D'},
146 const char *usage_str =
147 " Usage: eventdev_demo [options]\n"
149 " -n, --packets=N Send N packets (default ~32M), 0 implies no limit\n"
150 " -f, --atomic-flows=N Use N random flows from 1 to N (default 16)\n"
151 " -s, --num_stages=N Use N atomic stages (default 1)\n"
152 " -r, --rx-mask=core mask Run NIC rx on CPUs in core mask\n"
153 " -w, --worker-mask=core mask Run worker on CPUs in core mask\n"
154 " -t, --tx-mask=core mask Run NIC tx on CPUs in core mask\n"
155 " -e --sched-mask=core mask Run scheduler on CPUs in core mask\n"
156 " -c --cq-depth=N Worker CQ depth (default 16)\n"
157 " -W --work-cycles=N Worker cycles (default 0)\n"
158 " -P --queue-priority Enable scheduler queue prioritization\n"
159 " -o, --ordered Use ordered scheduling\n"
160 " -p, --parallel Use parallel scheduling\n"
161 " -q, --quiet Minimize printed output\n"
162 " -a, --use-atq Use all type queues\n"
163 " -m, --mempool-size=N Dictate the mempool size\n"
164 " -D, --dump Print detailed statistics before exit"
166 fprintf(stderr, "%s", usage_str);
171 parse_app_args(int argc, char **argv)
173 /* Parse cli options*/
177 uint64_t rx_lcore_mask = 0;
178 uint64_t tx_lcore_mask = 0;
179 uint64_t sched_lcore_mask = 0;
180 uint64_t worker_lcore_mask = 0;
184 c = getopt_long(argc, argv, "r:t:e:c:w:n:f:s:m:paoPqDW:",
185 long_options, &option_index);
192 cdata.num_packets = (int64_t)atol(optarg);
193 if (cdata.num_packets == 0)
194 cdata.num_packets = INT64_MAX;
197 cdata.num_fids = (unsigned int)atoi(optarg);
200 cdata.num_stages = (unsigned int)atoi(optarg);
203 cdata.worker_cq_depth = (unsigned int)atoi(optarg);
206 cdata.worker_cycles = (unsigned int)atoi(optarg);
209 cdata.enable_queue_priorities = 1;
212 cdata.queue_type = RTE_SCHED_TYPE_ORDERED;
215 cdata.queue_type = RTE_SCHED_TYPE_PARALLEL;
218 cdata.all_type_queues = 1;
227 worker_lcore_mask = parse_coremask(optarg);
230 rx_lcore_mask = parse_coremask(optarg);
231 popcnt = __builtin_popcountll(rx_lcore_mask);
232 fdata->rx_single = (popcnt == 1);
235 tx_lcore_mask = parse_coremask(optarg);
236 popcnt = __builtin_popcountll(tx_lcore_mask);
237 fdata->tx_single = (popcnt == 1);
240 sched_lcore_mask = parse_coremask(optarg);
241 popcnt = __builtin_popcountll(sched_lcore_mask);
242 fdata->sched_single = (popcnt == 1);
245 cdata.num_mbuf = (uint64_t)atol(optarg);
252 cdata.worker_lcore_mask = worker_lcore_mask;
253 cdata.sched_lcore_mask = sched_lcore_mask;
254 cdata.rx_lcore_mask = rx_lcore_mask;
255 cdata.tx_lcore_mask = tx_lcore_mask;
257 if (cdata.num_stages == 0 || cdata.num_stages > MAX_NUM_STAGES)
260 for (i = 0; i < MAX_NUM_CORE; i++) {
261 fdata->rx_core[i] = !!(rx_lcore_mask & (1ULL << i));
262 fdata->tx_core[i] = !!(tx_lcore_mask & (1ULL << i));
263 fdata->sched_core[i] = !!(sched_lcore_mask & (1ULL << i));
264 fdata->worker_core[i] = !!(worker_lcore_mask & (1ULL << i));
266 if (fdata->worker_core[i])
268 if (core_in_use(i)) {
269 if (!rte_lcore_is_enabled(i)) {
270 printf("lcore %d is not enabled in lcore list\n",
272 rte_exit(EXIT_FAILURE,
273 "check lcore params failed\n");
275 cdata.active_cores++;
281 do_capability_setup(uint8_t eventdev_id)
285 uint8_t generic_pipeline = 0;
288 RTE_ETH_FOREACH_DEV(i) {
291 ret = rte_event_eth_tx_adapter_caps_get(eventdev_id, i, &caps);
293 rte_exit(EXIT_FAILURE,
294 "Invalid capability for Tx adptr port %d\n", i);
295 generic_pipeline |= !(caps &
296 RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT);
299 struct rte_event_dev_info eventdev_info;
300 memset(&eventdev_info, 0, sizeof(struct rte_event_dev_info));
302 rte_event_dev_info_get(eventdev_id, &eventdev_info);
303 burst = eventdev_info.event_dev_cap & RTE_EVENT_DEV_CAP_BURST_MODE ? 1 :
306 if (generic_pipeline)
307 set_worker_generic_setup_data(&fdata->cap, burst);
309 set_worker_tx_enq_setup_data(&fdata->cap, burst);
313 signal_handler(int signum)
318 rte_exit(1, "Exiting on signal %d\n", signum);
319 if ((signum == SIGINT || signum == SIGTERM) && !once) {
320 printf("\n\nSignal %d received, preparing to exit...\n",
323 rte_event_dev_dump(0, stdout);
327 if (signum == SIGTSTP)
328 rte_event_dev_dump(0, stdout);
331 static inline uint64_t
332 port_stat(int dev_id, int32_t p)
335 snprintf(statname, sizeof(statname), "port_%u_rx", p);
336 return rte_event_dev_xstats_by_name_get(dev_id, statname, NULL);
340 main(int argc, char **argv)
342 struct worker_data *worker_data;
348 signal(SIGINT, signal_handler);
349 signal(SIGTERM, signal_handler);
350 signal(SIGTSTP, signal_handler);
352 err = rte_eal_init(argc, argv);
354 rte_panic("Invalid EAL arguments\n");
359 fdata = rte_malloc(NULL, sizeof(struct fastpath_data), 0);
361 rte_panic("Out of memory\n");
363 /* Parse cli options*/
364 parse_app_args(argc, argv);
366 num_ports = rte_eth_dev_count_avail();
368 rte_panic("No ethernet ports found\n");
370 const unsigned int cores_needed = cdata.active_cores;
373 printf(" Config:\n");
374 printf("\tports: %u\n", num_ports);
375 printf("\tworkers: %u\n", cdata.num_workers);
376 printf("\tpackets: %"PRIi64"\n", cdata.num_packets);
377 printf("\tQueue-prio: %u\n", cdata.enable_queue_priorities);
378 if (cdata.queue_type == RTE_SCHED_TYPE_ORDERED)
379 printf("\tqid0 type: ordered\n");
380 if (cdata.queue_type == RTE_SCHED_TYPE_ATOMIC)
381 printf("\tqid0 type: atomic\n");
382 printf("\tCores available: %u\n", rte_lcore_count());
383 printf("\tCores used: %u\n", cores_needed);
386 if (rte_lcore_count() < cores_needed)
387 rte_panic("Too few cores (%d < %d)\n", rte_lcore_count(),
390 const unsigned int ndevs = rte_event_dev_count();
392 rte_panic("No dev_id devs found. Pasl in a --vdev eventdev.\n");
394 fprintf(stderr, "Warning: More than one eventdev, using idx 0");
397 do_capability_setup(0);
398 fdata->cap.check_opt();
400 worker_data = rte_calloc(0, cdata.num_workers,
401 sizeof(worker_data[0]), 0);
402 if (worker_data == NULL)
403 rte_panic("rte_calloc failed\n");
405 int dev_id = fdata->cap.evdev_setup(worker_data);
407 rte_exit(EXIT_FAILURE, "Error setting up eventdev\n");
409 fdata->cap.adptr_setup(num_ports);
411 /* Start the Ethernet port. */
412 RTE_ETH_FOREACH_DEV(portid) {
413 err = rte_eth_dev_start(portid);
415 rte_exit(EXIT_FAILURE, "Error starting ethdev %d\n",
420 RTE_LCORE_FOREACH_WORKER(lcore_id) {
421 if (lcore_id >= MAX_NUM_CORE)
424 if (!fdata->rx_core[lcore_id] &&
425 !fdata->worker_core[lcore_id] &&
426 !fdata->tx_core[lcore_id] &&
427 !fdata->sched_core[lcore_id])
430 dump_core_info(lcore_id, worker_data, worker_idx);
432 err = rte_eal_remote_launch(fdata->cap.worker,
433 &worker_data[worker_idx], lcore_id);
435 rte_panic("Failed to launch worker on core %d\n",
439 if (fdata->worker_core[lcore_id])
443 lcore_id = rte_lcore_id();
445 if (core_in_use(lcore_id)) {
446 dump_core_info(lcore_id, worker_data, worker_idx);
447 fdata->cap.worker(&worker_data[worker_idx]);
449 if (fdata->worker_core[lcore_id])
453 rte_eal_mp_wait_lcore();
455 if (!cdata.quiet && (port_stat(dev_id, worker_data[0].port_id) !=
456 (uint64_t)-ENOTSUP)) {
457 printf("\nPort Workload distribution:\n");
459 uint64_t tot_pkts = 0;
460 uint64_t pkts_per_wkr[RTE_MAX_LCORE] = {0};
461 for (i = 0; i < cdata.num_workers; i++) {
463 port_stat(dev_id, worker_data[i].port_id);
464 tot_pkts += pkts_per_wkr[i];
466 for (i = 0; i < cdata.num_workers; i++) {
467 float pc = pkts_per_wkr[i] * 100 /
469 printf("worker %i :\t%.1f %% (%"PRIu64" pkts)\n",
470 i, pc, pkts_per_wkr[i]);
475 RTE_ETH_FOREACH_DEV(portid) {
476 rte_event_eth_rx_adapter_stop(portid);
477 rte_event_eth_tx_adapter_stop(portid);
478 if (rte_eth_dev_stop(portid) < 0)
479 printf("Failed to stop port %u", portid);
480 rte_eth_dev_close(portid);
483 rte_event_dev_stop(0);
484 rte_event_dev_close(0);