2 * SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2010-2014 Intel Corporation
4 * Copyright 2017 Cavium, Inc.
7 #include "pipeline_common.h"
9 static __rte_always_inline void
10 worker_fwd_event(struct rte_event *ev, uint8_t sched)
12 ev->event_type = RTE_EVENT_TYPE_CPU;
13 ev->op = RTE_EVENT_OP_FORWARD;
14 ev->sched_type = sched;
17 static __rte_always_inline void
18 worker_event_enqueue(const uint8_t dev, const uint8_t port,
21 while (rte_event_enqueue_burst(dev, port, ev, 1) != 1)
25 static __rte_always_inline void
26 worker_event_enqueue_burst(const uint8_t dev, const uint8_t port,
27 struct rte_event *ev, const uint16_t nb_rx)
31 enq = rte_event_enqueue_burst(dev, port, ev, nb_rx);
33 enq += rte_event_enqueue_burst(dev, port,
34 ev + enq, nb_rx - enq);
38 static __rte_always_inline void
39 worker_tx_pkt(const uint8_t dev, const uint8_t port, struct rte_event *ev)
41 exchange_mac(ev->mbuf);
42 rte_event_eth_tx_adapter_txq_set(ev->mbuf, 0);
43 while (!rte_event_eth_tx_adapter_enqueue(dev, port, ev, 1))
47 /* Single stage pipeline workers */
50 worker_do_tx_single(void *arg)
52 struct worker_data *data = (struct worker_data *)arg;
53 const uint8_t dev = data->dev_id;
54 const uint8_t port = data->port_id;
55 size_t fwd = 0, received = 0, tx = 0;
58 while (!fdata->done) {
60 if (!rte_event_dequeue_burst(dev, port, &ev, 1, 0)) {
67 if (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
68 worker_tx_pkt(dev, port, &ev);
73 worker_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);
74 worker_event_enqueue(dev, port, &ev);
80 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n",
81 rte_lcore_id(), received, fwd, tx);
86 worker_do_tx_single_atq(void *arg)
88 struct worker_data *data = (struct worker_data *)arg;
89 const uint8_t dev = data->dev_id;
90 const uint8_t port = data->port_id;
91 size_t fwd = 0, received = 0, tx = 0;
94 while (!fdata->done) {
96 if (!rte_event_dequeue_burst(dev, port, &ev, 1, 0)) {
103 if (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
104 worker_tx_pkt(dev, port, &ev);
108 worker_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);
109 worker_event_enqueue(dev, port, &ev);
115 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n",
116 rte_lcore_id(), received, fwd, tx);
121 worker_do_tx_single_burst(void *arg)
123 struct rte_event ev[BATCH_SIZE + 1];
125 struct worker_data *data = (struct worker_data *)arg;
126 const uint8_t dev = data->dev_id;
127 const uint8_t port = data->port_id;
128 size_t fwd = 0, received = 0, tx = 0;
130 while (!fdata->done) {
132 uint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev,
141 for (i = 0; i < nb_rx; i++) {
142 rte_prefetch0(ev[i + 1].mbuf);
143 if (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) {
145 worker_tx_pkt(dev, port, &ev[i]);
146 ev[i].op = RTE_EVENT_OP_RELEASE;
151 worker_fwd_event(&ev[i], RTE_SCHED_TYPE_ATOMIC);
156 worker_event_enqueue_burst(dev, port, ev, nb_rx);
161 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n",
162 rte_lcore_id(), received, fwd, tx);
167 worker_do_tx_single_burst_atq(void *arg)
169 struct rte_event ev[BATCH_SIZE + 1];
171 struct worker_data *data = (struct worker_data *)arg;
172 const uint8_t dev = data->dev_id;
173 const uint8_t port = data->port_id;
174 size_t fwd = 0, received = 0, tx = 0;
176 while (!fdata->done) {
178 uint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev,
188 for (i = 0; i < nb_rx; i++) {
189 rte_prefetch0(ev[i + 1].mbuf);
190 if (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) {
192 worker_tx_pkt(dev, port, &ev[i]);
193 ev[i].op = RTE_EVENT_OP_RELEASE;
196 worker_fwd_event(&ev[i], RTE_SCHED_TYPE_ATOMIC);
200 worker_event_enqueue_burst(dev, port, ev, nb_rx);
205 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n",
206 rte_lcore_id(), received, fwd, tx);
210 /* Multi stage Pipeline Workers */
213 worker_do_tx(void *arg)
217 struct worker_data *data = (struct worker_data *)arg;
218 const uint8_t dev = data->dev_id;
219 const uint8_t port = data->port_id;
220 const uint8_t lst_qid = cdata.num_stages - 1;
221 size_t fwd = 0, received = 0, tx = 0;
224 while (!fdata->done) {
226 if (!rte_event_dequeue_burst(dev, port, &ev, 1, 0)) {
232 const uint8_t cq_id = ev.queue_id % cdata.num_stages;
234 if (cq_id >= lst_qid) {
235 if (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
236 worker_tx_pkt(dev, port, &ev);
241 worker_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);
242 ev.queue_id = (cq_id == lst_qid) ?
243 cdata.next_qid[ev.queue_id] : ev.queue_id;
245 ev.queue_id = cdata.next_qid[ev.queue_id];
246 worker_fwd_event(&ev, cdata.queue_type);
250 worker_event_enqueue(dev, port, &ev);
255 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n",
256 rte_lcore_id(), received, fwd, tx);
262 worker_do_tx_atq(void *arg)
266 struct worker_data *data = (struct worker_data *)arg;
267 const uint8_t dev = data->dev_id;
268 const uint8_t port = data->port_id;
269 const uint8_t lst_qid = cdata.num_stages - 1;
270 size_t fwd = 0, received = 0, tx = 0;
272 while (!fdata->done) {
274 if (!rte_event_dequeue_burst(dev, port, &ev, 1, 0)) {
280 const uint8_t cq_id = ev.sub_event_type % cdata.num_stages;
282 if (cq_id == lst_qid) {
283 if (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
284 worker_tx_pkt(dev, port, &ev);
289 worker_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);
292 worker_fwd_event(&ev, cdata.queue_type);
296 worker_event_enqueue(dev, port, &ev);
301 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n",
302 rte_lcore_id(), received, fwd, tx);
308 worker_do_tx_burst(void *arg)
310 struct rte_event ev[BATCH_SIZE];
312 struct worker_data *data = (struct worker_data *)arg;
313 uint8_t dev = data->dev_id;
314 uint8_t port = data->port_id;
315 uint8_t lst_qid = cdata.num_stages - 1;
316 size_t fwd = 0, received = 0, tx = 0;
318 while (!fdata->done) {
320 const uint16_t nb_rx = rte_event_dequeue_burst(dev, port,
329 for (i = 0; i < nb_rx; i++) {
330 const uint8_t cq_id = ev[i].queue_id % cdata.num_stages;
332 if (cq_id >= lst_qid) {
333 if (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) {
334 worker_tx_pkt(dev, port, &ev[i]);
336 ev[i].op = RTE_EVENT_OP_RELEASE;
339 ev[i].queue_id = (cq_id == lst_qid) ?
340 cdata.next_qid[ev[i].queue_id] :
343 worker_fwd_event(&ev[i], RTE_SCHED_TYPE_ATOMIC);
345 ev[i].queue_id = cdata.next_qid[ev[i].queue_id];
346 worker_fwd_event(&ev[i], cdata.queue_type);
350 worker_event_enqueue_burst(dev, port, ev, nb_rx);
356 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n",
357 rte_lcore_id(), received, fwd, tx);
363 worker_do_tx_burst_atq(void *arg)
365 struct rte_event ev[BATCH_SIZE];
367 struct worker_data *data = (struct worker_data *)arg;
368 uint8_t dev = data->dev_id;
369 uint8_t port = data->port_id;
370 uint8_t lst_qid = cdata.num_stages - 1;
371 size_t fwd = 0, received = 0, tx = 0;
373 while (!fdata->done) {
376 const uint16_t nb_rx = rte_event_dequeue_burst(dev, port,
385 for (i = 0; i < nb_rx; i++) {
386 const uint8_t cq_id = ev[i].sub_event_type %
389 if (cq_id == lst_qid) {
390 if (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) {
391 worker_tx_pkt(dev, port, &ev[i]);
393 ev[i].op = RTE_EVENT_OP_RELEASE;
397 worker_fwd_event(&ev[i], RTE_SCHED_TYPE_ATOMIC);
399 ev[i].sub_event_type++;
400 worker_fwd_event(&ev[i], cdata.queue_type);
405 worker_event_enqueue_burst(dev, port, ev, nb_rx);
410 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n",
411 rte_lcore_id(), received, fwd, tx);
417 setup_eventdev_worker_tx_enq(struct worker_data *worker_data)
420 const uint8_t atq = cdata.all_type_queues ? 1 : 0;
421 const uint8_t dev_id = 0;
422 const uint8_t nb_ports = cdata.num_workers;
423 uint8_t nb_slots = 0;
424 uint8_t nb_queues = rte_eth_dev_count_avail();
427 * In case where all type queues are not enabled, use queues equal to
428 * number of stages * eth_dev_count and one extra queue per pipeline
432 nb_queues *= cdata.num_stages;
433 nb_queues += rte_eth_dev_count_avail();
436 struct rte_event_dev_config config = {
437 .nb_event_queues = nb_queues,
438 .nb_event_ports = nb_ports,
439 .nb_events_limit = 4096,
440 .nb_event_queue_flows = 1024,
441 .nb_event_port_dequeue_depth = 128,
442 .nb_event_port_enqueue_depth = 128,
444 struct rte_event_port_conf wkr_p_conf = {
445 .dequeue_depth = cdata.worker_cq_depth,
447 .new_event_threshold = 4096,
449 struct rte_event_queue_conf wkr_q_conf = {
450 .schedule_type = cdata.queue_type,
451 .priority = RTE_EVENT_DEV_PRIORITY_NORMAL,
452 .nb_atomic_flows = 1024,
453 .nb_atomic_order_sequences = 1024,
456 int ret, ndev = rte_event_dev_count();
459 printf("%d: No Eventdev Devices Found\n", __LINE__);
464 struct rte_event_dev_info dev_info;
465 ret = rte_event_dev_info_get(dev_id, &dev_info);
466 printf("\tEventdev %d: %s\n", dev_id, dev_info.driver_name);
468 if (dev_info.max_event_port_dequeue_depth <
469 config.nb_event_port_dequeue_depth)
470 config.nb_event_port_dequeue_depth =
471 dev_info.max_event_port_dequeue_depth;
472 if (dev_info.max_event_port_enqueue_depth <
473 config.nb_event_port_enqueue_depth)
474 config.nb_event_port_enqueue_depth =
475 dev_info.max_event_port_enqueue_depth;
477 ret = rte_event_dev_configure(dev_id, &config);
479 printf("%d: Error configuring device\n", __LINE__);
483 printf(" Stages:\n");
484 for (i = 0; i < nb_queues; i++) {
488 nb_slots = cdata.num_stages;
489 wkr_q_conf.event_queue_cfg =
490 RTE_EVENT_QUEUE_CFG_ALL_TYPES;
494 nb_slots = cdata.num_stages + 1;
496 wkr_q_conf.schedule_type = slot == cdata.num_stages ?
497 RTE_SCHED_TYPE_ATOMIC : cdata.queue_type;
500 if (rte_event_queue_setup(dev_id, i, &wkr_q_conf) < 0) {
501 printf("%d: error creating qid %d\n", __LINE__, i);
505 cdata.next_qid[i] = i+1;
506 if (cdata.enable_queue_priorities) {
507 const uint32_t prio_delta =
508 (RTE_EVENT_DEV_PRIORITY_LOWEST) /
511 /* higher priority for queues closer to tx */
512 wkr_q_conf.priority =
513 RTE_EVENT_DEV_PRIORITY_LOWEST - prio_delta *
517 const char *type_str = "Atomic";
518 switch (wkr_q_conf.schedule_type) {
519 case RTE_SCHED_TYPE_ORDERED:
520 type_str = "Ordered";
522 case RTE_SCHED_TYPE_PARALLEL:
523 type_str = "Parallel";
526 printf("\tStage %d, Type %s\tPriority = %d\n", i, type_str,
527 wkr_q_conf.priority);
531 if (wkr_p_conf.dequeue_depth > config.nb_event_port_dequeue_depth)
532 wkr_p_conf.dequeue_depth = config.nb_event_port_dequeue_depth;
533 if (wkr_p_conf.enqueue_depth > config.nb_event_port_enqueue_depth)
534 wkr_p_conf.enqueue_depth = config.nb_event_port_enqueue_depth;
536 /* set up one port per worker, linking to all stage queues */
537 for (i = 0; i < cdata.num_workers; i++) {
538 struct worker_data *w = &worker_data[i];
540 if (rte_event_port_setup(dev_id, i, &wkr_p_conf) < 0) {
541 printf("Error setting up port %d\n", i);
545 if (rte_event_port_link(dev_id, i, NULL, NULL, 0)
547 printf("%d: error creating link for port %d\n",
554 * Reduce the load on ingress event queue by splitting the traffic
555 * across multiple event queues.
556 * for example, nb_stages = 2 and nb_ethdev = 2 then
558 * nb_queues = (2 * 2) + 2 = 6 (non atq)
561 * So, traffic is split across queue 0 and queue 3 since queue id for
562 * rx adapter is chosen <ethport_id> * <rx_stride> i.e in the above
563 * case eth port 0, 1 will inject packets into event queue 0, 3
566 * This forms two set of queue pipelines 0->1->2->tx and 3->4->5->tx.
568 cdata.rx_stride = atq ? 1 : nb_slots;
569 ret = rte_event_dev_service_id_get(dev_id,
570 &fdata->evdev_service_id);
571 if (ret != -ESRCH && ret != 0) {
572 printf("Error getting the service ID\n");
575 rte_service_runstate_set(fdata->evdev_service_id, 1);
576 rte_service_set_runstate_mapped_check(fdata->evdev_service_id, 0);
578 if (rte_event_dev_start(dev_id) < 0)
579 rte_exit(EXIT_FAILURE, "Error starting eventdev");
585 struct rx_adptr_services {
586 uint16_t nb_rx_adptrs;
587 uint32_t *rx_adpt_arr;
591 service_rx_adapter(void *arg)
594 struct rx_adptr_services *adptr_services = arg;
596 for (i = 0; i < adptr_services->nb_rx_adptrs; i++)
597 rte_service_run_iter_on_app_lcore(
598 adptr_services->rx_adpt_arr[i], 1);
603 init_adapters(uint16_t nb_ports)
607 uint8_t evdev_id = 0;
608 struct rx_adptr_services *adptr_services = NULL;
609 struct rte_event_dev_info dev_info;
611 ret = rte_event_dev_info_get(evdev_id, &dev_info);
612 adptr_services = rte_zmalloc(NULL, sizeof(struct rx_adptr_services), 0);
614 struct rte_event_port_conf adptr_p_conf = {
615 .dequeue_depth = cdata.worker_cq_depth,
617 .new_event_threshold = 4096,
620 if (adptr_p_conf.dequeue_depth > dev_info.max_event_port_dequeue_depth)
621 adptr_p_conf.dequeue_depth =
622 dev_info.max_event_port_dequeue_depth;
623 if (adptr_p_conf.enqueue_depth > dev_info.max_event_port_enqueue_depth)
624 adptr_p_conf.enqueue_depth =
625 dev_info.max_event_port_enqueue_depth;
627 struct rte_event_eth_rx_adapter_queue_conf queue_conf;
628 memset(&queue_conf, 0, sizeof(queue_conf));
629 queue_conf.ev.sched_type = cdata.queue_type;
631 for (i = 0; i < nb_ports; i++) {
635 ret = rte_event_eth_rx_adapter_create(i, evdev_id,
638 rte_exit(EXIT_FAILURE,
639 "failed to create rx adapter[%d]", i);
641 ret = rte_event_eth_rx_adapter_caps_get(evdev_id, i, &cap);
643 rte_exit(EXIT_FAILURE,
644 "failed to get event rx adapter "
647 queue_conf.ev.queue_id = cdata.rx_stride ?
648 (i * cdata.rx_stride)
649 : (uint8_t)cdata.qid[0];
651 ret = rte_event_eth_rx_adapter_queue_add(i, i, -1, &queue_conf);
653 rte_exit(EXIT_FAILURE,
654 "Failed to add queues to Rx adapter");
656 /* Producer needs to be scheduled. */
657 if (!(cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT)) {
658 ret = rte_event_eth_rx_adapter_service_id_get(i,
660 if (ret != -ESRCH && ret != 0) {
661 rte_exit(EXIT_FAILURE,
662 "Error getting the service ID for rx adptr\n");
665 rte_service_runstate_set(service_id, 1);
666 rte_service_set_runstate_mapped_check(service_id, 0);
668 adptr_services->nb_rx_adptrs++;
669 adptr_services->rx_adpt_arr = rte_realloc(
670 adptr_services->rx_adpt_arr,
671 adptr_services->nb_rx_adptrs *
672 sizeof(uint32_t), 0);
673 adptr_services->rx_adpt_arr[
674 adptr_services->nb_rx_adptrs - 1] =
678 ret = rte_event_eth_rx_adapter_start(i);
680 rte_exit(EXIT_FAILURE, "Rx adapter[%d] start failed",
684 /* We already know that Tx adapter has INTERNAL port cap*/
685 ret = rte_event_eth_tx_adapter_create(cdata.tx_adapter_id, evdev_id,
688 rte_exit(EXIT_FAILURE, "failed to create tx adapter[%d]",
689 cdata.tx_adapter_id);
691 for (i = 0; i < nb_ports; i++) {
692 ret = rte_event_eth_tx_adapter_queue_add(cdata.tx_adapter_id, i,
695 rte_exit(EXIT_FAILURE,
696 "Failed to add queues to Tx adapter");
699 ret = rte_event_eth_tx_adapter_start(cdata.tx_adapter_id);
701 rte_exit(EXIT_FAILURE, "Tx adapter[%d] start failed",
702 cdata.tx_adapter_id);
704 if (adptr_services->nb_rx_adptrs) {
705 struct rte_service_spec service;
707 memset(&service, 0, sizeof(struct rte_service_spec));
708 snprintf(service.name, sizeof(service.name), "rx_service");
709 service.callback = service_rx_adapter;
710 service.callback_userdata = (void *)adptr_services;
712 int32_t ret = rte_service_component_register(&service,
713 &fdata->rxadptr_service_id);
715 rte_exit(EXIT_FAILURE,
716 "Rx adapter service register failed");
718 rte_service_runstate_set(fdata->rxadptr_service_id, 1);
719 rte_service_component_runstate_set(fdata->rxadptr_service_id,
721 rte_service_set_runstate_mapped_check(fdata->rxadptr_service_id,
724 memset(fdata->rx_core, 0, sizeof(unsigned int) * MAX_NUM_CORE);
725 rte_free(adptr_services);
728 if (!adptr_services->nb_rx_adptrs && (dev_info.event_dev_cap &
729 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED))
730 fdata->cap.scheduler = NULL;
734 worker_tx_enq_opt_check(void)
739 uint8_t rx_needed = 0;
740 uint8_t sched_needed = 0;
741 struct rte_event_dev_info eventdev_info;
743 memset(&eventdev_info, 0, sizeof(struct rte_event_dev_info));
744 rte_event_dev_info_get(0, &eventdev_info);
746 if (cdata.all_type_queues && !(eventdev_info.event_dev_cap &
747 RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES))
748 rte_exit(EXIT_FAILURE,
749 "Event dev doesn't support all type queues\n");
750 sched_needed = !(eventdev_info.event_dev_cap &
751 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED);
753 RTE_ETH_FOREACH_DEV(i) {
754 ret = rte_event_eth_rx_adapter_caps_get(0, i, &cap);
756 rte_exit(EXIT_FAILURE,
757 "failed to get event rx adapter capabilities");
759 !(cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT);
762 if (cdata.worker_lcore_mask == 0 ||
763 (rx_needed && cdata.rx_lcore_mask == 0) ||
764 (sched_needed && cdata.sched_lcore_mask == 0)) {
765 printf("Core part of pipeline was not assigned any cores. "
766 "This will stall the pipeline, please check core masks "
767 "(use -h for details on setting core masks):\n"
768 "\trx: %"PRIu64"\n\tsched: %"PRIu64
769 "\n\tworkers: %"PRIu64"\n", cdata.rx_lcore_mask,
770 cdata.sched_lcore_mask, cdata.worker_lcore_mask);
771 rte_exit(-1, "Fix core masks\n");
775 memset(fdata->sched_core, 0,
776 sizeof(unsigned int) * MAX_NUM_CORE);
778 memset(fdata->rx_core, 0,
779 sizeof(unsigned int) * MAX_NUM_CORE);
781 memset(fdata->tx_core, 0, sizeof(unsigned int) * MAX_NUM_CORE);
785 get_worker_loop_single_burst(uint8_t atq)
788 return worker_do_tx_single_burst_atq;
790 return worker_do_tx_single_burst;
794 get_worker_loop_single_non_burst(uint8_t atq)
797 return worker_do_tx_single_atq;
799 return worker_do_tx_single;
803 get_worker_loop_burst(uint8_t atq)
806 return worker_do_tx_burst_atq;
808 return worker_do_tx_burst;
812 get_worker_loop_non_burst(uint8_t atq)
815 return worker_do_tx_atq;
821 get_worker_single_stage(bool burst)
823 uint8_t atq = cdata.all_type_queues ? 1 : 0;
826 return get_worker_loop_single_burst(atq);
828 return get_worker_loop_single_non_burst(atq);
832 get_worker_multi_stage(bool burst)
834 uint8_t atq = cdata.all_type_queues ? 1 : 0;
837 return get_worker_loop_burst(atq);
839 return get_worker_loop_non_burst(atq);
843 set_worker_tx_enq_setup_data(struct setup_data *caps, bool burst)
845 if (cdata.num_stages == 1)
846 caps->worker = get_worker_single_stage(burst);
848 caps->worker = get_worker_multi_stage(burst);
850 caps->check_opt = worker_tx_enq_opt_check;
851 caps->scheduler = schedule_devices;
852 caps->evdev_setup = setup_eventdev_worker_tx_enq;
853 caps->adptr_setup = init_adapters;