2 * SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2010-2014 Intel Corporation
4 * Copyright 2017 Cavium, Inc.
7 #include "pipeline_common.h"
9 static __rte_always_inline void
10 worker_fwd_event(struct rte_event *ev, uint8_t sched)
12 ev->event_type = RTE_EVENT_TYPE_CPU;
13 ev->op = RTE_EVENT_OP_FORWARD;
14 ev->sched_type = sched;
17 static __rte_always_inline void
18 worker_event_enqueue(const uint8_t dev, const uint8_t port,
21 while (!rte_event_enqueue_burst(dev, port, ev, 1) && !fdata->done)
25 static __rte_always_inline uint16_t
26 worker_event_enqueue_burst(const uint8_t dev, const uint8_t port,
27 struct rte_event *ev, const uint16_t nb_rx)
31 enq = rte_event_enqueue_burst(dev, port, ev, nb_rx);
32 while (enq < nb_rx && !fdata->done)
33 enq += rte_event_enqueue_burst(dev, port,
34 ev + enq, nb_rx - enq);
39 static __rte_always_inline void
40 worker_tx_pkt(const uint8_t dev, const uint8_t port, struct rte_event *ev)
42 exchange_mac(ev->mbuf);
43 rte_event_eth_tx_adapter_txq_set(ev->mbuf, 0);
44 while (!rte_event_eth_tx_adapter_enqueue(dev, port, ev, 1, 0) &&
49 /* Single stage pipeline workers */
52 worker_do_tx_single(void *arg)
54 struct worker_data *data = (struct worker_data *)arg;
55 const uint8_t dev = data->dev_id;
56 const uint8_t port = data->port_id;
57 size_t fwd = 0, received = 0, tx = 0;
60 while (!fdata->done) {
62 if (!rte_event_dequeue_burst(dev, port, &ev, 1, 0)) {
69 if (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
70 worker_tx_pkt(dev, port, &ev);
75 worker_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);
76 worker_event_enqueue(dev, port, &ev);
82 ev.op = RTE_EVENT_OP_RELEASE;
83 rte_event_enqueue_burst(dev, port, &ev, 1);
87 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n",
88 rte_lcore_id(), received, fwd, tx);
93 worker_do_tx_single_atq(void *arg)
95 struct worker_data *data = (struct worker_data *)arg;
96 const uint8_t dev = data->dev_id;
97 const uint8_t port = data->port_id;
98 size_t fwd = 0, received = 0, tx = 0;
101 while (!fdata->done) {
103 if (!rte_event_dequeue_burst(dev, port, &ev, 1, 0)) {
110 if (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
111 worker_tx_pkt(dev, port, &ev);
115 worker_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);
116 worker_event_enqueue(dev, port, &ev);
122 ev.op = RTE_EVENT_OP_RELEASE;
123 rte_event_enqueue_burst(dev, port, &ev, 1);
127 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n",
128 rte_lcore_id(), received, fwd, tx);
133 worker_do_tx_single_burst(void *arg)
135 struct rte_event ev[BATCH_SIZE + 1];
137 struct worker_data *data = (struct worker_data *)arg;
138 const uint8_t dev = data->dev_id;
139 const uint8_t port = data->port_id;
140 size_t fwd = 0, received = 0, tx = 0;
141 uint16_t nb_tx = 0, nb_rx = 0, i;
143 while (!fdata->done) {
144 nb_rx = rte_event_dequeue_burst(dev, port, ev, BATCH_SIZE, 0);
152 for (i = 0; i < nb_rx; i++) {
153 rte_prefetch0(ev[i + 1].mbuf);
154 if (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) {
156 worker_tx_pkt(dev, port, &ev[i]);
157 ev[i].op = RTE_EVENT_OP_RELEASE;
162 worker_fwd_event(&ev[i], RTE_SCHED_TYPE_ATOMIC);
167 nb_tx = worker_event_enqueue_burst(dev, port, ev, nb_rx);
171 worker_cleanup(dev, port, ev, nb_tx, nb_rx);
174 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n",
175 rte_lcore_id(), received, fwd, tx);
180 worker_do_tx_single_burst_atq(void *arg)
182 struct rte_event ev[BATCH_SIZE + 1];
184 struct worker_data *data = (struct worker_data *)arg;
185 const uint8_t dev = data->dev_id;
186 const uint8_t port = data->port_id;
187 size_t fwd = 0, received = 0, tx = 0;
188 uint16_t i, nb_rx = 0, nb_tx = 0;
190 while (!fdata->done) {
191 nb_rx = rte_event_dequeue_burst(dev, port, ev, BATCH_SIZE, 0);
200 for (i = 0; i < nb_rx; i++) {
201 rte_prefetch0(ev[i + 1].mbuf);
202 if (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) {
204 worker_tx_pkt(dev, port, &ev[i]);
205 ev[i].op = RTE_EVENT_OP_RELEASE;
208 worker_fwd_event(&ev[i], RTE_SCHED_TYPE_ATOMIC);
212 nb_tx = worker_event_enqueue_burst(dev, port, ev, nb_rx);
216 worker_cleanup(dev, port, ev, nb_tx, nb_rx);
219 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n",
220 rte_lcore_id(), received, fwd, tx);
224 /* Multi stage Pipeline Workers */
227 worker_do_tx(void *arg)
231 struct worker_data *data = (struct worker_data *)arg;
232 const uint8_t dev = data->dev_id;
233 const uint8_t port = data->port_id;
234 const uint8_t lst_qid = cdata.num_stages - 1;
235 size_t fwd = 0, received = 0, tx = 0;
238 while (!fdata->done) {
240 if (!rte_event_dequeue_burst(dev, port, &ev, 1, 0)) {
246 const uint8_t cq_id = ev.queue_id % cdata.num_stages;
248 if (cq_id >= lst_qid) {
249 if (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
250 worker_tx_pkt(dev, port, &ev);
255 worker_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);
256 ev.queue_id = (cq_id == lst_qid) ?
257 cdata.next_qid[ev.queue_id] : ev.queue_id;
259 ev.queue_id = cdata.next_qid[ev.queue_id];
260 worker_fwd_event(&ev, cdata.queue_type);
264 worker_event_enqueue(dev, port, &ev);
269 ev.op = RTE_EVENT_OP_RELEASE;
270 rte_event_enqueue_burst(dev, port, &ev, 1);
274 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n",
275 rte_lcore_id(), received, fwd, tx);
281 worker_do_tx_atq(void *arg)
285 struct worker_data *data = (struct worker_data *)arg;
286 const uint8_t dev = data->dev_id;
287 const uint8_t port = data->port_id;
288 const uint8_t lst_qid = cdata.num_stages - 1;
289 size_t fwd = 0, received = 0, tx = 0;
291 while (!fdata->done) {
293 if (!rte_event_dequeue_burst(dev, port, &ev, 1, 0)) {
299 const uint8_t cq_id = ev.sub_event_type % cdata.num_stages;
301 if (cq_id == lst_qid) {
302 if (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
303 worker_tx_pkt(dev, port, &ev);
308 worker_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);
311 worker_fwd_event(&ev, cdata.queue_type);
315 worker_event_enqueue(dev, port, &ev);
320 ev.op = RTE_EVENT_OP_RELEASE;
321 rte_event_enqueue_burst(dev, port, &ev, 1);
325 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n",
326 rte_lcore_id(), received, fwd, tx);
332 worker_do_tx_burst(void *arg)
334 struct rte_event ev[BATCH_SIZE];
336 struct worker_data *data = (struct worker_data *)arg;
337 uint8_t dev = data->dev_id;
338 uint8_t port = data->port_id;
339 uint8_t lst_qid = cdata.num_stages - 1;
340 size_t fwd = 0, received = 0, tx = 0;
341 uint16_t i, nb_rx = 0, nb_tx = 0;
343 while (!fdata->done) {
344 nb_rx = rte_event_dequeue_burst(dev, port, ev, BATCH_SIZE, 0);
352 for (i = 0; i < nb_rx; i++) {
353 const uint8_t cq_id = ev[i].queue_id % cdata.num_stages;
355 if (cq_id >= lst_qid) {
356 if (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) {
357 worker_tx_pkt(dev, port, &ev[i]);
359 ev[i].op = RTE_EVENT_OP_RELEASE;
362 ev[i].queue_id = (cq_id == lst_qid) ?
363 cdata.next_qid[ev[i].queue_id] :
366 worker_fwd_event(&ev[i], RTE_SCHED_TYPE_ATOMIC);
368 ev[i].queue_id = cdata.next_qid[ev[i].queue_id];
369 worker_fwd_event(&ev[i], cdata.queue_type);
374 nb_tx = worker_event_enqueue_burst(dev, port, ev, nb_rx);
378 worker_cleanup(dev, port, ev, nb_tx, nb_rx);
381 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n",
382 rte_lcore_id(), received, fwd, tx);
388 worker_do_tx_burst_atq(void *arg)
390 struct rte_event ev[BATCH_SIZE];
392 struct worker_data *data = (struct worker_data *)arg;
393 uint8_t dev = data->dev_id;
394 uint8_t port = data->port_id;
395 uint8_t lst_qid = cdata.num_stages - 1;
396 size_t fwd = 0, received = 0, tx = 0;
397 uint16_t i, nb_rx = 0, nb_tx = 0;
399 while (!fdata->done) {
400 nb_rx = rte_event_dequeue_burst(dev, port, ev, BATCH_SIZE, 0);
408 for (i = 0; i < nb_rx; i++) {
409 const uint8_t cq_id = ev[i].sub_event_type %
412 if (cq_id == lst_qid) {
413 if (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) {
414 worker_tx_pkt(dev, port, &ev[i]);
416 ev[i].op = RTE_EVENT_OP_RELEASE;
420 worker_fwd_event(&ev[i], RTE_SCHED_TYPE_ATOMIC);
422 ev[i].sub_event_type++;
423 worker_fwd_event(&ev[i], cdata.queue_type);
428 nb_tx = worker_event_enqueue_burst(dev, port, ev, nb_rx);
432 worker_cleanup(dev, port, ev, nb_tx, nb_rx);
435 printf(" worker %u thread done. RX=%zu FWD=%zu TX=%zu\n",
436 rte_lcore_id(), received, fwd, tx);
442 setup_eventdev_worker_tx_enq(struct worker_data *worker_data)
445 const uint8_t atq = cdata.all_type_queues ? 1 : 0;
446 const uint8_t dev_id = 0;
447 const uint8_t nb_ports = cdata.num_workers;
448 uint8_t nb_slots = 0;
449 uint8_t nb_queues = rte_eth_dev_count_avail();
452 * In case where all type queues are not enabled, use queues equal to
453 * number of stages * eth_dev_count and one extra queue per pipeline
457 nb_queues *= cdata.num_stages;
458 nb_queues += rte_eth_dev_count_avail();
461 struct rte_event_dev_config config = {
462 .nb_event_queues = nb_queues,
463 .nb_event_ports = nb_ports,
464 .nb_single_link_event_port_queues = 0,
465 .nb_events_limit = 4096,
466 .nb_event_queue_flows = 1024,
467 .nb_event_port_dequeue_depth = 128,
468 .nb_event_port_enqueue_depth = 128,
470 struct rte_event_port_conf wkr_p_conf = {
471 .dequeue_depth = cdata.worker_cq_depth,
473 .new_event_threshold = 4096,
474 .event_port_cfg = RTE_EVENT_PORT_CFG_HINT_WORKER,
476 struct rte_event_queue_conf wkr_q_conf = {
477 .schedule_type = cdata.queue_type,
478 .priority = RTE_EVENT_DEV_PRIORITY_NORMAL,
479 .nb_atomic_flows = 1024,
480 .nb_atomic_order_sequences = 1024,
483 int ret, ndev = rte_event_dev_count();
486 printf("%d: No Eventdev Devices Found\n", __LINE__);
491 struct rte_event_dev_info dev_info;
492 ret = rte_event_dev_info_get(dev_id, &dev_info);
493 printf("\tEventdev %d: %s\n", dev_id, dev_info.driver_name);
495 if (dev_info.max_num_events < config.nb_events_limit)
496 config.nb_events_limit = dev_info.max_num_events;
497 if (dev_info.max_event_port_dequeue_depth <
498 config.nb_event_port_dequeue_depth)
499 config.nb_event_port_dequeue_depth =
500 dev_info.max_event_port_dequeue_depth;
501 if (dev_info.max_event_port_enqueue_depth <
502 config.nb_event_port_enqueue_depth)
503 config.nb_event_port_enqueue_depth =
504 dev_info.max_event_port_enqueue_depth;
506 ret = rte_event_dev_configure(dev_id, &config);
508 printf("%d: Error configuring device\n", __LINE__);
512 printf(" Stages:\n");
513 for (i = 0; i < nb_queues; i++) {
517 nb_slots = cdata.num_stages;
518 wkr_q_conf.event_queue_cfg =
519 RTE_EVENT_QUEUE_CFG_ALL_TYPES;
523 nb_slots = cdata.num_stages + 1;
525 wkr_q_conf.schedule_type = slot == cdata.num_stages ?
526 RTE_SCHED_TYPE_ATOMIC : cdata.queue_type;
529 if (rte_event_queue_setup(dev_id, i, &wkr_q_conf) < 0) {
530 printf("%d: error creating qid %d\n", __LINE__, i);
534 cdata.next_qid[i] = i+1;
535 if (cdata.enable_queue_priorities) {
536 const uint32_t prio_delta =
537 (RTE_EVENT_DEV_PRIORITY_LOWEST) /
540 /* higher priority for queues closer to tx */
541 wkr_q_conf.priority =
542 RTE_EVENT_DEV_PRIORITY_LOWEST - prio_delta *
546 const char *type_str = "Atomic";
547 switch (wkr_q_conf.schedule_type) {
548 case RTE_SCHED_TYPE_ORDERED:
549 type_str = "Ordered";
551 case RTE_SCHED_TYPE_PARALLEL:
552 type_str = "Parallel";
555 printf("\tStage %d, Type %s\tPriority = %d\n", i, type_str,
556 wkr_q_conf.priority);
560 if (wkr_p_conf.new_event_threshold > config.nb_events_limit)
561 wkr_p_conf.new_event_threshold = config.nb_events_limit;
562 if (wkr_p_conf.dequeue_depth > config.nb_event_port_dequeue_depth)
563 wkr_p_conf.dequeue_depth = config.nb_event_port_dequeue_depth;
564 if (wkr_p_conf.enqueue_depth > config.nb_event_port_enqueue_depth)
565 wkr_p_conf.enqueue_depth = config.nb_event_port_enqueue_depth;
567 /* set up one port per worker, linking to all stage queues */
568 for (i = 0; i < cdata.num_workers; i++) {
569 struct worker_data *w = &worker_data[i];
571 if (rte_event_port_setup(dev_id, i, &wkr_p_conf) < 0) {
572 printf("Error setting up port %d\n", i);
576 if (rte_event_port_link(dev_id, i, NULL, NULL, 0)
578 printf("%d: error creating link for port %d\n",
585 * Reduce the load on ingress event queue by splitting the traffic
586 * across multiple event queues.
587 * for example, nb_stages = 2 and nb_ethdev = 2 then
589 * nb_queues = (2 * 2) + 2 = 6 (non atq)
592 * So, traffic is split across queue 0 and queue 3 since queue id for
593 * rx adapter is chosen <ethport_id> * <rx_stride> i.e in the above
594 * case eth port 0, 1 will inject packets into event queue 0, 3
597 * This forms two set of queue pipelines 0->1->2->tx and 3->4->5->tx.
599 cdata.rx_stride = atq ? 1 : nb_slots;
600 ret = rte_event_dev_service_id_get(dev_id,
601 &fdata->evdev_service_id);
602 if (ret != -ESRCH && ret != 0) {
603 printf("Error getting the service ID\n");
606 rte_service_runstate_set(fdata->evdev_service_id, 1);
607 rte_service_set_runstate_mapped_check(fdata->evdev_service_id, 0);
609 if (rte_event_dev_start(dev_id) < 0)
610 rte_exit(EXIT_FAILURE, "Error starting eventdev");
616 struct rx_adptr_services {
617 uint16_t nb_rx_adptrs;
618 uint32_t *rx_adpt_arr;
622 service_rx_adapter(void *arg)
625 struct rx_adptr_services *adptr_services = arg;
627 for (i = 0; i < adptr_services->nb_rx_adptrs; i++)
628 rte_service_run_iter_on_app_lcore(
629 adptr_services->rx_adpt_arr[i], 1);
634 * Initializes a given port using global settings and with the RX buffers
635 * coming from the mbuf_pool passed as a parameter.
638 port_init(uint8_t port, struct rte_mempool *mbuf_pool)
640 struct rte_eth_rxconf rx_conf;
641 static const struct rte_eth_conf port_conf_default = {
643 .mq_mode = RTE_ETH_MQ_RX_RSS,
647 .rss_hf = RTE_ETH_RSS_IP |
653 const uint16_t rx_rings = 1, tx_rings = 1;
654 const uint16_t rx_ring_size = 512, tx_ring_size = 512;
655 struct rte_eth_conf port_conf = port_conf_default;
658 struct rte_eth_dev_info dev_info;
659 struct rte_eth_txconf txconf;
661 if (!rte_eth_dev_is_valid_port(port))
664 retval = rte_eth_dev_info_get(port, &dev_info);
666 printf("Error during getting device (port %u) info: %s\n",
667 port, strerror(-retval));
671 if (dev_info.tx_offload_capa & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE)
672 port_conf.txmode.offloads |=
673 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
674 rx_conf = dev_info.default_rxconf;
675 rx_conf.offloads = port_conf.rxmode.offloads;
677 port_conf.rx_adv_conf.rss_conf.rss_hf &=
678 dev_info.flow_type_rss_offloads;
679 if (port_conf.rx_adv_conf.rss_conf.rss_hf !=
680 port_conf_default.rx_adv_conf.rss_conf.rss_hf) {
681 printf("Port %u modified RSS hash function based on hardware support,"
682 "requested:%#"PRIx64" configured:%#"PRIx64"\n",
684 port_conf_default.rx_adv_conf.rss_conf.rss_hf,
685 port_conf.rx_adv_conf.rss_conf.rss_hf);
688 /* Configure the Ethernet device. */
689 retval = rte_eth_dev_configure(port, rx_rings, tx_rings, &port_conf);
693 /* Allocate and set up 1 RX queue per Ethernet port. */
694 for (q = 0; q < rx_rings; q++) {
695 retval = rte_eth_rx_queue_setup(port, q, rx_ring_size,
696 rte_eth_dev_socket_id(port), &rx_conf,
702 txconf = dev_info.default_txconf;
703 txconf.offloads = port_conf_default.txmode.offloads;
704 /* Allocate and set up 1 TX queue per Ethernet port. */
705 for (q = 0; q < tx_rings; q++) {
706 retval = rte_eth_tx_queue_setup(port, q, tx_ring_size,
707 rte_eth_dev_socket_id(port), &txconf);
712 /* Display the port MAC address. */
713 struct rte_ether_addr addr;
714 retval = rte_eth_macaddr_get(port, &addr);
716 printf("Failed to get MAC address (port %u): %s\n",
717 port, rte_strerror(-retval));
721 printf("Port %u MAC: %02" PRIx8 " %02" PRIx8 " %02" PRIx8
722 " %02" PRIx8 " %02" PRIx8 " %02" PRIx8 "\n",
723 (unsigned int)port, RTE_ETHER_ADDR_BYTES(&addr));
725 /* Enable RX in promiscuous mode for the Ethernet device. */
726 retval = rte_eth_promiscuous_enable(port);
734 init_ports(uint16_t num_ports)
739 cdata.num_mbuf = 16384 * num_ports;
741 struct rte_mempool *mp = rte_pktmbuf_pool_create("packet_pool",
742 /* mbufs */ cdata.num_mbuf,
743 /* cache_size */ 512,
745 /* data_room_size */ RTE_MBUF_DEFAULT_BUF_SIZE,
748 RTE_ETH_FOREACH_DEV(portid)
749 if (port_init(portid, mp) != 0)
750 rte_exit(EXIT_FAILURE, "Cannot init port %"PRIu16 "\n",
757 init_adapters(uint16_t nb_ports)
761 uint8_t evdev_id = 0;
762 struct rx_adptr_services *adptr_services = NULL;
763 struct rte_event_dev_info dev_info;
765 ret = rte_event_dev_info_get(evdev_id, &dev_info);
766 adptr_services = rte_zmalloc(NULL, sizeof(struct rx_adptr_services), 0);
768 struct rte_event_port_conf adptr_p_conf = {
769 .dequeue_depth = cdata.worker_cq_depth,
771 .new_event_threshold = 4096,
772 .event_port_cfg = RTE_EVENT_PORT_CFG_HINT_PRODUCER,
775 init_ports(nb_ports);
776 if (adptr_p_conf.new_event_threshold > dev_info.max_num_events)
777 adptr_p_conf.new_event_threshold = dev_info.max_num_events;
778 if (adptr_p_conf.dequeue_depth > dev_info.max_event_port_dequeue_depth)
779 adptr_p_conf.dequeue_depth =
780 dev_info.max_event_port_dequeue_depth;
781 if (adptr_p_conf.enqueue_depth > dev_info.max_event_port_enqueue_depth)
782 adptr_p_conf.enqueue_depth =
783 dev_info.max_event_port_enqueue_depth;
785 struct rte_event_eth_rx_adapter_queue_conf queue_conf;
786 memset(&queue_conf, 0, sizeof(queue_conf));
787 queue_conf.ev.sched_type = cdata.queue_type;
789 for (i = 0; i < nb_ports; i++) {
793 ret = rte_event_eth_rx_adapter_create(i, evdev_id,
796 rte_exit(EXIT_FAILURE,
797 "failed to create rx adapter[%d]", i);
799 ret = rte_event_eth_rx_adapter_caps_get(evdev_id, i, &cap);
801 rte_exit(EXIT_FAILURE,
802 "failed to get event rx adapter "
805 queue_conf.ev.queue_id = cdata.rx_stride ?
806 (i * cdata.rx_stride)
807 : (uint8_t)cdata.qid[0];
809 ret = rte_event_eth_rx_adapter_queue_add(i, i, -1, &queue_conf);
811 rte_exit(EXIT_FAILURE,
812 "Failed to add queues to Rx adapter");
814 /* Producer needs to be scheduled. */
815 if (!(cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT)) {
816 ret = rte_event_eth_rx_adapter_service_id_get(i,
818 if (ret != -ESRCH && ret != 0) {
819 rte_exit(EXIT_FAILURE,
820 "Error getting the service ID for rx adptr\n");
823 rte_service_runstate_set(service_id, 1);
824 rte_service_set_runstate_mapped_check(service_id, 0);
826 adptr_services->nb_rx_adptrs++;
827 adptr_services->rx_adpt_arr = rte_realloc(
828 adptr_services->rx_adpt_arr,
829 adptr_services->nb_rx_adptrs *
830 sizeof(uint32_t), 0);
831 adptr_services->rx_adpt_arr[
832 adptr_services->nb_rx_adptrs - 1] =
836 ret = rte_event_eth_rx_adapter_start(i);
838 rte_exit(EXIT_FAILURE, "Rx adapter[%d] start failed",
842 /* We already know that Tx adapter has INTERNAL port cap*/
843 ret = rte_event_eth_tx_adapter_create(cdata.tx_adapter_id, evdev_id,
846 rte_exit(EXIT_FAILURE, "failed to create tx adapter[%d]",
847 cdata.tx_adapter_id);
849 for (i = 0; i < nb_ports; i++) {
850 ret = rte_event_eth_tx_adapter_queue_add(cdata.tx_adapter_id, i,
853 rte_exit(EXIT_FAILURE,
854 "Failed to add queues to Tx adapter");
857 ret = rte_event_eth_tx_adapter_start(cdata.tx_adapter_id);
859 rte_exit(EXIT_FAILURE, "Tx adapter[%d] start failed",
860 cdata.tx_adapter_id);
862 if (adptr_services->nb_rx_adptrs) {
863 struct rte_service_spec service;
865 memset(&service, 0, sizeof(struct rte_service_spec));
866 snprintf(service.name, sizeof(service.name), "rx_service");
867 service.callback = service_rx_adapter;
868 service.callback_userdata = (void *)adptr_services;
870 int32_t ret = rte_service_component_register(&service,
871 &fdata->rxadptr_service_id);
873 rte_exit(EXIT_FAILURE,
874 "Rx adapter service register failed");
876 rte_service_runstate_set(fdata->rxadptr_service_id, 1);
877 rte_service_component_runstate_set(fdata->rxadptr_service_id,
879 rte_service_set_runstate_mapped_check(fdata->rxadptr_service_id,
882 memset(fdata->rx_core, 0, sizeof(unsigned int) * MAX_NUM_CORE);
883 rte_free(adptr_services);
886 if (!adptr_services->nb_rx_adptrs && (dev_info.event_dev_cap &
887 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED))
888 fdata->cap.scheduler = NULL;
892 worker_tx_enq_opt_check(void)
897 uint8_t rx_needed = 0;
898 uint8_t sched_needed = 0;
899 struct rte_event_dev_info eventdev_info;
901 memset(&eventdev_info, 0, sizeof(struct rte_event_dev_info));
902 rte_event_dev_info_get(0, &eventdev_info);
904 if (cdata.all_type_queues && !(eventdev_info.event_dev_cap &
905 RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES))
906 rte_exit(EXIT_FAILURE,
907 "Event dev doesn't support all type queues\n");
908 sched_needed = !(eventdev_info.event_dev_cap &
909 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED);
911 RTE_ETH_FOREACH_DEV(i) {
912 ret = rte_event_eth_rx_adapter_caps_get(0, i, &cap);
914 rte_exit(EXIT_FAILURE,
915 "failed to get event rx adapter capabilities");
917 !(cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT);
920 if (cdata.worker_lcore_mask == 0 ||
921 (rx_needed && cdata.rx_lcore_mask == 0) ||
922 (sched_needed && cdata.sched_lcore_mask == 0)) {
923 printf("Core part of pipeline was not assigned any cores. "
924 "This will stall the pipeline, please check core masks "
925 "(use -h for details on setting core masks):\n"
926 "\trx: %"PRIu64"\n\tsched: %"PRIu64
927 "\n\tworkers: %"PRIu64"\n", cdata.rx_lcore_mask,
928 cdata.sched_lcore_mask, cdata.worker_lcore_mask);
929 rte_exit(-1, "Fix core masks\n");
933 memset(fdata->sched_core, 0,
934 sizeof(unsigned int) * MAX_NUM_CORE);
936 memset(fdata->rx_core, 0,
937 sizeof(unsigned int) * MAX_NUM_CORE);
939 memset(fdata->tx_core, 0, sizeof(unsigned int) * MAX_NUM_CORE);
943 get_worker_loop_single_burst(uint8_t atq)
946 return worker_do_tx_single_burst_atq;
948 return worker_do_tx_single_burst;
952 get_worker_loop_single_non_burst(uint8_t atq)
955 return worker_do_tx_single_atq;
957 return worker_do_tx_single;
961 get_worker_loop_burst(uint8_t atq)
964 return worker_do_tx_burst_atq;
966 return worker_do_tx_burst;
970 get_worker_loop_non_burst(uint8_t atq)
973 return worker_do_tx_atq;
979 get_worker_single_stage(bool burst)
981 uint8_t atq = cdata.all_type_queues ? 1 : 0;
984 return get_worker_loop_single_burst(atq);
986 return get_worker_loop_single_non_burst(atq);
990 get_worker_multi_stage(bool burst)
992 uint8_t atq = cdata.all_type_queues ? 1 : 0;
995 return get_worker_loop_burst(atq);
997 return get_worker_loop_non_burst(atq);
1001 set_worker_tx_enq_setup_data(struct setup_data *caps, bool burst)
1003 if (cdata.num_stages == 1)
1004 caps->worker = get_worker_single_stage(burst);
1006 caps->worker = get_worker_multi_stage(burst);
1008 caps->check_opt = worker_tx_enq_opt_check;
1009 caps->scheduler = schedule_devices;
1010 caps->evdev_setup = setup_eventdev_worker_tx_enq;
1011 caps->adptr_setup = init_adapters;