examples/eventdev_pipeline_sw_pmd/main.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2016-2017 Intel Corporation. All rights reserved.
   5  *
   6  *   Redistribution and use in source and binary forms, with or without
   7  *   modification, are permitted provided that the following conditions
   8  *   are met:
   9  *
  10  *     * Redistributions of source code must retain the above copyright
  11  *       notice, this list of conditions and the following disclaimer.
  12  *     * Redistributions in binary form must reproduce the above copyright
  13  *       notice, this list of conditions and the following disclaimer in
  14  *       the documentation and/or other materials provided with the
  15  *       distribution.
  16  *     * Neither the name of Intel Corporation nor the names of its
  17  *       contributors may be used to endorse or promote products derived
  18  *       from this software without specific prior written permission.
  19  *
  20  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <getopt.h>
  34 #include <stdint.h>
  35 #include <stdio.h>
  36 #include <signal.h>
  37 #include <sched.h>
  38 #include <stdbool.h>
  39
  40 #include <rte_eal.h>
  41 #include <rte_mempool.h>
  42 #include <rte_mbuf.h>
  43 #include <rte_launch.h>
  44 #include <rte_malloc.h>
  45 #include <rte_random.h>
  46 #include <rte_cycles.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_eventdev.h>
  49
  50 #define MAX_NUM_STAGES 8
  51 #define BATCH_SIZE 16
  52 #define MAX_NUM_CORE 64
  53
  54 struct prod_data {
  55         uint8_t dev_id;
  56         uint8_t port_id;
  57         int32_t qid;
  58         unsigned int num_nic_ports;
  59 } __rte_cache_aligned;
  60
  61 struct cons_data {
  62         uint8_t dev_id;
  63         uint8_t port_id;
  64 } __rte_cache_aligned;
  65
  66 static struct prod_data prod_data;
  67 static struct cons_data cons_data;
  68
  69 struct worker_data {
  70         uint8_t dev_id;
  71         uint8_t port_id;
  72 } __rte_cache_aligned;
  73
  74 struct fastpath_data {
  75         volatile int done;
  76         uint32_t rx_lock;
  77         uint32_t tx_lock;
  78         uint32_t sched_lock;
  79         bool rx_single;
  80         bool tx_single;
  81         bool sched_single;
  82         unsigned int rx_core[MAX_NUM_CORE];
  83         unsigned int tx_core[MAX_NUM_CORE];
  84         unsigned int sched_core[MAX_NUM_CORE];
  85         unsigned int worker_core[MAX_NUM_CORE];
  86         struct rte_eth_dev_tx_buffer *tx_buf[RTE_MAX_ETHPORTS];
  87 };
  88
  89 static struct fastpath_data *fdata;
  90
  91 struct config_data {
  92         unsigned int active_cores;
  93         unsigned int num_workers;
  94         long num_packets;
  95         unsigned int num_fids;
  96         int queue_type;
  97         int worker_cycles;
  98         int enable_queue_priorities;
  99         int quiet;
 100         int dump_dev;
 101         int dump_dev_signal;
 102         unsigned int num_stages;
 103         unsigned int worker_cq_depth;
 104         int16_t next_qid[MAX_NUM_STAGES+2];
 105         int16_t qid[MAX_NUM_STAGES];
 106 };
 107
 108 static struct config_data cdata = {
 109         .num_packets = (1L << 25), /* do ~32M packets */
 110         .num_fids = 512,
 111         .queue_type = RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY,
 112         .next_qid = {-1},
 113         .qid = {-1},
 114         .num_stages = 1,
 115         .worker_cq_depth = 16
 116 };
 117
 118 static bool
 119 core_in_use(unsigned int lcore_id) {
 120         return (fdata->rx_core[lcore_id] || fdata->sched_core[lcore_id] ||
 121                 fdata->tx_core[lcore_id] || fdata->worker_core[lcore_id]);
 122 }
 123
 124
 125 static void
 126 eth_tx_buffer_retry(struct rte_mbuf **pkts, uint16_t unsent,
 127                         void *userdata)
 128 {
 129         int port_id = (uintptr_t) userdata;
 130         unsigned int _sent = 0;
 131
 132         do {
 133                 /* Note: hard-coded TX queue */
 134                 _sent += rte_eth_tx_burst(port_id, 0, &pkts[_sent],
 135                                           unsent - _sent);
 136         } while (_sent != unsent);
 137 }
 138
 139 static int
 140 consumer(void)
 141 {
 142         const uint64_t freq_khz = rte_get_timer_hz() / 1000;
 143         struct rte_event packets[BATCH_SIZE];
 144
 145         static uint64_t received;
 146         static uint64_t last_pkts;
 147         static uint64_t last_time;
 148         static uint64_t start_time;
 149         unsigned int i, j;
 150         uint8_t dev_id = cons_data.dev_id;
 151         uint8_t port_id = cons_data.port_id;
 152
 153         uint16_t n = rte_event_dequeue_burst(dev_id, port_id,
 154                         packets, RTE_DIM(packets), 0);
 155
 156         if (n == 0) {
 157                 for (j = 0; j < rte_eth_dev_count(); j++)
 158                         rte_eth_tx_buffer_flush(j, 0, fdata->tx_buf[j]);
 159                 return 0;
 160         }
 161         if (start_time == 0)
 162                 last_time = start_time = rte_get_timer_cycles();
 163
 164         received += n;
 165         for (i = 0; i < n; i++) {
 166                 uint8_t outport = packets[i].mbuf->port;
 167                 rte_eth_tx_buffer(outport, 0, fdata->tx_buf[outport],
 168                                 packets[i].mbuf);
 169         }
 170
 171         /* Print out mpps every 1<22 packets */
 172         if (!cdata.quiet && received >= last_pkts + (1<<22)) {
 173                 const uint64_t now = rte_get_timer_cycles();
 174                 const uint64_t total_ms = (now - start_time) / freq_khz;
 175                 const uint64_t delta_ms = (now - last_time) / freq_khz;
 176                 uint64_t delta_pkts = received - last_pkts;
 177
 178                 printf("# consumer RX=%"PRIu64", time %"PRIu64 "ms, "
 179                         "avg %.3f mpps [current %.3f mpps]\n",
 180                                 received,
 181                                 total_ms,
 182                                 received / (total_ms * 1000.0),
 183                                 delta_pkts / (delta_ms * 1000.0));
 184                 last_pkts = received;
 185                 last_time = now;
 186         }
 187
 188         cdata.num_packets -= n;
 189         if (cdata.num_packets <= 0)
 190                 fdata->done = 1;
 191
 192         return 0;
 193 }
 194
 195 static int
 196 producer(void)
 197 {
 198         static uint8_t eth_port;
 199         struct rte_mbuf *mbufs[BATCH_SIZE+2];
 200         struct rte_event ev[BATCH_SIZE+2];
 201         uint32_t i, num_ports = prod_data.num_nic_ports;
 202         int32_t qid = prod_data.qid;
 203         uint8_t dev_id = prod_data.dev_id;
 204         uint8_t port_id = prod_data.port_id;
 205         uint32_t prio_idx = 0;
 206
 207         const uint16_t nb_rx = rte_eth_rx_burst(eth_port, 0, mbufs, BATCH_SIZE);
 208         if (++eth_port == num_ports)
 209                 eth_port = 0;
 210         if (nb_rx == 0) {
 211                 rte_pause();
 212                 return 0;
 213         }
 214
 215         for (i = 0; i < nb_rx; i++) {
 216                 ev[i].flow_id = mbufs[i]->hash.rss;
 217                 ev[i].op = RTE_EVENT_OP_NEW;
 218                 ev[i].sched_type = cdata.queue_type;
 219                 ev[i].queue_id = qid;
 220                 ev[i].event_type = RTE_EVENT_TYPE_ETHDEV;
 221                 ev[i].sub_event_type = 0;
 222                 ev[i].priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
 223                 ev[i].mbuf = mbufs[i];
 224                 RTE_SET_USED(prio_idx);
 225         }
 226
 227         const int nb_tx = rte_event_enqueue_burst(dev_id, port_id, ev, nb_rx);
 228         if (nb_tx != nb_rx) {
 229                 for (i = nb_tx; i < nb_rx; i++)
 230                         rte_pktmbuf_free(mbufs[i]);
 231         }
 232
 233         return 0;
 234 }
 235
 236 static inline void
 237 schedule_devices(uint8_t dev_id, unsigned int lcore_id)
 238 {
 239         if (fdata->rx_core[lcore_id] && (fdata->rx_single ||
 240             rte_atomic32_cmpset(&(fdata->rx_lock), 0, 1))) {
 241                 producer();
 242                 rte_atomic32_clear((rte_atomic32_t *)&(fdata->rx_lock));
 243         }
 244
 245         if (fdata->sched_core[lcore_id] && (fdata->sched_single ||
 246             rte_atomic32_cmpset(&(fdata->sched_lock), 0, 1))) {
 247                 rte_event_schedule(dev_id);
 248                 if (cdata.dump_dev_signal) {
 249                         rte_event_dev_dump(0, stdout);
 250                         cdata.dump_dev_signal = 0;
 251                 }
 252                 rte_atomic32_clear((rte_atomic32_t *)&(fdata->sched_lock));
 253         }
 254
 255         if (fdata->tx_core[lcore_id] && (fdata->tx_single ||
 256             rte_atomic32_cmpset(&(fdata->tx_lock), 0, 1))) {
 257                 consumer();
 258                 rte_atomic32_clear((rte_atomic32_t *)&(fdata->tx_lock));
 259         }
 260 }
 261
 262 static inline void
 263 work(struct rte_mbuf *m)
 264 {
 265         struct ether_hdr *eth;
 266         struct ether_addr addr;
 267
 268         /* change mac addresses on packet (to use mbuf data) */
 269         /*
 270          * FIXME Swap mac address properly and also handle the
 271          * case for both odd and even number of stages that the
 272          * addresses end up the same at the end of the pipeline
 273          */
 274         eth = rte_pktmbuf_mtod(m, struct ether_hdr *);
 275         ether_addr_copy(&eth->d_addr, &addr);
 276         ether_addr_copy(&addr, &eth->d_addr);
 277
 278         /* do a number of cycles of work per packet */
 279         volatile uint64_t start_tsc = rte_rdtsc();
 280         while (rte_rdtsc() < start_tsc + cdata.worker_cycles)
 281                 rte_pause();
 282 }
 283
 284 static int
 285 worker(void *arg)
 286 {
 287         struct rte_event events[BATCH_SIZE];
 288
 289         struct worker_data *data = (struct worker_data *)arg;
 290         uint8_t dev_id = data->dev_id;
 291         uint8_t port_id = data->port_id;
 292         size_t sent = 0, received = 0;
 293         unsigned int lcore_id = rte_lcore_id();
 294
 295         while (!fdata->done) {
 296                 uint16_t i;
 297
 298                 schedule_devices(dev_id, lcore_id);
 299
 300                 if (!fdata->worker_core[lcore_id]) {
 301                         rte_pause();
 302                         continue;
 303                 }
 304
 305                 const uint16_t nb_rx = rte_event_dequeue_burst(dev_id, port_id,
 306                                 events, RTE_DIM(events), 0);
 307
 308                 if (nb_rx == 0) {
 309                         rte_pause();
 310                         continue;
 311                 }
 312                 received += nb_rx;
 313
 314                 for (i = 0; i < nb_rx; i++) {
 315
 316                         /* The first worker stage does classification */
 317                         if (events[i].queue_id == cdata.qid[0])
 318                                 events[i].flow_id = events[i].mbuf->hash.rss
 319                                                         % cdata.num_fids;
 320
 321                         events[i].queue_id = cdata.next_qid[events[i].queue_id];
 322                         events[i].op = RTE_EVENT_OP_FORWARD;
 323                         events[i].sched_type = cdata.queue_type;
 324
 325                         work(events[i].mbuf);
 326                 }
 327                 uint16_t nb_tx = rte_event_enqueue_burst(dev_id, port_id,
 328                                 events, nb_rx);
 329                 while (nb_tx < nb_rx && !fdata->done)
 330                         nb_tx += rte_event_enqueue_burst(dev_id, port_id,
 331                                                         events + nb_tx,
 332                                                         nb_rx - nb_tx);
 333                 sent += nb_tx;
 334         }
 335
 336         if (!cdata.quiet)
 337                 printf("  worker %u thread done. RX=%zu TX=%zu\n",
 338                                 rte_lcore_id(), received, sent);
 339
 340         return 0;
 341 }
 342
 343 /*
 344  * Parse the coremask given as argument (hexadecimal string) and fill
 345  * the global configuration (core role and core count) with the parsed
 346  * value.
 347  */
 348 static int xdigit2val(unsigned char c)
 349 {
 350         int val;
 351
 352         if (isdigit(c))
 353                 val = c - '0';
 354         else if (isupper(c))
 355                 val = c - 'A' + 10;
 356         else
 357                 val = c - 'a' + 10;
 358         return val;
 359 }
 360
 361 static uint64_t
 362 parse_coremask(const char *coremask)
 363 {
 364         int i, j, idx = 0;
 365         unsigned int count = 0;
 366         char c;
 367         int val;
 368         uint64_t mask = 0;
 369         const int32_t BITS_HEX = 4;
 370
 371         if (coremask == NULL)
 372                 return -1;
 373         /* Remove all blank characters ahead and after .
 374          * Remove 0x/0X if exists.
 375          */
 376         while (isblank(*coremask))
 377                 coremask++;
 378         if (coremask[0] == '0' && ((coremask[1] == 'x')
 379                 || (coremask[1] == 'X')))
 380                 coremask += 2;
 381         i = strlen(coremask);
 382         while ((i > 0) && isblank(coremask[i - 1]))
 383                 i--;
 384         if (i == 0)
 385                 return -1;
 386
 387         for (i = i - 1; i >= 0 && idx < MAX_NUM_CORE; i--) {
 388                 c = coremask[i];
 389                 if (isxdigit(c) == 0) {
 390                         /* invalid characters */
 391                         return -1;
 392                 }
 393                 val = xdigit2val(c);
 394                 for (j = 0; j < BITS_HEX && idx < MAX_NUM_CORE; j++, idx++) {
 395                         if ((1 << j) & val) {
 396                                 mask |= (1UL << idx);
 397                                 count++;
 398                         }
 399                 }
 400         }
 401         for (; i >= 0; i--)
 402                 if (coremask[i] != '0')
 403                         return -1;
 404         if (count == 0)
 405                 return -1;
 406         return mask;
 407 }
 408
 409 static struct option long_options[] = {
 410         {"workers", required_argument, 0, 'w'},
 411         {"packets", required_argument, 0, 'n'},
 412         {"atomic-flows", required_argument, 0, 'f'},
 413         {"num_stages", required_argument, 0, 's'},
 414         {"rx-mask", required_argument, 0, 'r'},
 415         {"tx-mask", required_argument, 0, 't'},
 416         {"sched-mask", required_argument, 0, 'e'},
 417         {"cq-depth", required_argument, 0, 'c'},
 418         {"work-cycles", required_argument, 0, 'W'},
 419         {"queue-priority", no_argument, 0, 'P'},
 420         {"parallel", no_argument, 0, 'p'},
 421         {"ordered", no_argument, 0, 'o'},
 422         {"quiet", no_argument, 0, 'q'},
 423         {"dump", no_argument, 0, 'D'},
 424         {0, 0, 0, 0}
 425 };
 426
 427 static void
 428 usage(void)
 429 {
 430         const char *usage_str =
 431                 "  Usage: eventdev_demo [options]\n"
 432                 "  Options:\n"
 433                 "  -n, --packets=N              Send N packets (default ~32M), 0 implies no limit\n"
 434                 "  -f, --atomic-flows=N         Use N random flows from 1 to N (default 16)\n"
 435                 "  -s, --num_stages=N           Use N atomic stages (default 1)\n"
 436                 "  -r, --rx-mask=core mask      Run NIC rx on CPUs in core mask\n"
 437                 "  -w, --worker-mask=core mask  Run worker on CPUs in core mask\n"
 438                 "  -t, --tx-mask=core mask      Run NIC tx on CPUs in core mask\n"
 439                 "  -e  --sched-mask=core mask   Run scheduler on CPUs in core mask\n"
 440                 "  -c  --cq-depth=N             Worker CQ depth (default 16)\n"
 441                 "  -W  --work-cycles=N          Worker cycles (default 0)\n"
 442                 "  -P  --queue-priority         Enable scheduler queue prioritization\n"
 443                 "  -o, --ordered                Use ordered scheduling\n"
 444                 "  -p, --parallel               Use parallel scheduling\n"
 445                 "  -q, --quiet                  Minimize printed output\n"
 446                 "  -D, --dump                   Print detailed statistics before exit"
 447                 "\n";
 448         fprintf(stderr, "%s", usage_str);
 449         exit(1);
 450 }
 451
 452 static void
 453 parse_app_args(int argc, char **argv)
 454 {
 455         /* Parse cli options*/
 456         int option_index;
 457         int c;
 458         opterr = 0;
 459         uint64_t rx_lcore_mask = 0;
 460         uint64_t tx_lcore_mask = 0;
 461         uint64_t sched_lcore_mask = 0;
 462         uint64_t worker_lcore_mask = 0;
 463         int i;
 464
 465         for (;;) {
 466                 c = getopt_long(argc, argv, "r:t:e:c:w:n:f:s:poPqDW:",
 467                                 long_options, &option_index);
 468                 if (c == -1)
 469                         break;
 470
 471                 int popcnt = 0;
 472                 switch (c) {
 473                 case 'n':
 474                         cdata.num_packets = (unsigned long)atol(optarg);
 475                         break;
 476                 case 'f':
 477                         cdata.num_fids = (unsigned int)atoi(optarg);
 478                         break;
 479                 case 's':
 480                         cdata.num_stages = (unsigned int)atoi(optarg);
 481                         break;
 482                 case 'c':
 483                         cdata.worker_cq_depth = (unsigned int)atoi(optarg);
 484                         break;
 485                 case 'W':
 486                         cdata.worker_cycles = (unsigned int)atoi(optarg);
 487                         break;
 488                 case 'P':
 489                         cdata.enable_queue_priorities = 1;
 490                         break;
 491                 case 'o':
 492                         cdata.queue_type = RTE_EVENT_QUEUE_CFG_ORDERED_ONLY;
 493                         break;
 494                 case 'p':
 495                         cdata.queue_type = RTE_EVENT_QUEUE_CFG_PARALLEL_ONLY;
 496                         break;
 497                 case 'q':
 498                         cdata.quiet = 1;
 499                         break;
 500                 case 'D':
 501                         cdata.dump_dev = 1;
 502                         break;
 503                 case 'w':
 504                         worker_lcore_mask = parse_coremask(optarg);
 505                         break;
 506                 case 'r':
 507                         rx_lcore_mask = parse_coremask(optarg);
 508                         popcnt = __builtin_popcountll(rx_lcore_mask);
 509                         fdata->rx_single = (popcnt == 1);
 510                         break;
 511                 case 't':
 512                         tx_lcore_mask = parse_coremask(optarg);
 513                         popcnt = __builtin_popcountll(tx_lcore_mask);
 514                         fdata->tx_single = (popcnt == 1);
 515                         break;
 516                 case 'e':
 517                         sched_lcore_mask = parse_coremask(optarg);
 518                         popcnt = __builtin_popcountll(sched_lcore_mask);
 519                         fdata->sched_single = (popcnt == 1);
 520                         break;
 521                 default:
 522                         usage();
 523                 }
 524         }
 525
 526         if (worker_lcore_mask == 0 || rx_lcore_mask == 0 ||
 527             sched_lcore_mask == 0 || tx_lcore_mask == 0) {
 528                 printf("Core part of pipeline was not assigned any cores. "
 529                         "This will stall the pipeline, please check core masks "
 530                         "(use -h for details on setting core masks):\n"
 531                         "\trx: %"PRIu64"\n\ttx: %"PRIu64"\n\tsched: %"PRIu64
 532                         "\n\tworkers: %"PRIu64"\n",
 533                         rx_lcore_mask, tx_lcore_mask, sched_lcore_mask,
 534                         worker_lcore_mask);
 535                 rte_exit(-1, "Fix core masks\n");
 536         }
 537         if (cdata.num_stages == 0 || cdata.num_stages > MAX_NUM_STAGES)
 538                 usage();
 539
 540         for (i = 0; i < MAX_NUM_CORE; i++) {
 541                 fdata->rx_core[i] = !!(rx_lcore_mask & (1UL << i));
 542                 fdata->tx_core[i] = !!(tx_lcore_mask & (1UL << i));
 543                 fdata->sched_core[i] = !!(sched_lcore_mask & (1UL << i));
 544                 fdata->worker_core[i] = !!(worker_lcore_mask & (1UL << i));
 545
 546                 if (fdata->worker_core[i])
 547                         cdata.num_workers++;
 548                 if (core_in_use(i))
 549                         cdata.active_cores++;
 550         }
 551 }
 552
 553 /*
 554  * Initializes a given port using global settings and with the RX buffers
 555  * coming from the mbuf_pool passed as a parameter.
 556  */
 557 static inline int
 558 port_init(uint8_t port, struct rte_mempool *mbuf_pool)
 559 {
 560         static const struct rte_eth_conf port_conf_default = {
 561                 .rxmode = {
 562                         .mq_mode = ETH_MQ_RX_RSS,
 563                         .max_rx_pkt_len = ETHER_MAX_LEN
 564                 },
 565                 .rx_adv_conf = {
 566                         .rss_conf = {
 567                                 .rss_hf = ETH_RSS_IP |
 568                                           ETH_RSS_TCP |
 569                                           ETH_RSS_UDP,
 570                         }
 571                 }
 572         };
 573         const uint16_t rx_rings = 1, tx_rings = 1;
 574         const uint16_t rx_ring_size = 512, tx_ring_size = 512;
 575         struct rte_eth_conf port_conf = port_conf_default;
 576         int retval;
 577         uint16_t q;
 578
 579         if (port >= rte_eth_dev_count())
 580                 return -1;
 581
 582         /* Configure the Ethernet device. */
 583         retval = rte_eth_dev_configure(port, rx_rings, tx_rings, &port_conf);
 584         if (retval != 0)
 585                 return retval;
 586
 587         /* Allocate and set up 1 RX queue per Ethernet port. */
 588         for (q = 0; q < rx_rings; q++) {
 589                 retval = rte_eth_rx_queue_setup(port, q, rx_ring_size,
 590                                 rte_eth_dev_socket_id(port), NULL, mbuf_pool);
 591                 if (retval < 0)
 592                         return retval;
 593         }
 594
 595         /* Allocate and set up 1 TX queue per Ethernet port. */
 596         for (q = 0; q < tx_rings; q++) {
 597                 retval = rte_eth_tx_queue_setup(port, q, tx_ring_size,
 598                                 rte_eth_dev_socket_id(port), NULL);
 599                 if (retval < 0)
 600                         return retval;
 601         }
 602
 603         /* Start the Ethernet port. */
 604         retval = rte_eth_dev_start(port);
 605         if (retval < 0)
 606                 return retval;
 607
 608         /* Display the port MAC address. */
 609         struct ether_addr addr;
 610         rte_eth_macaddr_get(port, &addr);
 611         printf("Port %u MAC: %02" PRIx8 " %02" PRIx8 " %02" PRIx8
 612                            " %02" PRIx8 " %02" PRIx8 " %02" PRIx8 "\n",
 613                         (unsigned int)port,
 614                         addr.addr_bytes[0], addr.addr_bytes[1],
 615                         addr.addr_bytes[2], addr.addr_bytes[3],
 616                         addr.addr_bytes[4], addr.addr_bytes[5]);
 617
 618         /* Enable RX in promiscuous mode for the Ethernet device. */
 619         rte_eth_promiscuous_enable(port);
 620
 621         return 0;
 622 }
 623
 624 static int
 625 init_ports(unsigned int num_ports)
 626 {
 627         uint8_t portid;
 628         unsigned int i;
 629
 630         struct rte_mempool *mp = rte_pktmbuf_pool_create("packet_pool",
 631                         /* mbufs */ 16384 * num_ports,
 632                         /* cache_size */ 512,
 633                         /* priv_size*/ 0,
 634                         /* data_room_size */ RTE_MBUF_DEFAULT_BUF_SIZE,
 635                         rte_socket_id());
 636
 637         for (portid = 0; portid < num_ports; portid++)
 638                 if (port_init(portid, mp) != 0)
 639                         rte_exit(EXIT_FAILURE, "Cannot init port %"PRIu8 "\n",
 640                                         portid);
 641
 642         for (i = 0; i < num_ports; i++) {
 643                 void *userdata = (void *)(uintptr_t) i;
 644                 fdata->tx_buf[i] =
 645                         rte_malloc(NULL, RTE_ETH_TX_BUFFER_SIZE(32), 0);
 646                 if (fdata->tx_buf[i] == NULL)
 647                         rte_panic("Out of memory\n");
 648                 rte_eth_tx_buffer_init(fdata->tx_buf[i], 32);
 649                 rte_eth_tx_buffer_set_err_callback(fdata->tx_buf[i],
 650                                                    eth_tx_buffer_retry,
 651                                                    userdata);
 652         }
 653
 654         return 0;
 655 }
 656
 657 struct port_link {
 658         uint8_t queue_id;
 659         uint8_t priority;
 660 };
 661
 662 static int
 663 setup_eventdev(struct prod_data *prod_data,
 664                 struct cons_data *cons_data,
 665                 struct worker_data *worker_data)
 666 {
 667         const uint8_t dev_id = 0;
 668         /* +1 stages is for a SINGLE_LINK TX stage */
 669         const uint8_t nb_queues = cdata.num_stages + 1;
 670         /* + 2 is one port for producer and one for consumer */
 671         const uint8_t nb_ports = cdata.num_workers + 2;
 672         struct rte_event_dev_config config = {
 673                         .nb_event_queues = nb_queues,
 674                         .nb_event_ports = nb_ports,
 675                         .nb_events_limit  = 4096,
 676                         .nb_event_queue_flows = 1024,
 677                         .nb_event_port_dequeue_depth = 128,
 678                         .nb_event_port_enqueue_depth = 128,
 679         };
 680         struct rte_event_port_conf wkr_p_conf = {
 681                         .dequeue_depth = cdata.worker_cq_depth,
 682                         .enqueue_depth = 64,
 683                         .new_event_threshold = 4096,
 684         };
 685         struct rte_event_queue_conf wkr_q_conf = {
 686                         .event_queue_cfg = cdata.queue_type,
 687                         .priority = RTE_EVENT_DEV_PRIORITY_NORMAL,
 688                         .nb_atomic_flows = 1024,
 689                         .nb_atomic_order_sequences = 1024,
 690         };
 691         struct rte_event_port_conf tx_p_conf = {
 692                         .dequeue_depth = 128,
 693                         .enqueue_depth = 128,
 694                         .new_event_threshold = 4096,
 695         };
 696         const struct rte_event_queue_conf tx_q_conf = {
 697                         .priority = RTE_EVENT_DEV_PRIORITY_HIGHEST,
 698                         .event_queue_cfg =
 699                                         RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY |
 700                                         RTE_EVENT_QUEUE_CFG_SINGLE_LINK,
 701                         .nb_atomic_flows = 1024,
 702                         .nb_atomic_order_sequences = 1024,
 703         };
 704
 705         struct port_link worker_queues[MAX_NUM_STAGES];
 706         struct port_link tx_queue;
 707         unsigned int i;
 708
 709         int ret, ndev = rte_event_dev_count();
 710         if (ndev < 1) {
 711                 printf("%d: No Eventdev Devices Found\n", __LINE__);
 712                 return -1;
 713         }
 714
 715         struct rte_event_dev_info dev_info;
 716         ret = rte_event_dev_info_get(dev_id, &dev_info);
 717         printf("\tEventdev %d: %s\n", dev_id, dev_info.driver_name);
 718
 719         if (dev_info.max_event_port_dequeue_depth <
 720                         config.nb_event_port_dequeue_depth)
 721                 config.nb_event_port_dequeue_depth =
 722                                 dev_info.max_event_port_dequeue_depth;
 723         if (dev_info.max_event_port_enqueue_depth <
 724                         config.nb_event_port_enqueue_depth)
 725                 config.nb_event_port_enqueue_depth =
 726                                 dev_info.max_event_port_enqueue_depth;
 727
 728         ret = rte_event_dev_configure(dev_id, &config);
 729         if (ret < 0) {
 730                 printf("%d: Error configuring device\n", __LINE__);
 731                 return -1;
 732         }
 733
 734         /* Q creation - one load balanced per pipeline stage*/
 735         printf("  Stages:\n");
 736         for (i = 0; i < cdata.num_stages; i++) {
 737                 if (rte_event_queue_setup(dev_id, i, &wkr_q_conf) < 0) {
 738                         printf("%d: error creating qid %d\n", __LINE__, i);
 739                         return -1;
 740                 }
 741                 cdata.qid[i] = i;
 742                 cdata.next_qid[i] = i+1;
 743                 worker_queues[i].queue_id = i;
 744                 if (cdata.enable_queue_priorities) {
 745                         /* calculate priority stepping for each stage, leaving
 746                          * headroom of 1 for the SINGLE_LINK TX below
 747                          */
 748                         const uint32_t prio_delta =
 749                                 (RTE_EVENT_DEV_PRIORITY_LOWEST-1) /  nb_queues;
 750
 751                         /* higher priority for queues closer to tx */
 752                         wkr_q_conf.priority =
 753                                 RTE_EVENT_DEV_PRIORITY_LOWEST - prio_delta * i;
 754                 }
 755
 756                 const char *type_str = "Atomic";
 757                 switch (wkr_q_conf.event_queue_cfg) {
 758                 case RTE_EVENT_QUEUE_CFG_ORDERED_ONLY:
 759                         type_str = "Ordered";
 760                         break;
 761                 case RTE_EVENT_QUEUE_CFG_PARALLEL_ONLY:
 762                         type_str = "Parallel";
 763                         break;
 764                 }
 765                 printf("\tStage %d, Type %s\tPriority = %d\n", i, type_str,
 766                                 wkr_q_conf.priority);
 767         }
 768         printf("\n");
 769
 770         /* final queue for sending to TX core */
 771         if (rte_event_queue_setup(dev_id, i, &tx_q_conf) < 0) {
 772                 printf("%d: error creating qid %d\n", __LINE__, i);
 773                 return -1;
 774         }
 775         tx_queue.queue_id = i;
 776         tx_queue.priority = RTE_EVENT_DEV_PRIORITY_HIGHEST;
 777
 778         if (wkr_p_conf.dequeue_depth > config.nb_event_port_dequeue_depth)
 779                 wkr_p_conf.dequeue_depth = config.nb_event_port_dequeue_depth;
 780         if (wkr_p_conf.enqueue_depth > config.nb_event_port_enqueue_depth)
 781                 wkr_p_conf.enqueue_depth = config.nb_event_port_enqueue_depth;
 782
 783         /* set up one port per worker, linking to all stage queues */
 784         for (i = 0; i < cdata.num_workers; i++) {
 785                 struct worker_data *w = &worker_data[i];
 786                 w->dev_id = dev_id;
 787                 if (rte_event_port_setup(dev_id, i, &wkr_p_conf) < 0) {
 788                         printf("Error setting up port %d\n", i);
 789                         return -1;
 790                 }
 791
 792                 uint32_t s;
 793                 for (s = 0; s < cdata.num_stages; s++) {
 794                         if (rte_event_port_link(dev_id, i,
 795                                                 &worker_queues[s].queue_id,
 796                                                 &worker_queues[s].priority,
 797                                                 1) != 1) {
 798                                 printf("%d: error creating link for port %d\n",
 799                                                 __LINE__, i);
 800                                 return -1;
 801                         }
 802                 }
 803                 w->port_id = i;
 804         }
 805
 806         if (tx_p_conf.dequeue_depth > config.nb_event_port_dequeue_depth)
 807                 tx_p_conf.dequeue_depth = config.nb_event_port_dequeue_depth;
 808         if (tx_p_conf.enqueue_depth > config.nb_event_port_enqueue_depth)
 809                 tx_p_conf.enqueue_depth = config.nb_event_port_enqueue_depth;
 810
 811         /* port for consumer, linked to TX queue */
 812         if (rte_event_port_setup(dev_id, i, &tx_p_conf) < 0) {
 813                 printf("Error setting up port %d\n", i);
 814                 return -1;
 815         }
 816         if (rte_event_port_link(dev_id, i, &tx_queue.queue_id,
 817                                 &tx_queue.priority, 1) != 1) {
 818                 printf("%d: error creating link for port %d\n",
 819                                 __LINE__, i);
 820                 return -1;
 821         }
 822         /* port for producer, no links */
 823         struct rte_event_port_conf rx_p_conf = {
 824                         .dequeue_depth = 8,
 825                         .enqueue_depth = 8,
 826                         .new_event_threshold = 1200,
 827         };
 828
 829         if (rx_p_conf.dequeue_depth > config.nb_event_port_dequeue_depth)
 830                 rx_p_conf.dequeue_depth = config.nb_event_port_dequeue_depth;
 831         if (rx_p_conf.enqueue_depth > config.nb_event_port_enqueue_depth)
 832                 rx_p_conf.enqueue_depth = config.nb_event_port_enqueue_depth;
 833
 834         if (rte_event_port_setup(dev_id, i + 1, &rx_p_conf) < 0) {
 835                 printf("Error setting up port %d\n", i);
 836                 return -1;
 837         }
 838
 839         *prod_data = (struct prod_data){.dev_id = dev_id,
 840                                         .port_id = i + 1,
 841                                         .qid = cdata.qid[0] };
 842         *cons_data = (struct cons_data){.dev_id = dev_id,
 843                                         .port_id = i };
 844
 845         if (rte_event_dev_start(dev_id) < 0) {
 846                 printf("Error starting eventdev\n");
 847                 return -1;
 848         }
 849
 850         return dev_id;
 851 }
 852
 853 static void
 854 signal_handler(int signum)
 855 {
 856         if (fdata->done)
 857                 rte_exit(1, "Exiting on signal %d\n", signum);
 858         if (signum == SIGINT || signum == SIGTERM) {
 859                 printf("\n\nSignal %d received, preparing to exit...\n",
 860                                 signum);
 861                 fdata->done = 1;
 862         }
 863         if (signum == SIGTSTP)
 864                 rte_event_dev_dump(0, stdout);
 865 }
 866
 867 static inline uint64_t
 868 port_stat(int dev_id, int32_t p)
 869 {
 870         char statname[64];
 871         snprintf(statname, sizeof(statname), "port_%u_rx", p);
 872         return rte_event_dev_xstats_by_name_get(dev_id, statname, NULL);
 873 }
 874
 875 int
 876 main(int argc, char **argv)
 877 {
 878         struct worker_data *worker_data;
 879         unsigned int num_ports;
 880         int lcore_id;
 881         int err;
 882
 883         signal(SIGINT, signal_handler);
 884         signal(SIGTERM, signal_handler);
 885         signal(SIGTSTP, signal_handler);
 886
 887         err = rte_eal_init(argc, argv);
 888         if (err < 0)
 889                 rte_panic("Invalid EAL arguments\n");
 890
 891         argc -= err;
 892         argv += err;
 893
 894         fdata = rte_malloc(NULL, sizeof(struct fastpath_data), 0);
 895         if (fdata == NULL)
 896                 rte_panic("Out of memory\n");
 897
 898         /* Parse cli options*/
 899         parse_app_args(argc, argv);
 900
 901         num_ports = rte_eth_dev_count();
 902         if (num_ports == 0)
 903                 rte_panic("No ethernet ports found\n");
 904
 905         const unsigned int cores_needed = cdata.active_cores;
 906
 907         if (!cdata.quiet) {
 908                 printf("  Config:\n");
 909                 printf("\tports: %u\n", num_ports);
 910                 printf("\tworkers: %u\n", cdata.num_workers);
 911                 printf("\tpackets: %lu\n", cdata.num_packets);
 912                 printf("\tQueue-prio: %u\n", cdata.enable_queue_priorities);
 913                 if (cdata.queue_type == RTE_EVENT_QUEUE_CFG_ORDERED_ONLY)
 914                         printf("\tqid0 type: ordered\n");
 915                 if (cdata.queue_type == RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY)
 916                         printf("\tqid0 type: atomic\n");
 917                 printf("\tCores available: %u\n", rte_lcore_count());
 918                 printf("\tCores used: %u\n", cores_needed);
 919         }
 920
 921         if (rte_lcore_count() < cores_needed)
 922                 rte_panic("Too few cores (%d < %d)\n", rte_lcore_count(),
 923                                 cores_needed);
 924
 925         const unsigned int ndevs = rte_event_dev_count();
 926         if (ndevs == 0)
 927                 rte_panic("No dev_id devs found. Pasl in a --vdev eventdev.\n");
 928         if (ndevs > 1)
 929                 fprintf(stderr, "Warning: More than one eventdev, using idx 0");
 930
 931         worker_data = rte_calloc(0, cdata.num_workers,
 932                         sizeof(worker_data[0]), 0);
 933         if (worker_data == NULL)
 934                 rte_panic("rte_calloc failed\n");
 935
 936         int dev_id = setup_eventdev(&prod_data, &cons_data, worker_data);
 937         if (dev_id < 0)
 938                 rte_exit(EXIT_FAILURE, "Error setting up eventdev\n");
 939
 940         prod_data.num_nic_ports = num_ports;
 941         init_ports(num_ports);
 942
 943         int worker_idx = 0;
 944         RTE_LCORE_FOREACH_SLAVE(lcore_id) {
 945                 if (lcore_id >= MAX_NUM_CORE)
 946                         break;
 947
 948                 if (!fdata->rx_core[lcore_id] &&
 949                         !fdata->worker_core[lcore_id] &&
 950                         !fdata->tx_core[lcore_id] &&
 951                         !fdata->sched_core[lcore_id])
 952                         continue;
 953
 954                 if (fdata->rx_core[lcore_id])
 955                         printf(
 956                                 "[%s()] lcore %d executing NIC Rx, and using eventdev port %u\n",
 957                                 __func__, lcore_id, prod_data.port_id);
 958
 959                 if (fdata->tx_core[lcore_id])
 960                         printf(
 961                                 "[%s()] lcore %d executing NIC Tx, and using eventdev port %u\n",
 962                                 __func__, lcore_id, cons_data.port_id);
 963
 964                 if (fdata->sched_core[lcore_id])
 965                         printf("[%s()] lcore %d executing scheduler\n",
 966                                         __func__, lcore_id);
 967
 968                 if (fdata->worker_core[lcore_id])
 969                         printf(
 970                                 "[%s()] lcore %d executing worker, using eventdev port %u\n",
 971                                 __func__, lcore_id,
 972                                 worker_data[worker_idx].port_id);
 973
 974                 err = rte_eal_remote_launch(worker, &worker_data[worker_idx],
 975                                             lcore_id);
 976                 if (err) {
 977                         rte_panic("Failed to launch worker on core %d\n",
 978                                         lcore_id);
 979                         continue;
 980                 }
 981                 if (fdata->worker_core[lcore_id])
 982                         worker_idx++;
 983         }
 984
 985         lcore_id = rte_lcore_id();
 986
 987         if (core_in_use(lcore_id))
 988                 worker(&worker_data[worker_idx++]);
 989
 990         rte_eal_mp_wait_lcore();
 991
 992         if (cdata.dump_dev)
 993                 rte_event_dev_dump(dev_id, stdout);
 994
 995         if (!cdata.quiet && (port_stat(dev_id, worker_data[0].port_id) !=
 996                         (uint64_t)-ENOTSUP)) {
 997                 printf("\nPort Workload distribution:\n");
 998                 uint32_t i;
 999                 uint64_t tot_pkts = 0;
1000                 uint64_t pkts_per_wkr[RTE_MAX_LCORE] = {0};
1001                 for (i = 0; i < cdata.num_workers; i++) {
1002                         pkts_per_wkr[i] =
1003                                 port_stat(dev_id, worker_data[i].port_id);
1004                         tot_pkts += pkts_per_wkr[i];
1005                 }
1006                 for (i = 0; i < cdata.num_workers; i++) {
1007                         float pc = pkts_per_wkr[i]  * 100 /
1008                                 ((float)tot_pkts);
1009                         printf("worker %i :\t%.1f %% (%"PRIu64" pkts)\n",
1010                                         i, pc, pkts_per_wkr[i]);
1011                 }
1012
1013         }
1014
1015         return 0;
1016 }