1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
8 #include <rte_common.h>
9 #include <rte_malloc.h>
10 #include <rte_byteorder.h>
11 #include <rte_table_stub.h>
12 #include <rte_table_hash.h>
13 #include <rte_pipeline.h>
15 #include "pipeline_passthrough_be.h"
16 #include "pipeline_actions_common.h"
18 #include "hash_func.h"
20 #define SWAP_DIM (PIPELINE_PASSTHROUGH_SWAP_N_FIELDS_MAX * \
21 (PIPELINE_PASSTHROUGH_SWAP_FIELD_SIZE_MAX / sizeof(uint64_t)))
23 struct pipeline_passthrough {
25 struct pipeline_passthrough_params params;
26 rte_table_hash_op_hash f_hash;
27 uint32_t swap_field0_offset[SWAP_DIM];
28 uint32_t swap_field1_offset[SWAP_DIM];
29 uint64_t swap_field_mask[SWAP_DIM];
30 uint32_t swap_n_fields;
31 } __rte_cache_aligned;
33 static pipeline_msg_req_handler handlers[] = {
34 [PIPELINE_MSG_REQ_PING] =
35 pipeline_msg_req_ping_handler,
36 [PIPELINE_MSG_REQ_STATS_PORT_IN] =
37 pipeline_msg_req_stats_port_in_handler,
38 [PIPELINE_MSG_REQ_STATS_PORT_OUT] =
39 pipeline_msg_req_stats_port_out_handler,
40 [PIPELINE_MSG_REQ_STATS_TABLE] =
41 pipeline_msg_req_stats_table_handler,
42 [PIPELINE_MSG_REQ_PORT_IN_ENABLE] =
43 pipeline_msg_req_port_in_enable_handler,
44 [PIPELINE_MSG_REQ_PORT_IN_DISABLE] =
45 pipeline_msg_req_port_in_disable_handler,
46 [PIPELINE_MSG_REQ_CUSTOM] =
47 pipeline_msg_req_invalid_handler,
50 static __rte_always_inline void
55 uint32_t hash_enabled,
57 uint32_t port_out_pow2)
59 struct pipeline_passthrough *p = arg;
61 uint64_t *dma_dst = RTE_MBUF_METADATA_UINT64_PTR(pkt,
62 p->params.dma_dst_offset);
63 uint64_t *dma_src = RTE_MBUF_METADATA_UINT64_PTR(pkt,
64 p->params.dma_src_offset);
65 uint64_t *dma_mask = (uint64_t *) p->params.dma_src_mask;
66 uint32_t *dma_hash = RTE_MBUF_METADATA_UINT32_PTR(pkt,
67 p->params.dma_hash_offset);
70 /* Read (dma_src), compute (dma_dst), write (dma_dst) */
71 for (i = 0; i < (dma_size / 8); i++)
72 dma_dst[i] = dma_src[i] & dma_mask[i];
74 /* Read (dma_dst), compute (hash), write (hash) */
76 uint32_t hash = p->f_hash(dma_src, dma_mask, dma_size, 0);
84 = hash & (p->p.n_ports_out - 1);
87 = hash % p->p.n_ports_out;
89 rte_pipeline_port_out_packet_insert(p->p.p,
95 static __rte_always_inline void
97 struct rte_mbuf **pkts,
100 uint32_t hash_enabled,
102 uint32_t port_out_pow2)
104 struct pipeline_passthrough *p = arg;
106 uint64_t *dma_dst0 = RTE_MBUF_METADATA_UINT64_PTR(pkts[0],
107 p->params.dma_dst_offset);
108 uint64_t *dma_dst1 = RTE_MBUF_METADATA_UINT64_PTR(pkts[1],
109 p->params.dma_dst_offset);
110 uint64_t *dma_dst2 = RTE_MBUF_METADATA_UINT64_PTR(pkts[2],
111 p->params.dma_dst_offset);
112 uint64_t *dma_dst3 = RTE_MBUF_METADATA_UINT64_PTR(pkts[3],
113 p->params.dma_dst_offset);
115 uint64_t *dma_src0 = RTE_MBUF_METADATA_UINT64_PTR(pkts[0],
116 p->params.dma_src_offset);
117 uint64_t *dma_src1 = RTE_MBUF_METADATA_UINT64_PTR(pkts[1],
118 p->params.dma_src_offset);
119 uint64_t *dma_src2 = RTE_MBUF_METADATA_UINT64_PTR(pkts[2],
120 p->params.dma_src_offset);
121 uint64_t *dma_src3 = RTE_MBUF_METADATA_UINT64_PTR(pkts[3],
122 p->params.dma_src_offset);
124 uint64_t *dma_mask = (uint64_t *) p->params.dma_src_mask;
126 uint32_t *dma_hash0 = RTE_MBUF_METADATA_UINT32_PTR(pkts[0],
127 p->params.dma_hash_offset);
128 uint32_t *dma_hash1 = RTE_MBUF_METADATA_UINT32_PTR(pkts[1],
129 p->params.dma_hash_offset);
130 uint32_t *dma_hash2 = RTE_MBUF_METADATA_UINT32_PTR(pkts[2],
131 p->params.dma_hash_offset);
132 uint32_t *dma_hash3 = RTE_MBUF_METADATA_UINT32_PTR(pkts[3],
133 p->params.dma_hash_offset);
137 /* Read (dma_src), compute (dma_dst), write (dma_dst) */
138 for (i = 0; i < (dma_size / 8); i++) {
139 dma_dst0[i] = dma_src0[i] & dma_mask[i];
140 dma_dst1[i] = dma_src1[i] & dma_mask[i];
141 dma_dst2[i] = dma_src2[i] & dma_mask[i];
142 dma_dst3[i] = dma_src3[i] & dma_mask[i];
145 /* Read (dma_dst), compute (hash), write (hash) */
147 uint32_t hash0 = p->f_hash(dma_src0, dma_mask, dma_size, 0);
148 uint32_t hash1 = p->f_hash(dma_src1, dma_mask, dma_size, 0);
149 uint32_t hash2 = p->f_hash(dma_src2, dma_mask, dma_size, 0);
150 uint32_t hash3 = p->f_hash(dma_src3, dma_mask, dma_size, 0);
158 uint32_t port_out0, port_out1, port_out2, port_out3;
162 = hash0 & (p->p.n_ports_out - 1);
164 = hash1 & (p->p.n_ports_out - 1);
166 = hash2 & (p->p.n_ports_out - 1);
168 = hash3 & (p->p.n_ports_out - 1);
171 = hash0 % p->p.n_ports_out;
173 = hash1 % p->p.n_ports_out;
175 = hash2 % p->p.n_ports_out;
177 = hash3 % p->p.n_ports_out;
179 rte_pipeline_port_out_packet_insert(p->p.p,
181 rte_pipeline_port_out_packet_insert(p->p.p,
183 rte_pipeline_port_out_packet_insert(p->p.p,
185 rte_pipeline_port_out_packet_insert(p->p.p,
191 static __rte_always_inline void
193 struct rte_mbuf *pkt,
196 struct pipeline_passthrough *p = arg;
199 /* Read(field0, field1), compute(field0, field1), write(field0, field1) */
200 for (i = 0; i < p->swap_n_fields; i++) {
201 uint64_t *field0_ptr = RTE_MBUF_METADATA_UINT64_PTR(pkt,
202 p->swap_field0_offset[i]);
203 uint64_t *field1_ptr = RTE_MBUF_METADATA_UINT64_PTR(pkt,
204 p->swap_field1_offset[i]);
205 uint64_t mask = p->swap_field_mask[i];
207 uint64_t field0 = *field0_ptr;
208 uint64_t field1 = *field1_ptr;
210 *field0_ptr = (field0 & (~mask)) + (field1 & mask);
211 *field1_ptr = (field0 & mask) + (field1 & (~mask));
215 static __rte_always_inline void
217 struct rte_mbuf **pkts,
220 struct pipeline_passthrough *p = arg;
223 /* Read(field0, field1), compute(field0, field1), write(field0, field1) */
224 for (i = 0; i < p->swap_n_fields; i++) {
225 uint64_t *pkt0_field0_ptr = RTE_MBUF_METADATA_UINT64_PTR(pkts[0],
226 p->swap_field0_offset[i]);
227 uint64_t *pkt1_field0_ptr = RTE_MBUF_METADATA_UINT64_PTR(pkts[1],
228 p->swap_field0_offset[i]);
229 uint64_t *pkt2_field0_ptr = RTE_MBUF_METADATA_UINT64_PTR(pkts[2],
230 p->swap_field0_offset[i]);
231 uint64_t *pkt3_field0_ptr = RTE_MBUF_METADATA_UINT64_PTR(pkts[3],
232 p->swap_field0_offset[i]);
234 uint64_t *pkt0_field1_ptr = RTE_MBUF_METADATA_UINT64_PTR(pkts[0],
235 p->swap_field1_offset[i]);
236 uint64_t *pkt1_field1_ptr = RTE_MBUF_METADATA_UINT64_PTR(pkts[1],
237 p->swap_field1_offset[i]);
238 uint64_t *pkt2_field1_ptr = RTE_MBUF_METADATA_UINT64_PTR(pkts[2],
239 p->swap_field1_offset[i]);
240 uint64_t *pkt3_field1_ptr = RTE_MBUF_METADATA_UINT64_PTR(pkts[3],
241 p->swap_field1_offset[i]);
243 uint64_t mask = p->swap_field_mask[i];
245 uint64_t pkt0_field0 = *pkt0_field0_ptr;
246 uint64_t pkt1_field0 = *pkt1_field0_ptr;
247 uint64_t pkt2_field0 = *pkt2_field0_ptr;
248 uint64_t pkt3_field0 = *pkt3_field0_ptr;
250 uint64_t pkt0_field1 = *pkt0_field1_ptr;
251 uint64_t pkt1_field1 = *pkt1_field1_ptr;
252 uint64_t pkt2_field1 = *pkt2_field1_ptr;
253 uint64_t pkt3_field1 = *pkt3_field1_ptr;
255 *pkt0_field0_ptr = (pkt0_field0 & (~mask)) + (pkt0_field1 & mask);
256 *pkt1_field0_ptr = (pkt1_field0 & (~mask)) + (pkt1_field1 & mask);
257 *pkt2_field0_ptr = (pkt2_field0 & (~mask)) + (pkt2_field1 & mask);
258 *pkt3_field0_ptr = (pkt3_field0 & (~mask)) + (pkt3_field1 & mask);
260 *pkt0_field1_ptr = (pkt0_field0 & mask) + (pkt0_field1 & (~mask));
261 *pkt1_field1_ptr = (pkt1_field0 & mask) + (pkt1_field1 & (~mask));
262 *pkt2_field1_ptr = (pkt2_field0 & mask) + (pkt2_field1 & (~mask));
263 *pkt3_field1_ptr = (pkt3_field0 & mask) + (pkt3_field1 & (~mask));
267 #define PKT_WORK_DMA(dma_size, hash_enabled, lb_hash, port_pow2) \
269 pkt_work_dma_size##dma_size##_hash##hash_enabled \
270 ##_lb##lb_hash##_pw##port_pow2( \
271 struct rte_mbuf *pkt, \
274 pkt_work_dma(pkt, arg, dma_size, hash_enabled, lb_hash, port_pow2); \
277 #define PKT4_WORK_DMA(dma_size, hash_enabled, lb_hash, port_pow2) \
279 pkt4_work_dma_size##dma_size##_hash##hash_enabled \
280 ##_lb##lb_hash##_pw##port_pow2( \
281 struct rte_mbuf **pkts, \
284 pkt4_work_dma(pkts, arg, dma_size, hash_enabled, lb_hash, port_pow2); \
287 #define port_in_ah_dma(dma_size, hash_enabled, lb_hash, port_pow2) \
288 PKT_WORK_DMA(dma_size, hash_enabled, lb_hash, port_pow2) \
289 PKT4_WORK_DMA(dma_size, hash_enabled, lb_hash, port_pow2) \
290 PIPELINE_PORT_IN_AH(port_in_ah_dma_size##dma_size##_hash \
291 ##hash_enabled##_lb##lb_hash##_pw##port_pow2, \
292 pkt_work_dma_size##dma_size##_hash##hash_enabled \
293 ##_lb##lb_hash##_pw##port_pow2, \
294 pkt4_work_dma_size##dma_size##_hash##hash_enabled \
295 ##_lb##lb_hash##_pw##port_pow2)
298 #define port_in_ah_lb(dma_size, hash_enabled, lb_hash, port_pow2) \
299 PKT_WORK_DMA(dma_size, hash_enabled, lb_hash, port_pow2) \
300 PKT4_WORK_DMA(dma_size, hash_enabled, lb_hash, port_pow2) \
301 PIPELINE_PORT_IN_AH_HIJACK_ALL( \
302 port_in_ah_lb_size##dma_size##_hash##hash_enabled \
303 ##_lb##lb_hash##_pw##port_pow2, \
304 pkt_work_dma_size##dma_size##_hash##hash_enabled \
305 ##_lb##lb_hash##_pw##port_pow2, \
306 pkt4_work_dma_size##dma_size##_hash##hash_enabled \
307 ##_lb##lb_hash##_pw##port_pow2)
309 PIPELINE_PORT_IN_AH(port_in_ah_swap, pkt_work_swap, pkt4_work_swap)
312 /* Port in AH DMA(dma_size, hash_enabled, lb_hash, port_pow2) */
314 port_in_ah_dma(8, 0, 0, 0)
315 port_in_ah_dma(8, 1, 0, 0)
316 port_in_ah_lb(8, 1, 1, 0)
317 port_in_ah_lb(8, 1, 1, 1)
319 port_in_ah_dma(16, 0, 0, 0)
320 port_in_ah_dma(16, 1, 0, 0)
321 port_in_ah_lb(16, 1, 1, 0)
322 port_in_ah_lb(16, 1, 1, 1)
324 port_in_ah_dma(24, 0, 0, 0)
325 port_in_ah_dma(24, 1, 0, 0)
326 port_in_ah_lb(24, 1, 1, 0)
327 port_in_ah_lb(24, 1, 1, 1)
329 port_in_ah_dma(32, 0, 0, 0)
330 port_in_ah_dma(32, 1, 0, 0)
331 port_in_ah_lb(32, 1, 1, 0)
332 port_in_ah_lb(32, 1, 1, 1)
334 port_in_ah_dma(40, 0, 0, 0)
335 port_in_ah_dma(40, 1, 0, 0)
336 port_in_ah_lb(40, 1, 1, 0)
337 port_in_ah_lb(40, 1, 1, 1)
339 port_in_ah_dma(48, 0, 0, 0)
340 port_in_ah_dma(48, 1, 0, 0)
341 port_in_ah_lb(48, 1, 1, 0)
342 port_in_ah_lb(48, 1, 1, 1)
344 port_in_ah_dma(56, 0, 0, 0)
345 port_in_ah_dma(56, 1, 0, 0)
346 port_in_ah_lb(56, 1, 1, 0)
347 port_in_ah_lb(56, 1, 1, 1)
349 port_in_ah_dma(64, 0, 0, 0)
350 port_in_ah_dma(64, 1, 0, 0)
351 port_in_ah_lb(64, 1, 1, 0)
352 port_in_ah_lb(64, 1, 1, 1)
354 static rte_pipeline_port_in_action_handler
355 get_port_in_ah(struct pipeline_passthrough *p)
357 if ((p->params.dma_enabled == 0) &&
358 (p->params.swap_enabled == 0))
361 if (p->params.swap_enabled)
362 return port_in_ah_swap;
364 if (p->params.dma_hash_enabled) {
365 if (p->params.dma_hash_lb_enabled) {
366 if (rte_is_power_of_2(p->p.n_ports_out))
367 switch (p->params.dma_size) {
369 case 8: return port_in_ah_lb_size8_hash1_lb1_pw1;
370 case 16: return port_in_ah_lb_size16_hash1_lb1_pw1;
371 case 24: return port_in_ah_lb_size24_hash1_lb1_pw1;
372 case 32: return port_in_ah_lb_size32_hash1_lb1_pw1;
373 case 40: return port_in_ah_lb_size40_hash1_lb1_pw1;
374 case 48: return port_in_ah_lb_size48_hash1_lb1_pw1;
375 case 56: return port_in_ah_lb_size56_hash1_lb1_pw1;
376 case 64: return port_in_ah_lb_size64_hash1_lb1_pw1;
377 default: return NULL;
380 switch (p->params.dma_size) {
382 case 8: return port_in_ah_lb_size8_hash1_lb1_pw0;
383 case 16: return port_in_ah_lb_size16_hash1_lb1_pw0;
384 case 24: return port_in_ah_lb_size24_hash1_lb1_pw0;
385 case 32: return port_in_ah_lb_size32_hash1_lb1_pw0;
386 case 40: return port_in_ah_lb_size40_hash1_lb1_pw0;
387 case 48: return port_in_ah_lb_size48_hash1_lb1_pw0;
388 case 56: return port_in_ah_lb_size56_hash1_lb1_pw0;
389 case 64: return port_in_ah_lb_size64_hash1_lb1_pw0;
390 default: return NULL;
393 switch (p->params.dma_size) {
395 case 8: return port_in_ah_dma_size8_hash1_lb0_pw0;
396 case 16: return port_in_ah_dma_size16_hash1_lb0_pw0;
397 case 24: return port_in_ah_dma_size24_hash1_lb0_pw0;
398 case 32: return port_in_ah_dma_size32_hash1_lb0_pw0;
399 case 40: return port_in_ah_dma_size40_hash1_lb0_pw0;
400 case 48: return port_in_ah_dma_size48_hash1_lb0_pw0;
401 case 56: return port_in_ah_dma_size56_hash1_lb0_pw0;
402 case 64: return port_in_ah_dma_size64_hash1_lb0_pw0;
403 default: return NULL;
406 switch (p->params.dma_size) {
408 case 8: return port_in_ah_dma_size8_hash0_lb0_pw0;
409 case 16: return port_in_ah_dma_size16_hash0_lb0_pw0;
410 case 24: return port_in_ah_dma_size24_hash0_lb0_pw0;
411 case 32: return port_in_ah_dma_size32_hash0_lb0_pw0;
412 case 40: return port_in_ah_dma_size40_hash0_lb0_pw0;
413 case 48: return port_in_ah_dma_size48_hash0_lb0_pw0;
414 case 56: return port_in_ah_dma_size56_hash0_lb0_pw0;
415 case 64: return port_in_ah_dma_size64_hash0_lb0_pw0;
416 default: return NULL;
421 pipeline_passthrough_parse_args(struct pipeline_passthrough_params *p,
422 struct pipeline_params *params)
424 uint32_t dma_dst_offset_present = 0;
425 uint32_t dma_src_offset_present = 0;
426 uint32_t dma_src_mask_present = 0;
427 char dma_mask_str[PIPELINE_PASSTHROUGH_DMA_SIZE_MAX * 2 + 1];
428 uint32_t dma_size_present = 0;
429 uint32_t dma_hash_offset_present = 0;
430 uint32_t dma_hash_lb_present = 0;
435 p->dma_hash_enabled = 0;
436 p->dma_hash_lb_enabled = 0;
437 memset(p->dma_src_mask, 0xFF, sizeof(p->dma_src_mask));
439 p->swap_n_fields = 0;
441 for (i = 0; i < params->n_args; i++) {
442 char *arg_name = params->args_name[i];
443 char *arg_value = params->args_value[i];
446 if (strcmp(arg_name, "dma_dst_offset") == 0) {
449 PIPELINE_PARSE_ERR_DUPLICATE(
450 dma_dst_offset_present == 0, params->name,
452 dma_dst_offset_present = 1;
454 status = parser_read_uint32(&p->dma_dst_offset,
456 PIPELINE_PARSE_ERR_INV_VAL((status != -EINVAL),
457 params->name, arg_name, arg_value);
458 PIPELINE_PARSE_ERR_OUT_RNG((status != -ERANGE),
459 params->name, arg_name, arg_value);
467 if (strcmp(arg_name, "dma_src_offset") == 0) {
470 PIPELINE_PARSE_ERR_DUPLICATE(
471 dma_src_offset_present == 0, params->name,
473 dma_src_offset_present = 1;
475 status = parser_read_uint32(&p->dma_src_offset,
477 PIPELINE_PARSE_ERR_INV_VAL((status != -EINVAL),
478 params->name, arg_name, arg_value);
479 PIPELINE_PARSE_ERR_OUT_RNG((status != -ERANGE),
480 params->name, arg_name, arg_value);
488 if (strcmp(arg_name, "dma_size") == 0) {
491 PIPELINE_PARSE_ERR_DUPLICATE(
492 dma_size_present == 0, params->name,
494 dma_size_present = 1;
496 status = parser_read_uint32(&p->dma_size,
498 PIPELINE_PARSE_ERR_INV_VAL(((status != -EINVAL) &&
499 (p->dma_size != 0) &&
500 ((p->dma_size % 8) == 0)),
501 params->name, arg_name, arg_value);
502 PIPELINE_PARSE_ERR_OUT_RNG(((status != -ERANGE) &&
504 PIPELINE_PASSTHROUGH_DMA_SIZE_MAX)),
505 params->name, arg_name, arg_value);
513 if (strcmp(arg_name, "dma_src_mask") == 0) {
514 int mask_str_len = strlen(arg_value);
516 PIPELINE_PARSE_ERR_DUPLICATE(
517 dma_src_mask_present == 0,
518 params->name, arg_name);
519 dma_src_mask_present = 1;
521 PIPELINE_ARG_CHECK((mask_str_len <=
522 (PIPELINE_PASSTHROUGH_DMA_SIZE_MAX * 2)),
523 "Parse error in section \"%s\": entry "
524 "\"%s\" too long", params->name,
527 snprintf(dma_mask_str, mask_str_len + 1,
535 /* dma_hash_offset */
536 if (strcmp(arg_name, "dma_hash_offset") == 0) {
539 PIPELINE_PARSE_ERR_DUPLICATE(
540 dma_hash_offset_present == 0,
541 params->name, arg_name);
542 dma_hash_offset_present = 1;
544 status = parser_read_uint32(&p->dma_hash_offset,
546 PIPELINE_PARSE_ERR_INV_VAL((status != -EINVAL),
547 params->name, arg_name, arg_value);
548 PIPELINE_PARSE_ERR_OUT_RNG((status != -ERANGE),
549 params->name, arg_name, arg_value);
551 p->dma_hash_enabled = 1;
556 /* load_balance mode */
557 if (strcmp(arg_name, "lb") == 0) {
558 PIPELINE_PARSE_ERR_DUPLICATE(
559 dma_hash_lb_present == 0,
560 params->name, arg_name);
561 dma_hash_lb_present = 1;
563 if (strcmp(arg_value, "hash") &&
564 strcmp(arg_value, "HASH"))
566 PIPELINE_PARSE_ERR_INV_VAL(0,
571 p->dma_hash_lb_enabled = 1;
577 if (strcmp(arg_name, "swap") == 0) {
578 uint32_t a, b, n_args;
581 n_args = sscanf(arg_value, "%" SCNu32 " %" SCNu32 "%n",
583 PIPELINE_PARSE_ERR_INV_VAL(((n_args == 2) &&
584 ((size_t) len == strlen(arg_value))),
585 params->name, arg_name, arg_value);
587 p->swap_field0_offset[p->swap_n_fields] = a;
588 p->swap_field1_offset[p->swap_n_fields] = b;
596 PIPELINE_PARSE_ERR_INV_ENT(0, params->name, arg_name);
599 /* Check correlations between arguments */
600 PIPELINE_ARG_CHECK((p->dma_enabled + p->swap_enabled < 2),
601 "Parse error in section \"%s\": DMA and SWAP actions are both enabled",
603 PIPELINE_ARG_CHECK((dma_dst_offset_present == p->dma_enabled),
604 "Parse error in section \"%s\": missing entry "
605 "\"dma_dst_offset\"", params->name);
606 PIPELINE_ARG_CHECK((dma_src_offset_present == p->dma_enabled),
607 "Parse error in section \"%s\": missing entry "
608 "\"dma_src_offset\"", params->name);
609 PIPELINE_ARG_CHECK((dma_size_present == p->dma_enabled),
610 "Parse error in section \"%s\": missing entry "
611 "\"dma_size\"", params->name);
612 PIPELINE_ARG_CHECK((p->dma_hash_enabled <= p->dma_enabled),
613 "Parse error in section \"%s\": missing all DMA entries",
615 PIPELINE_ARG_CHECK((p->dma_hash_lb_enabled <= p->dma_hash_enabled),
616 "Parse error in section \"%s\": missing all DMA hash entries ",
619 if (dma_src_mask_present) {
620 uint32_t dma_size = p->dma_size;
623 PIPELINE_ARG_CHECK((strlen(dma_mask_str) ==
624 (dma_size * 2)), "Parse error in section "
625 "\"%s\": dma_src_mask should have exactly %u hex "
626 "digits", params->name, (dma_size * 2));
628 status = parse_hex_string(dma_mask_str, p->dma_src_mask,
631 PIPELINE_PARSE_ERR_INV_VAL(((status == 0) &&
632 (dma_size == p->dma_size)), params->name,
633 "dma_src_mask", dma_mask_str);
636 if (p->dma_hash_lb_enabled)
637 PIPELINE_ARG_CHECK((params->n_ports_out > 1),
638 "Parse error in section \"%s\": entry \"lb\" not "
639 "allowed for single output port pipeline",
642 PIPELINE_ARG_CHECK(((params->n_ports_in >= params->n_ports_out)
643 && ((params->n_ports_in % params->n_ports_out) == 0)),
644 "Parse error in section \"%s\": n_ports_in needs to be "
645 "a multiple of n_ports_out (lb mode disabled)",
651 static rte_table_hash_op_hash
652 get_hash_function(struct pipeline_passthrough *p)
654 switch (p->params.dma_size) {
656 case 8: return hash_default_key8;
657 case 16: return hash_default_key16;
658 case 24: return hash_default_key24;
659 case 32: return hash_default_key32;
660 case 40: return hash_default_key40;
661 case 48: return hash_default_key48;
662 case 56: return hash_default_key56;
663 case 64: return hash_default_key64;
664 default: return NULL;
669 pipeline_passthrough_swap_convert(struct pipeline_passthrough *p)
673 p->swap_n_fields = 0;
675 for (i = 0; i < p->params.swap_n_fields; i++) {
676 uint32_t offset0 = p->params.swap_field0_offset[i];
677 uint32_t offset1 = p->params.swap_field1_offset[i];
678 uint32_t size = offset1 - offset0;
682 if ((offset0 >= offset1) ||
683 (size > PIPELINE_PASSTHROUGH_SWAP_FIELD_SIZE_MAX) ||
684 (p->swap_n_fields >= SWAP_DIM))
687 for (j = 0; j < (size / sizeof(uint64_t)); j++) {
688 p->swap_field0_offset[p->swap_n_fields] = offset0;
689 p->swap_field1_offset[p->swap_n_fields] = offset1;
690 p->swap_field_mask[p->swap_n_fields] = UINT64_MAX;
692 offset0 += sizeof(uint64_t);
693 offset1 += sizeof(uint64_t);
695 if (size % sizeof(uint64_t)) {
696 uint32_t n_bits = (size % sizeof(uint64_t)) * 8;
698 p->swap_field0_offset[p->swap_n_fields] = offset0;
699 p->swap_field1_offset[p->swap_n_fields] = offset1;
700 p->swap_field_mask[p->swap_n_fields] =
701 RTE_LEN2MASK(n_bits, uint64_t);
710 pipeline_passthrough_init(struct pipeline_params *params,
711 __rte_unused void *arg)
714 struct pipeline_passthrough *p_pt;
717 /* Check input arguments */
718 if ((params == NULL) ||
719 (params->n_ports_in == 0) ||
720 (params->n_ports_out == 0))
723 /* Memory allocation */
724 size = RTE_CACHE_LINE_ROUNDUP(sizeof(struct pipeline_passthrough));
725 p = rte_zmalloc(NULL, size, RTE_CACHE_LINE_SIZE);
726 p_pt = (struct pipeline_passthrough *) p;
730 strcpy(p->name, params->name);
731 p->log_level = params->log_level;
733 PLOG(p, HIGH, "Pass-through");
735 /* Parse arguments */
736 if (pipeline_passthrough_parse_args(&p_pt->params, params))
738 if (pipeline_passthrough_swap_convert(p_pt))
740 p_pt->f_hash = get_hash_function(p_pt);
744 struct rte_pipeline_params pipeline_params = {
745 .name = "PASS-THROUGH",
746 .socket_id = params->socket_id,
750 p->p = rte_pipeline_create(&pipeline_params);
757 p->n_ports_in = params->n_ports_in;
758 p->n_ports_out = params->n_ports_out;
759 p->n_tables = p->n_ports_in;
762 for (i = 0; i < p->n_ports_in; i++) {
763 struct rte_pipeline_port_in_params port_params = {
764 .ops = pipeline_port_in_params_get_ops(
765 ¶ms->port_in[i]),
766 .arg_create = pipeline_port_in_params_convert(
767 ¶ms->port_in[i]),
768 .f_action = get_port_in_ah(p_pt),
770 .burst_size = params->port_in[i].burst_size,
773 int status = rte_pipeline_port_in_create(p->p,
778 rte_pipeline_free(p->p);
785 for (i = 0; i < p->n_ports_out; i++) {
786 struct rte_pipeline_port_out_params port_params = {
787 .ops = pipeline_port_out_params_get_ops(
788 ¶ms->port_out[i]),
789 .arg_create = pipeline_port_out_params_convert(
790 ¶ms->port_out[i]),
795 int status = rte_pipeline_port_out_create(p->p,
800 rte_pipeline_free(p->p);
807 for (i = 0; i < p->n_ports_in; i++) {
808 struct rte_pipeline_table_params table_params = {
809 .ops = &rte_table_stub_ops,
811 .f_action_hit = NULL,
812 .f_action_miss = NULL,
814 .action_data_size = 0,
817 int status = rte_pipeline_table_create(p->p,
822 rte_pipeline_free(p->p);
828 /* Connecting input ports to tables */
829 for (i = 0; i < p->n_ports_in; i++) {
830 int status = rte_pipeline_port_in_connect_to_table(p->p,
835 rte_pipeline_free(p->p);
841 /* Add entries to tables */
842 for (i = 0; i < p->n_ports_in; i++) {
843 uint32_t port_out_id = (p_pt->params.dma_hash_lb_enabled == 0) ?
844 (i / (p->n_ports_in / p->n_ports_out)) :
847 struct rte_pipeline_table_entry default_entry = {
848 .action = RTE_PIPELINE_ACTION_PORT,
849 {.port_id = p->port_out_id[port_out_id]},
852 struct rte_pipeline_table_entry *default_entry_ptr;
854 int status = rte_pipeline_table_default_entry_add(p->p,
860 rte_pipeline_free(p->p);
866 /* Enable input ports */
867 for (i = 0; i < p->n_ports_in; i++) {
868 int status = rte_pipeline_port_in_enable(p->p,
872 rte_pipeline_free(p->p);
878 /* Check pipeline consistency */
879 if (rte_pipeline_check(p->p) < 0) {
880 rte_pipeline_free(p->p);
886 p->n_msgq = params->n_msgq;
887 for (i = 0; i < p->n_msgq; i++)
888 p->msgq_in[i] = params->msgq_in[i];
889 for (i = 0; i < p->n_msgq; i++)
890 p->msgq_out[i] = params->msgq_out[i];
892 /* Message handlers */
893 memcpy(p->handlers, handlers, sizeof(p->handlers));
899 pipeline_passthrough_free(void *pipeline)
901 struct pipeline *p = (struct pipeline *) pipeline;
903 /* Check input arguments */
908 rte_pipeline_free(p->p);
914 pipeline_passthrough_timer(void *pipeline)
916 struct pipeline *p = (struct pipeline *) pipeline;
918 pipeline_msg_req_handle(p);
919 rte_pipeline_flush(p->p);
924 struct pipeline_be_ops pipeline_passthrough_be_ops = {
925 .f_init = pipeline_passthrough_init,
926 .f_free = pipeline_passthrough_free,
928 .f_timer = pipeline_passthrough_timer,