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38 #include <rte_malloc.h>
41 #include <rte_port_ring.h>
42 #include <rte_table_stub.h>
43 #include <rte_pipeline.h>
48 app_main_loop_pipeline_passthrough(void) {
49 struct rte_pipeline_params pipeline_params = {
51 .socket_id = rte_socket_id(),
54 struct rte_pipeline *p;
55 uint32_t port_in_id[APP_MAX_PORTS];
56 uint32_t port_out_id[APP_MAX_PORTS];
57 uint32_t table_id[APP_MAX_PORTS];
60 uint32_t core_id = rte_lcore_id();
61 struct app_core_params *core_params = app_get_core_params(core_id);
63 if ((core_params == NULL) || (core_params->core_type != APP_CORE_PT))
64 rte_panic("Core %u misconfiguration\n", core_id);
66 RTE_LOG(INFO, USER1, "Core %u is doing pass-through\n", core_id);
68 /* Pipeline configuration */
69 p = rte_pipeline_create(&pipeline_params);
71 rte_panic("%s: Unable to configure the pipeline\n", __func__);
73 /* Input port configuration */
74 for (i = 0; i < app.n_ports; i++) {
75 struct rte_port_ring_reader_params port_ring_params = {
76 .ring = app.rings[core_params->swq_in[i]],
79 struct rte_pipeline_port_in_params port_params = {
80 .ops = &rte_port_ring_reader_ops,
81 .arg_create = (void *) &port_ring_params,
84 .burst_size = app.bsz_swq_rd,
87 if (rte_pipeline_port_in_create(p, &port_params,
89 rte_panic("%s: Unable to configure input port for "
90 "ring %d\n", __func__, i);
94 /* Output port configuration */
95 for (i = 0; i < app.n_ports; i++) {
96 struct rte_port_ring_writer_params port_ring_params = {
97 .ring = app.rings[core_params->swq_out[i]],
98 .tx_burst_sz = app.bsz_swq_wr,
101 struct rte_pipeline_port_out_params port_params = {
102 .ops = &rte_port_ring_writer_ops,
103 .arg_create = (void *) &port_ring_params,
105 .f_action_bulk = NULL,
109 if (rte_pipeline_port_out_create(p, &port_params,
111 rte_panic("%s: Unable to configure output port for "
112 "ring %d\n", __func__, i);
116 /* Table configuration */
117 for (i = 0; i < app.n_ports; i++) {
118 struct rte_pipeline_table_params table_params = {
119 .ops = &rte_table_stub_ops,
121 .f_action_hit = NULL,
122 .f_action_miss = NULL,
124 .action_data_size = 0,
127 if (rte_pipeline_table_create(p, &table_params, &table_id[i]))
128 rte_panic("%s: Unable to configure table %u\n",
132 /* Interconnecting ports and tables */
133 for (i = 0; i < app.n_ports; i++) {
134 if (rte_pipeline_port_in_connect_to_table(p, port_in_id[i],
136 rte_panic("%s: Unable to connect input port %u to "
137 "table %u\n", __func__, port_in_id[i],
142 /* Add entries to tables */
143 for (i = 0; i < app.n_ports; i++) {
144 struct rte_pipeline_table_entry default_entry = {
145 .action = RTE_PIPELINE_ACTION_PORT,
146 {.port_id = port_out_id[i]},
149 struct rte_pipeline_table_entry *default_entry_ptr;
151 if (rte_pipeline_table_default_entry_add(p, table_id[i],
152 &default_entry, &default_entry_ptr))
153 rte_panic("%s: Unable to add default entry to "
154 "table %u\n", __func__, table_id[i]);
157 /* Enable input ports */
158 for (i = 0; i < app.n_ports; i++)
159 if (rte_pipeline_port_in_enable(p, port_in_id[i]))
160 rte_panic("Unable to enable input port %u\n",
163 /* Check pipeline consistency */
164 if (rte_pipeline_check(p) < 0)
165 rte_panic("%s: Pipeline consistency check failed\n", __func__);
171 if ((i & APP_FLUSH) == 0)
172 rte_pipeline_flush(p);
177 app_main_loop_passthrough(void) {
178 struct app_mbuf_array *m;
181 uint32_t core_id = rte_lcore_id();
182 struct app_core_params *core_params = app_get_core_params(core_id);
184 if ((core_params == NULL) || (core_params->core_type != APP_CORE_PT))
185 rte_panic("Core %u misconfiguration\n", core_id);
187 RTE_LOG(INFO, USER1, "Core %u is doing pass-through (no pipeline)\n",
190 m = rte_malloc_socket(NULL, sizeof(struct app_mbuf_array),
191 CACHE_LINE_SIZE, rte_socket_id());
193 rte_panic("%s: cannot allocate buffer space\n", __func__);
195 for (i = 0; ; i = ((i + 1) & (app.n_ports - 1))) {
198 ret = rte_ring_sc_dequeue_bulk(
199 app.rings[core_params->swq_in[i]],
207 ret = rte_ring_sp_enqueue_bulk(
208 app.rings[core_params->swq_out[i]],