1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2018 Intel Corporation
7 #include <rte_common.h>
8 #include <rte_string_fns.h>
12 static struct rte_sched_subport_profile_params
13 subport_profile[TMGR_SUBPORT_PROFILE_MAX];
15 static uint32_t n_subport_profiles;
17 static struct rte_sched_pipe_params
18 pipe_profile[TMGR_PIPE_PROFILE_MAX];
20 static uint32_t n_pipe_profiles;
22 static const struct rte_sched_subport_params subport_params_default = {
23 .n_pipes_per_subport_enabled = 0, /* filled at runtime */
24 .qsize = {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64},
25 .pipe_profiles = pipe_profile,
26 .n_pipe_profiles = 0, /* filled at run time */
27 .n_max_pipe_profiles = RTE_DIM(pipe_profile),
30 /* Traffic Class 0 Colors Green / Yellow / Red */
31 [0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
32 [0][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
33 [0][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
35 /* Traffic Class 1 - Colors Green / Yellow / Red */
36 [1][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
37 [1][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
38 [1][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
40 /* Traffic Class 2 - Colors Green / Yellow / Red */
41 [2][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
42 [2][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
43 [2][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
45 /* Traffic Class 3 - Colors Green / Yellow / Red */
46 [3][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
47 [3][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
48 [3][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
50 /* Traffic Class 4 - Colors Green / Yellow / Red */
51 [4][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
52 [4][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
53 [4][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
55 /* Traffic Class 5 - Colors Green / Yellow / Red */
56 [5][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
57 [5][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
58 [5][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
60 /* Traffic Class 6 - Colors Green / Yellow / Red */
61 [6][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
62 [6][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
63 [6][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
65 /* Traffic Class 7 - Colors Green / Yellow / Red */
66 [7][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
67 [7][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
68 [7][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
70 /* Traffic Class 8 - Colors Green / Yellow / Red */
71 [8][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
72 [8][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
73 [8][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
75 /* Traffic Class 9 - Colors Green / Yellow / Red */
76 [9][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
77 [9][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
78 [9][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
80 /* Traffic Class 10 - Colors Green / Yellow / Red */
81 [10][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
82 [10][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
83 [10][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
85 /* Traffic Class 11 - Colors Green / Yellow / Red */
86 [11][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
87 [11][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
88 [11][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
90 /* Traffic Class 12 - Colors Green / Yellow / Red */
91 [12][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
92 [12][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
93 [12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
95 #endif /* RTE_SCHED_CMAN */
98 static struct tmgr_port_list tmgr_port_list;
103 TAILQ_INIT(&tmgr_port_list);
109 tmgr_port_find(const char *name)
111 struct tmgr_port *tmgr_port;
116 TAILQ_FOREACH(tmgr_port, &tmgr_port_list, node)
117 if (strcmp(tmgr_port->name, name) == 0)
124 tmgr_subport_profile_add(struct rte_sched_subport_profile_params *params)
126 /* Check input params */
131 memcpy(&subport_profile[n_subport_profiles],
135 n_subport_profiles++;
141 tmgr_pipe_profile_add(struct rte_sched_pipe_params *p)
143 /* Check input params */
148 memcpy(&pipe_profile[n_pipe_profiles],
158 tmgr_port_create(const char *name, struct tmgr_port_params *params)
160 struct rte_sched_subport_params subport_params;
161 struct rte_sched_port_params p;
162 struct tmgr_port *tmgr_port;
163 struct rte_sched_port *s;
166 /* Check input params */
167 if ((name == NULL) ||
168 tmgr_port_find(name) ||
170 (params->n_subports_per_port == 0) ||
171 (params->n_pipes_per_subport == 0) ||
172 (params->cpu_id >= RTE_MAX_NUMA_NODES) ||
173 (n_subport_profiles == 0) ||
174 (n_pipe_profiles == 0))
177 /* Resource create */
179 p.socket = (int) params->cpu_id;
180 p.rate = params->rate;
182 p.frame_overhead = params->frame_overhead;
183 p.n_subports_per_port = params->n_subports_per_port;
184 p.n_subport_profiles = n_subport_profiles;
185 p.subport_profiles = subport_profile;
186 p.n_max_subport_profiles = TMGR_SUBPORT_PROFILE_MAX;
187 p.n_pipes_per_subport = params->n_pipes_per_subport;
190 s = rte_sched_port_config(&p);
194 memcpy(&subport_params, &subport_params_default,
195 sizeof(subport_params_default));
197 subport_params.n_pipe_profiles = n_pipe_profiles;
198 subport_params.n_pipes_per_subport_enabled =
199 params->n_pipes_per_subport;
201 for (i = 0; i < params->n_subports_per_port; i++) {
204 status = rte_sched_subport_config(
211 rte_sched_port_free(s);
215 for (j = 0; j < params->n_pipes_per_subport; j++) {
217 status = rte_sched_pipe_config(
224 rte_sched_port_free(s);
230 /* Node allocation */
231 tmgr_port = calloc(1, sizeof(struct tmgr_port));
232 if (tmgr_port == NULL) {
233 rte_sched_port_free(s);
238 strlcpy(tmgr_port->name, name, sizeof(tmgr_port->name));
240 tmgr_port->n_subports_per_port = params->n_subports_per_port;
241 tmgr_port->n_pipes_per_subport = params->n_pipes_per_subport;
243 /* Node add to list */
244 TAILQ_INSERT_TAIL(&tmgr_port_list, tmgr_port, node);
250 tmgr_subport_config(const char *port_name,
252 uint32_t subport_profile_id)
254 struct tmgr_port *port;
257 /* Check input params */
258 if (port_name == NULL)
261 port = tmgr_port_find(port_name);
262 if ((port == NULL) ||
263 (subport_id >= port->n_subports_per_port) ||
264 (subport_profile_id >= n_subport_profiles))
267 /* Resource config */
268 status = rte_sched_subport_config(
278 tmgr_pipe_config(const char *port_name,
280 uint32_t pipe_id_first,
281 uint32_t pipe_id_last,
282 uint32_t pipe_profile_id)
284 struct tmgr_port *port;
287 /* Check input params */
288 if (port_name == NULL)
291 port = tmgr_port_find(port_name);
292 if ((port == NULL) ||
293 (subport_id >= port->n_subports_per_port) ||
294 (pipe_id_first >= port->n_pipes_per_subport) ||
295 (pipe_id_last >= port->n_pipes_per_subport) ||
296 (pipe_id_first > pipe_id_last) ||
297 (pipe_profile_id >= n_pipe_profiles))
300 /* Resource config */
301 for (i = pipe_id_first; i <= pipe_id_last; i++) {
304 status = rte_sched_pipe_config(
308 (int) pipe_profile_id);