1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2018 Intel Corporation
7 #include <rte_common.h>
8 #include <rte_string_fns.h>
12 static struct rte_sched_subport_profile_params
13 subport_profile[TMGR_SUBPORT_PROFILE_MAX];
15 static uint32_t n_subport_profiles;
17 static struct rte_sched_pipe_params
18 pipe_profile[TMGR_PIPE_PROFILE_MAX];
21 static struct rte_sched_cman_params cman_params = {
23 /* Traffic Class 0 Colors Green / Yellow / Red */
24 [0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
25 [0][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
26 [0][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
28 /* Traffic Class 1 - Colors Green / Yellow / Red */
29 [1][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
30 [1][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
31 [1][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
33 /* Traffic Class 2 - Colors Green / Yellow / Red */
34 [2][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
35 [2][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
36 [2][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
38 /* Traffic Class 3 - Colors Green / Yellow / Red */
39 [3][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
40 [3][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
41 [3][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
43 /* Traffic Class 4 - Colors Green / Yellow / Red */
44 [4][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
45 [4][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
46 [4][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
48 /* Traffic Class 5 - Colors Green / Yellow / Red */
49 [5][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
50 [5][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
51 [5][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
53 /* Traffic Class 6 - Colors Green / Yellow / Red */
54 [6][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
55 [6][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
56 [6][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
58 /* Traffic Class 7 - Colors Green / Yellow / Red */
59 [7][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
60 [7][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
61 [7][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
63 /* Traffic Class 8 - Colors Green / Yellow / Red */
64 [8][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
65 [8][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
66 [8][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
68 /* Traffic Class 9 - Colors Green / Yellow / Red */
69 [9][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
70 [9][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
71 [9][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
73 /* Traffic Class 10 - Colors Green / Yellow / Red */
74 [10][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
75 [10][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
76 [10][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
78 /* Traffic Class 11 - Colors Green / Yellow / Red */
79 [11][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
80 [11][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
81 [11][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
83 /* Traffic Class 12 - Colors Green / Yellow / Red */
84 [12][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
85 [12][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
86 [12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
89 #endif /* RTE_SCHED_CMAN */
91 static uint32_t n_pipe_profiles;
93 static const struct rte_sched_subport_params subport_params_default = {
94 .n_pipes_per_subport_enabled = 0, /* filled at runtime */
95 .qsize = {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64},
96 .pipe_profiles = pipe_profile,
97 .n_pipe_profiles = 0, /* filled at run time */
98 .n_max_pipe_profiles = RTE_DIM(pipe_profile),
100 .cman_params = &cman_params,
101 #endif /* RTE_SCHED_CMAN */
104 static struct tmgr_port_list tmgr_port_list;
109 TAILQ_INIT(&tmgr_port_list);
115 tmgr_port_find(const char *name)
117 struct tmgr_port *tmgr_port;
122 TAILQ_FOREACH(tmgr_port, &tmgr_port_list, node)
123 if (strcmp(tmgr_port->name, name) == 0)
130 tmgr_subport_profile_add(struct rte_sched_subport_profile_params *params)
132 /* Check input params */
137 memcpy(&subport_profile[n_subport_profiles],
141 n_subport_profiles++;
147 tmgr_pipe_profile_add(struct rte_sched_pipe_params *p)
149 /* Check input params */
154 memcpy(&pipe_profile[n_pipe_profiles],
164 tmgr_port_create(const char *name, struct tmgr_port_params *params)
166 struct rte_sched_subport_params subport_params;
167 struct rte_sched_port_params p;
168 struct tmgr_port *tmgr_port;
169 struct rte_sched_port *s;
172 /* Check input params */
173 if ((name == NULL) ||
174 tmgr_port_find(name) ||
176 (params->n_subports_per_port == 0) ||
177 (params->n_pipes_per_subport == 0) ||
178 (params->cpu_id >= RTE_MAX_NUMA_NODES) ||
179 (n_subport_profiles == 0) ||
180 (n_pipe_profiles == 0))
183 /* Resource create */
185 p.socket = (int) params->cpu_id;
186 p.rate = params->rate;
188 p.frame_overhead = params->frame_overhead;
189 p.n_subports_per_port = params->n_subports_per_port;
190 p.n_subport_profiles = n_subport_profiles;
191 p.subport_profiles = subport_profile;
192 p.n_max_subport_profiles = TMGR_SUBPORT_PROFILE_MAX;
193 p.n_pipes_per_subport = params->n_pipes_per_subport;
196 s = rte_sched_port_config(&p);
200 memcpy(&subport_params, &subport_params_default,
201 sizeof(subport_params_default));
203 subport_params.n_pipe_profiles = n_pipe_profiles;
204 subport_params.n_pipes_per_subport_enabled =
205 params->n_pipes_per_subport;
207 for (i = 0; i < params->n_subports_per_port; i++) {
210 status = rte_sched_subport_config(
217 rte_sched_port_free(s);
221 for (j = 0; j < params->n_pipes_per_subport; j++) {
223 status = rte_sched_pipe_config(
230 rte_sched_port_free(s);
236 /* Node allocation */
237 tmgr_port = calloc(1, sizeof(struct tmgr_port));
238 if (tmgr_port == NULL) {
239 rte_sched_port_free(s);
244 strlcpy(tmgr_port->name, name, sizeof(tmgr_port->name));
246 tmgr_port->n_subports_per_port = params->n_subports_per_port;
247 tmgr_port->n_pipes_per_subport = params->n_pipes_per_subport;
249 /* Node add to list */
250 TAILQ_INSERT_TAIL(&tmgr_port_list, tmgr_port, node);
256 tmgr_subport_config(const char *port_name,
258 uint32_t subport_profile_id)
260 struct tmgr_port *port;
263 /* Check input params */
264 if (port_name == NULL)
267 port = tmgr_port_find(port_name);
268 if ((port == NULL) ||
269 (subport_id >= port->n_subports_per_port) ||
270 (subport_profile_id >= n_subport_profiles))
273 /* Resource config */
274 status = rte_sched_subport_config(
284 tmgr_pipe_config(const char *port_name,
286 uint32_t pipe_id_first,
287 uint32_t pipe_id_last,
288 uint32_t pipe_profile_id)
290 struct tmgr_port *port;
293 /* Check input params */
294 if (port_name == NULL)
297 port = tmgr_port_find(port_name);
298 if ((port == NULL) ||
299 (subport_id >= port->n_subports_per_port) ||
300 (pipe_id_first >= port->n_pipes_per_subport) ||
301 (pipe_id_last >= port->n_pipes_per_subport) ||
302 (pipe_id_first > pipe_id_last) ||
303 (pipe_profile_id >= n_pipe_profiles))
306 /* Resource config */
307 for (i = pipe_id_first; i <= pipe_id_last; i++) {
310 status = rte_sched_pipe_config(
314 (int) pipe_profile_id);