1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
8 #include <rte_cycles.h>
9 #include <rte_ethdev.h>
10 #include <rte_eventdev.h>
11 #include <rte_event_eth_rx_adapter.h>
12 #include <rte_event_eth_tx_adapter.h>
13 #include <rte_lcore.h>
14 #include <rte_spinlock.h>
16 #include "l2fwd_common.h"
17 #include "l2fwd_event.h"
20 l2fwd_event_device_setup_generic(struct l2fwd_resources *rsrc)
22 struct l2fwd_event_resources *evt_rsrc = rsrc->evt_rsrc;
23 struct rte_event_dev_config event_d_conf = {
24 .nb_events_limit = 4096,
25 .nb_event_queue_flows = 1024,
26 .nb_event_port_dequeue_depth = 128,
27 .nb_event_port_enqueue_depth = 128
29 struct rte_event_dev_info dev_info;
30 const uint8_t event_d_id = 0; /* Always use first event device only */
31 uint32_t event_queue_cfg = 0;
32 uint16_t ethdev_count = 0;
33 uint16_t num_workers = 0;
37 RTE_ETH_FOREACH_DEV(port_id) {
38 if ((rsrc->enabled_port_mask & (1 << port_id)) == 0)
43 /* Event device configurtion */
44 rte_event_dev_info_get(event_d_id, &dev_info);
45 evt_rsrc->disable_implicit_release = !!(dev_info.event_dev_cap &
46 RTE_EVENT_DEV_CAP_IMPLICIT_RELEASE_DISABLE);
48 if (dev_info.event_dev_cap & RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES)
49 event_queue_cfg |= RTE_EVENT_QUEUE_CFG_ALL_TYPES;
51 /* One queue for each ethdev port + one Tx adapter Single link queue. */
52 event_d_conf.nb_event_queues = ethdev_count + 1;
53 if (dev_info.max_event_queues < event_d_conf.nb_event_queues)
54 event_d_conf.nb_event_queues = dev_info.max_event_queues;
56 if (dev_info.max_num_events < event_d_conf.nb_events_limit)
57 event_d_conf.nb_events_limit = dev_info.max_num_events;
59 if (dev_info.max_event_queue_flows < event_d_conf.nb_event_queue_flows)
60 event_d_conf.nb_event_queue_flows =
61 dev_info.max_event_queue_flows;
63 if (dev_info.max_event_port_dequeue_depth <
64 event_d_conf.nb_event_port_dequeue_depth)
65 event_d_conf.nb_event_port_dequeue_depth =
66 dev_info.max_event_port_dequeue_depth;
68 if (dev_info.max_event_port_enqueue_depth <
69 event_d_conf.nb_event_port_enqueue_depth)
70 event_d_conf.nb_event_port_enqueue_depth =
71 dev_info.max_event_port_enqueue_depth;
73 num_workers = rte_lcore_count() - rte_service_lcore_count();
74 if (dev_info.max_event_ports < num_workers)
75 num_workers = dev_info.max_event_ports;
77 event_d_conf.nb_event_ports = num_workers;
78 evt_rsrc->evp.nb_ports = num_workers;
79 evt_rsrc->evq.nb_queues = event_d_conf.nb_event_queues;
81 evt_rsrc->has_burst = !!(dev_info.event_dev_cap &
82 RTE_EVENT_DEV_CAP_BURST_MODE);
84 ret = rte_event_dev_configure(event_d_id, &event_d_conf);
86 rte_panic("Error in configuring event device\n");
88 evt_rsrc->event_d_id = event_d_id;
89 return event_queue_cfg;
93 l2fwd_event_port_setup_generic(struct l2fwd_resources *rsrc)
95 struct l2fwd_event_resources *evt_rsrc = rsrc->evt_rsrc;
96 uint8_t event_d_id = evt_rsrc->event_d_id;
97 struct rte_event_port_conf event_p_conf = {
100 .new_event_threshold = 4096
102 struct rte_event_port_conf def_p_conf;
106 evt_rsrc->evp.event_p_id = (uint8_t *)malloc(sizeof(uint8_t) *
107 evt_rsrc->evp.nb_ports);
108 if (!evt_rsrc->evp.event_p_id)
109 rte_panic("No space is available\n");
111 memset(&def_p_conf, 0, sizeof(struct rte_event_port_conf));
112 rte_event_port_default_conf_get(event_d_id, 0, &def_p_conf);
114 if (def_p_conf.new_event_threshold < event_p_conf.new_event_threshold)
115 event_p_conf.new_event_threshold =
116 def_p_conf.new_event_threshold;
118 if (def_p_conf.dequeue_depth < event_p_conf.dequeue_depth)
119 event_p_conf.dequeue_depth = def_p_conf.dequeue_depth;
121 if (def_p_conf.enqueue_depth < event_p_conf.enqueue_depth)
122 event_p_conf.enqueue_depth = def_p_conf.enqueue_depth;
124 event_p_conf.disable_implicit_release =
125 evt_rsrc->disable_implicit_release;
126 evt_rsrc->deq_depth = def_p_conf.dequeue_depth;
128 for (event_p_id = 0; event_p_id < evt_rsrc->evp.nb_ports;
130 ret = rte_event_port_setup(event_d_id, event_p_id,
133 rte_panic("Error in configuring event port %d\n",
136 ret = rte_event_port_link(event_d_id, event_p_id,
137 evt_rsrc->evq.event_q_id,
139 evt_rsrc->evq.nb_queues - 1);
140 if (ret != (evt_rsrc->evq.nb_queues - 1))
141 rte_panic("Error in linking event port %d to queues\n",
143 evt_rsrc->evp.event_p_id[event_p_id] = event_p_id;
146 rte_spinlock_init(&evt_rsrc->evp.lock);
148 evt_rsrc->def_p_conf = event_p_conf;
152 l2fwd_event_queue_setup_generic(struct l2fwd_resources *rsrc,
153 uint32_t event_queue_cfg)
155 struct l2fwd_event_resources *evt_rsrc = rsrc->evt_rsrc;
156 uint8_t event_d_id = evt_rsrc->event_d_id;
157 struct rte_event_queue_conf event_q_conf = {
158 .nb_atomic_flows = 1024,
159 .nb_atomic_order_sequences = 1024,
160 .event_queue_cfg = event_queue_cfg,
161 .priority = RTE_EVENT_DEV_PRIORITY_NORMAL
163 struct rte_event_queue_conf def_q_conf;
167 event_q_conf.schedule_type = rsrc->sched_type;
168 evt_rsrc->evq.event_q_id = (uint8_t *)malloc(sizeof(uint8_t) *
169 evt_rsrc->evq.nb_queues);
170 if (!evt_rsrc->evq.event_q_id)
171 rte_panic("Memory allocation failure\n");
173 rte_event_queue_default_conf_get(event_d_id, 0, &def_q_conf);
174 if (def_q_conf.nb_atomic_flows < event_q_conf.nb_atomic_flows)
175 event_q_conf.nb_atomic_flows = def_q_conf.nb_atomic_flows;
177 for (event_q_id = 0; event_q_id < (evt_rsrc->evq.nb_queues - 1);
179 ret = rte_event_queue_setup(event_d_id, event_q_id,
182 rte_panic("Error in configuring event queue\n");
183 evt_rsrc->evq.event_q_id[event_q_id] = event_q_id;
186 event_q_conf.event_queue_cfg |= RTE_EVENT_QUEUE_CFG_SINGLE_LINK;
187 event_q_conf.priority = RTE_EVENT_DEV_PRIORITY_HIGHEST,
188 ret = rte_event_queue_setup(event_d_id, event_q_id, &event_q_conf);
190 rte_panic("Error in configuring event queue for Tx adapter\n");
191 evt_rsrc->evq.event_q_id[event_q_id] = event_q_id;
195 l2fwd_event_set_generic_ops(struct event_setup_ops *ops)
197 ops->event_device_setup = l2fwd_event_device_setup_generic;
198 ops->event_queue_setup = l2fwd_event_queue_setup_generic;
199 ops->event_port_setup = l2fwd_event_port_setup_generic;