1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
8 #include "l3fwd_event.h"
11 l3fwd_event_device_setup_generic(void)
13 struct l3fwd_event_resources *evt_rsrc = l3fwd_get_eventdev_rsrc();
14 struct rte_event_dev_config event_d_conf = {
15 .nb_events_limit = 4096,
16 .nb_event_queue_flows = 1024,
17 .nb_event_port_dequeue_depth = 128,
18 .nb_event_port_enqueue_depth = 128
20 struct rte_event_dev_info dev_info;
21 const uint8_t event_d_id = 0; /* Always use first event device only */
22 uint32_t event_queue_cfg = 0;
23 uint16_t ethdev_count = 0;
24 uint16_t num_workers = 0;
28 RTE_ETH_FOREACH_DEV(port_id) {
29 if ((evt_rsrc->port_mask & (1 << port_id)) == 0)
34 /* Event device configuration */
35 rte_event_dev_info_get(event_d_id, &dev_info);
36 /* Enable implicit release */
37 if (dev_info.event_dev_cap & RTE_EVENT_DEV_CAP_IMPLICIT_RELEASE_DISABLE)
38 evt_rsrc->disable_implicit_release = 0;
40 if (dev_info.event_dev_cap & RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES)
41 event_queue_cfg |= RTE_EVENT_QUEUE_CFG_ALL_TYPES;
43 /* One queue for each ethdev port + one Tx adapter Single link queue. */
44 event_d_conf.nb_event_queues = ethdev_count + 1;
45 if (dev_info.max_event_queues < event_d_conf.nb_event_queues)
46 event_d_conf.nb_event_queues = dev_info.max_event_queues;
48 if (dev_info.max_num_events < event_d_conf.nb_events_limit)
49 event_d_conf.nb_events_limit = dev_info.max_num_events;
51 if (dev_info.max_event_queue_flows < event_d_conf.nb_event_queue_flows)
52 event_d_conf.nb_event_queue_flows =
53 dev_info.max_event_queue_flows;
55 if (dev_info.max_event_port_dequeue_depth <
56 event_d_conf.nb_event_port_dequeue_depth)
57 event_d_conf.nb_event_port_dequeue_depth =
58 dev_info.max_event_port_dequeue_depth;
60 if (dev_info.max_event_port_enqueue_depth <
61 event_d_conf.nb_event_port_enqueue_depth)
62 event_d_conf.nb_event_port_enqueue_depth =
63 dev_info.max_event_port_enqueue_depth;
65 num_workers = rte_lcore_count() - rte_service_lcore_count();
66 if (dev_info.max_event_ports < num_workers)
67 num_workers = dev_info.max_event_ports;
69 event_d_conf.nb_event_ports = num_workers;
70 evt_rsrc->evp.nb_ports = num_workers;
71 evt_rsrc->evq.nb_queues = event_d_conf.nb_event_queues;
73 evt_rsrc->has_burst = !!(dev_info.event_dev_cap &
74 RTE_EVENT_DEV_CAP_BURST_MODE);
76 ret = rte_event_dev_configure(event_d_id, &event_d_conf);
78 rte_panic("Error in configuring event device\n");
80 evt_rsrc->event_d_id = event_d_id;
81 return event_queue_cfg;
85 l3fwd_event_port_setup_generic(void)
87 struct l3fwd_event_resources *evt_rsrc = l3fwd_get_eventdev_rsrc();
88 uint8_t event_d_id = evt_rsrc->event_d_id;
89 struct rte_event_port_conf event_p_conf = {
92 .new_event_threshold = 4096
94 struct rte_event_port_conf def_p_conf;
98 evt_rsrc->evp.event_p_id = (uint8_t *)malloc(sizeof(uint8_t) *
99 evt_rsrc->evp.nb_ports);
100 if (!evt_rsrc->evp.event_p_id)
101 rte_panic("No space is available\n");
103 memset(&def_p_conf, 0, sizeof(struct rte_event_port_conf));
104 rte_event_port_default_conf_get(event_d_id, 0, &def_p_conf);
106 if (def_p_conf.new_event_threshold < event_p_conf.new_event_threshold)
107 event_p_conf.new_event_threshold =
108 def_p_conf.new_event_threshold;
110 if (def_p_conf.dequeue_depth < event_p_conf.dequeue_depth)
111 event_p_conf.dequeue_depth = def_p_conf.dequeue_depth;
113 if (def_p_conf.enqueue_depth < event_p_conf.enqueue_depth)
114 event_p_conf.enqueue_depth = def_p_conf.enqueue_depth;
116 event_p_conf.disable_implicit_release =
117 evt_rsrc->disable_implicit_release;
118 evt_rsrc->deq_depth = def_p_conf.dequeue_depth;
120 for (event_p_id = 0; event_p_id < evt_rsrc->evp.nb_ports;
122 ret = rte_event_port_setup(event_d_id, event_p_id,
125 rte_panic("Error in configuring event port %d\n",
128 ret = rte_event_port_link(event_d_id, event_p_id,
129 evt_rsrc->evq.event_q_id,
131 evt_rsrc->evq.nb_queues - 1);
132 if (ret != (evt_rsrc->evq.nb_queues - 1))
133 rte_panic("Error in linking event port %d to queues\n",
135 evt_rsrc->evp.event_p_id[event_p_id] = event_p_id;
138 rte_spinlock_init(&evt_rsrc->evp.lock);
140 evt_rsrc->def_p_conf = event_p_conf;
144 l3fwd_event_queue_setup_generic(uint32_t event_queue_cfg)
146 struct l3fwd_event_resources *evt_rsrc = l3fwd_get_eventdev_rsrc();
147 uint8_t event_d_id = evt_rsrc->event_d_id;
148 struct rte_event_queue_conf event_q_conf = {
149 .nb_atomic_flows = 1024,
150 .nb_atomic_order_sequences = 1024,
151 .event_queue_cfg = event_queue_cfg,
152 .priority = RTE_EVENT_DEV_PRIORITY_NORMAL
154 struct rte_event_queue_conf def_q_conf;
158 event_q_conf.schedule_type = evt_rsrc->sched_type;
159 evt_rsrc->evq.event_q_id = (uint8_t *)malloc(sizeof(uint8_t) *
160 evt_rsrc->evq.nb_queues);
161 if (!evt_rsrc->evq.event_q_id)
162 rte_panic("Memory allocation failure\n");
164 rte_event_queue_default_conf_get(event_d_id, 0, &def_q_conf);
165 if (def_q_conf.nb_atomic_flows < event_q_conf.nb_atomic_flows)
166 event_q_conf.nb_atomic_flows = def_q_conf.nb_atomic_flows;
168 for (event_q_id = 0; event_q_id < (evt_rsrc->evq.nb_queues - 1);
170 ret = rte_event_queue_setup(event_d_id, event_q_id,
173 rte_panic("Error in configuring event queue\n");
174 evt_rsrc->evq.event_q_id[event_q_id] = event_q_id;
177 event_q_conf.event_queue_cfg |= RTE_EVENT_QUEUE_CFG_SINGLE_LINK;
178 event_q_conf.priority = RTE_EVENT_DEV_PRIORITY_HIGHEST,
179 ret = rte_event_queue_setup(event_d_id, event_q_id, &event_q_conf);
181 rte_panic("Error in configuring event queue for Tx adapter\n");
182 evt_rsrc->evq.event_q_id[event_q_id] = event_q_id;
186 l3fwd_event_set_generic_ops(struct l3fwd_event_setup_ops *ops)
188 ops->event_device_setup = l3fwd_event_device_setup_generic;
189 ops->event_queue_setup = l3fwd_event_queue_setup_generic;
190 ops->event_port_setup = l3fwd_event_port_setup_generic;