4 * Copyright(c) 2010-2012 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 * version: DPDK.L.1.2.3-3
40 #ifndef APP_MAX_SOCKETS
41 #define APP_MAX_SOCKETS 2
44 #ifndef APP_MAX_LCORES
45 #define APP_MAX_LCORES RTE_MAX_LCORE
48 #ifndef APP_MAX_NIC_PORTS
49 #define APP_MAX_NIC_PORTS RTE_MAX_ETHPORTS
52 #ifndef APP_MAX_RX_QUEUES_PER_NIC_PORT
53 #define APP_MAX_RX_QUEUES_PER_NIC_PORT 128
56 #ifndef APP_MAX_TX_QUEUES_PER_NIC_PORT
57 #define APP_MAX_TX_QUEUES_PER_NIC_PORT 128
60 #ifndef APP_MAX_IO_LCORES
61 #define APP_MAX_IO_LCORES 16
63 #if (APP_MAX_IO_LCORES > APP_MAX_LCORES)
64 #error "APP_MAX_IO_LCORES is too big"
67 #ifndef APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE
68 #define APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE 16
71 #ifndef APP_MAX_NIC_TX_PORTS_PER_IO_LCORE
72 #define APP_MAX_NIC_TX_PORTS_PER_IO_LCORE 16
74 #if (APP_MAX_NIC_TX_PORTS_PER_IO_LCORE > APP_MAX_NIC_PORTS)
75 #error "APP_MAX_NIC_TX_PORTS_PER_IO_LCORE too big"
78 #ifndef APP_MAX_WORKER_LCORES
79 #define APP_MAX_WORKER_LCORES 16
81 #if (APP_MAX_WORKER_LCORES > APP_MAX_LCORES)
82 #error "APP_MAX_WORKER_LCORES is too big"
87 #ifndef APP_DEFAULT_MBUF_SIZE
88 #define APP_DEFAULT_MBUF_SIZE (2048 + sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM)
91 #ifndef APP_DEFAULT_MEMPOOL_BUFFERS
92 #define APP_DEFAULT_MEMPOOL_BUFFERS 8192
95 #ifndef APP_DEFAULT_MEMPOOL_CACHE_SIZE
96 #define APP_DEFAULT_MEMPOOL_CACHE_SIZE 256
100 #ifndef APP_MAX_LPM_RULES
101 #define APP_MAX_LPM_RULES 1024
105 #ifndef APP_DEFAULT_NIC_RX_RING_SIZE
106 #define APP_DEFAULT_NIC_RX_RING_SIZE 1024
110 * RX and TX Prefetch, Host, and Write-back threshold values should be
111 * carefully set for optimal performance. Consult the network
112 * controller's datasheet and supporting DPDK documentation for guidance
113 * on how these parameters should be set.
115 #ifndef APP_DEFAULT_NIC_RX_PTHRESH
116 #define APP_DEFAULT_NIC_RX_PTHRESH 8
119 #ifndef APP_DEFAULT_NIC_RX_HTHRESH
120 #define APP_DEFAULT_NIC_RX_HTHRESH 8
123 #ifndef APP_DEFAULT_NIC_RX_WTHRESH
124 #define APP_DEFAULT_NIC_RX_WTHRESH 4
127 #ifndef APP_DEFAULT_NIC_RX_FREE_THRESH
128 #define APP_DEFAULT_NIC_RX_FREE_THRESH 64
132 #ifndef APP_DEFAULT_NIC_TX_RING_SIZE
133 #define APP_DEFAULT_NIC_TX_RING_SIZE 1024
137 * These default values are optimized for use with the Intel(R) 82599 10 GbE
138 * Controller and the DPDK ixgbe PMD. Consider using other values for other
139 * network controllers and/or network drivers.
141 #ifndef APP_DEFAULT_NIC_TX_PTHRESH
142 #define APP_DEFAULT_NIC_TX_PTHRESH 36
145 #ifndef APP_DEFAULT_NIC_TX_HTHRESH
146 #define APP_DEFAULT_NIC_TX_HTHRESH 0
149 #ifndef APP_DEFAULT_NIC_TX_WTHRESH
150 #define APP_DEFAULT_NIC_TX_WTHRESH 0
153 #ifndef APP_DEFAULT_NIC_TX_FREE_THRESH
154 #define APP_DEFAULT_NIC_TX_FREE_THRESH 0
157 #ifndef APP_DEFAULT_NIC_TX_RS_THRESH
158 #define APP_DEFAULT_NIC_TX_RS_THRESH 0
162 #ifndef APP_DEFAULT_RING_RX_SIZE
163 #define APP_DEFAULT_RING_RX_SIZE 1024
166 #ifndef APP_DEFAULT_RING_TX_SIZE
167 #define APP_DEFAULT_RING_TX_SIZE 1024
171 #ifndef APP_MBUF_ARRAY_SIZE
172 #define APP_MBUF_ARRAY_SIZE 512
175 #ifndef APP_DEFAULT_BURST_SIZE_IO_RX_READ
176 #define APP_DEFAULT_BURST_SIZE_IO_RX_READ 144
178 #if (APP_DEFAULT_BURST_SIZE_IO_RX_READ > APP_MBUF_ARRAY_SIZE)
179 #error "APP_DEFAULT_BURST_SIZE_IO_RX_READ is too big"
182 #ifndef APP_DEFAULT_BURST_SIZE_IO_RX_WRITE
183 #define APP_DEFAULT_BURST_SIZE_IO_RX_WRITE 144
185 #if (APP_DEFAULT_BURST_SIZE_IO_RX_WRITE > APP_MBUF_ARRAY_SIZE)
186 #error "APP_DEFAULT_BURST_SIZE_IO_RX_WRITE is too big"
189 #ifndef APP_DEFAULT_BURST_SIZE_IO_TX_READ
190 #define APP_DEFAULT_BURST_SIZE_IO_TX_READ 144
192 #if (APP_DEFAULT_BURST_SIZE_IO_TX_READ > APP_MBUF_ARRAY_SIZE)
193 #error "APP_DEFAULT_BURST_SIZE_IO_TX_READ is too big"
196 #ifndef APP_DEFAULT_BURST_SIZE_IO_TX_WRITE
197 #define APP_DEFAULT_BURST_SIZE_IO_TX_WRITE 144
199 #if (APP_DEFAULT_BURST_SIZE_IO_TX_WRITE > APP_MBUF_ARRAY_SIZE)
200 #error "APP_DEFAULT_BURST_SIZE_IO_TX_WRITE is too big"
203 #ifndef APP_DEFAULT_BURST_SIZE_WORKER_READ
204 #define APP_DEFAULT_BURST_SIZE_WORKER_READ 144
206 #if ((2 * APP_DEFAULT_BURST_SIZE_WORKER_READ) > APP_MBUF_ARRAY_SIZE)
207 #error "APP_DEFAULT_BURST_SIZE_WORKER_READ is too big"
210 #ifndef APP_DEFAULT_BURST_SIZE_WORKER_WRITE
211 #define APP_DEFAULT_BURST_SIZE_WORKER_WRITE 144
213 #if (APP_DEFAULT_BURST_SIZE_WORKER_WRITE > APP_MBUF_ARRAY_SIZE)
214 #error "APP_DEFAULT_BURST_SIZE_WORKER_WRITE is too big"
217 /* Load balancing logic */
218 #ifndef APP_DEFAULT_IO_RX_LB_POS
219 #define APP_DEFAULT_IO_RX_LB_POS 29
221 #if (APP_DEFAULT_IO_RX_LB_POS >= 64)
222 #error "APP_DEFAULT_IO_RX_LB_POS is too big"
225 struct app_mbuf_array {
226 struct rte_mbuf *array[APP_MBUF_ARRAY_SIZE];
230 enum app_lcore_type {
231 e_APP_LCORE_DISABLED = 0,
236 struct app_lcore_params_io {
243 } nic_queues[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];
244 uint32_t n_nic_queues;
247 struct rte_ring *rings[APP_MAX_WORKER_LCORES];
250 /* Internal buffers */
251 struct app_mbuf_array mbuf_in;
252 struct app_mbuf_array mbuf_out[APP_MAX_WORKER_LCORES];
253 uint8_t mbuf_out_flush[APP_MAX_WORKER_LCORES];
256 uint32_t nic_queues_count[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];
257 uint32_t nic_queues_iters[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];
258 uint32_t rings_count[APP_MAX_WORKER_LCORES];
259 uint32_t rings_iters[APP_MAX_WORKER_LCORES];
265 struct rte_ring *rings[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];
268 uint8_t nic_ports[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
269 uint32_t n_nic_ports;
271 /* Internal buffers */
272 struct app_mbuf_array mbuf_out[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
273 uint8_t mbuf_out_flush[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
276 uint32_t rings_count[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];
277 uint32_t rings_iters[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];
278 uint32_t nic_ports_count[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
279 uint32_t nic_ports_iters[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
283 struct app_lcore_params_worker {
285 struct rte_ring *rings_in[APP_MAX_IO_LCORES];
287 struct rte_ring *rings_out[APP_MAX_NIC_PORTS];
290 struct rte_lpm *lpm_table;
293 /* Internal buffers */
294 struct app_mbuf_array mbuf_in;
295 struct app_mbuf_array mbuf_out[APP_MAX_NIC_PORTS];
296 uint8_t mbuf_out_flush[APP_MAX_NIC_PORTS];
299 uint32_t rings_in_count[APP_MAX_IO_LCORES];
300 uint32_t rings_in_iters[APP_MAX_IO_LCORES];
301 uint32_t rings_out_count[APP_MAX_NIC_PORTS];
302 uint32_t rings_out_iters[APP_MAX_NIC_PORTS];
305 struct app_lcore_params {
307 struct app_lcore_params_io io;
308 struct app_lcore_params_worker worker;
310 enum app_lcore_type type;
311 struct rte_mempool *pool;
312 } __rte_cache_aligned;
314 struct app_lpm_rule {
322 struct app_lcore_params lcore_params[APP_MAX_LCORES];
325 uint8_t nic_rx_queue_mask[APP_MAX_NIC_PORTS][APP_MAX_RX_QUEUES_PER_NIC_PORT];
326 uint8_t nic_tx_port_mask[APP_MAX_NIC_PORTS];
329 struct rte_mempool *pools[APP_MAX_SOCKETS];
332 struct rte_lpm *lpm_tables[APP_MAX_SOCKETS];
333 struct app_lpm_rule lpm_rules[APP_MAX_LPM_RULES];
334 uint32_t n_lpm_rules;
337 uint32_t nic_rx_ring_size;
338 uint32_t nic_tx_ring_size;
339 uint32_t ring_rx_size;
340 uint32_t ring_tx_size;
343 uint32_t burst_size_io_rx_read;
344 uint32_t burst_size_io_rx_write;
345 uint32_t burst_size_io_tx_read;
346 uint32_t burst_size_io_tx_write;
347 uint32_t burst_size_worker_read;
348 uint32_t burst_size_worker_write;
352 } __rte_cache_aligned;
354 extern struct app_params app;
356 int app_parse_args(int argc, char **argv);
357 void app_print_usage(void);
359 int app_lcore_main_loop(void *arg);
361 int app_get_nic_rx_queues_per_port(uint8_t port);
362 int app_get_lcore_for_nic_rx(uint8_t port, uint8_t queue, uint32_t *lcore_out);
363 int app_get_lcore_for_nic_tx(uint8_t port, uint32_t *lcore_out);
364 int app_is_socket_used(uint32_t socket);
365 uint32_t app_get_lcores_io_rx(void);
366 uint32_t app_get_lcores_worker(void);
367 void app_print_params(void);
369 #ifdef RTE_EXEC_ENV_BAREMETAL
375 int MAIN(int argc, char **argv);
377 #endif /* _MAIN_H_ */