examples/performance-thread/common/arch/arm64/ctx.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Cavium, Inc
   3  */
   4
   5 #ifndef CTX_H
   6 #define CTX_H
   7
   8 #ifdef __cplusplus
   9 extern "C" {
  10 #endif
  11
  12 /*
  13  * CPU context registers
  14  */
  15 struct ctx {
  16         void    *sp;            /* 0  */
  17         void    *fp;            /* 8 */
  18         void    *lr;            /* 16  */
  19
  20         /* Callee Saved Generic Registers */
  21         void    *r19;           /* 24 */
  22         void    *r20;           /* 32 */
  23         void    *r21;           /* 40 */
  24         void    *r22;           /* 48 */
  25         void    *r23;           /* 56 */
  26         void    *r24;           /* 64 */
  27         void    *r25;           /* 72 */
  28         void    *r26;           /* 80 */
  29         void    *r27;           /* 88 */
  30         void    *r28;           /* 96 */
  31
  32         /*
  33          * Callee Saved SIMD Registers. Only the bottom 64-bits
  34          * of these registers needs to be saved.
  35          */
  36         void    *v8;            /* 104 */
  37         void    *v9;            /* 112 */
  38         void    *v10;           /* 120 */
  39         void    *v11;           /* 128 */
  40         void    *v12;           /* 136 */
  41         void    *v13;           /* 144 */
  42         void    *v14;           /* 152 */
  43         void    *v15;           /* 160 */
  44 };
  45
  46
  47 void
  48 ctx_switch(struct ctx *new_ctx, struct ctx *curr_ctx);
  49
  50
  51 #ifdef __cplusplus
  52 }
  53 #endif
  54
  55 #endif /* RTE_CTX_H_ */