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45 #include <rte_lcore.h>
46 #include <rte_string_fns.h>
50 #define APP_NAME "qos_sched"
51 #define MAX_OPT_VALUES 8
52 #define SYS_CPU_DIR "/sys/devices/system/cpu/cpu%u/topology/"
54 static uint32_t app_master_core = 1;
55 static uint32_t app_numa_mask;
56 static uint64_t app_used_core_mask = 0;
57 static uint64_t app_used_port_mask = 0;
58 static uint64_t app_used_rx_port_mask = 0;
59 static uint64_t app_used_tx_port_mask = 0;
62 static const char usage[] =
66 "Application mandatory parameters: \n"
67 " --pfc \"RX PORT, TX PORT, RX LCORE, WT LCORE\" : Packet flow configuration \n"
68 " multiple pfc can be configured in command line \n"
70 "Application optional parameters: \n"
71 " --i : run in interactive mode (default value is %u) \n"
72 " --mst I : master core index (default value is %u) \n"
73 " --rsz \"A, B, C\" : Ring sizes \n"
74 " A = Size (in number of buffer descriptors) of each of the NIC RX \n"
75 " rings read by the I/O RX lcores (default value is %u) \n"
76 " B = Size (in number of elements) of each of the SW rings used by the\n"
77 " I/O RX lcores to send packets to worker lcores (default value is\n"
79 " C = Size (in number of buffer descriptors) of each of the NIC TX \n"
80 " rings written by worker lcores (default value is %u) \n"
81 " --bsz \"A, B, C, D\": Burst sizes \n"
82 " A = I/O RX lcore read burst size from NIC RX (default value is %u) \n"
83 " B = I/O RX lcore write burst size to output SW rings, \n"
84 " Worker lcore read burst size from input SW rings, \n"
85 " QoS enqueue size (default value is %u) \n"
86 " C = QoS dequeue size (default value is %u) \n"
87 " D = Worker lcore write burst size to NIC TX (default value is %u) \n"
88 " --msz M : Mempool size (in number of mbufs) for each pfc (default %u) \n"
89 " --rth \"A, B, C\" : RX queue threshold parameters \n"
90 " A = RX prefetch threshold (default value is %u) \n"
91 " B = RX host threshold (default value is %u) \n"
92 " C = RX write-back threshold (default value is %u) \n"
93 " --tth \"A, B, C\" : TX queue threshold parameters \n"
94 " A = TX prefetch threshold (default value is %u) \n"
95 " B = TX host threshold (default value is %u) \n"
96 " C = TX write-back threshold (default value is %u) \n"
97 " --cfg FILE : profile configuration to load \n"
102 app_usage(const char *prgname)
104 printf(usage, prgname, APP_INTERACTIVE_DEFAULT, app_master_core,
105 APP_RX_DESC_DEFAULT, APP_RING_SIZE, APP_TX_DESC_DEFAULT,
106 MAX_PKT_RX_BURST, PKT_ENQUEUE, PKT_DEQUEUE,
107 MAX_PKT_TX_BURST, NB_MBUF,
108 RX_PTHRESH, RX_HTHRESH, RX_WTHRESH,
109 TX_PTHRESH, TX_HTHRESH, TX_WTHRESH
113 static inline int str_is(const char *str, const char *is)
115 return (strcmp(str, is) == 0);
118 /* returns core mask used by DPDK */
120 app_eal_core_mask(void)
124 struct rte_config *cfg = rte_eal_get_configuration();
126 for (i = 0; i < RTE_MAX_LCORE; i++) {
127 if (cfg->lcore_role[i] == ROLE_RTE)
131 cm |= (1ULL << cfg->master_lcore);
137 /* returns total number of cores presented in a system */
139 app_cpu_core_count(void)
145 for(i = 0; i < RTE_MAX_LCORE; i++) {
146 len = rte_snprintf(path, sizeof(path), SYS_CPU_DIR, i);
147 if (len <= 0 || (unsigned)len >= sizeof(path))
150 if (access(path, F_OK) == 0)
158 number of values parsed
162 app_parse_opt_vals(const char *conf_str, char separator, uint32_t n_vals, uint32_t *opt_vals)
165 uint32_t i, n_tokens;
166 char *tokens[MAX_OPT_VALUES];
168 if (conf_str == NULL || opt_vals == NULL || n_vals == 0 || n_vals > MAX_OPT_VALUES)
171 /* duplicate configuration string before splitting it to tokens */
172 string = strdup(conf_str);
176 n_tokens = rte_strsplit(string, strnlen(string, 32), tokens, n_vals, separator);
178 for(i = 0; i < n_tokens; i++) {
179 opt_vals[i] = (uint32_t)atol(tokens[i]);
188 app_parse_ring_conf(const char *conf_str)
193 ret = app_parse_opt_vals(conf_str, ',', 3, vals);
197 ring_conf.rx_size = vals[0];
198 ring_conf.ring_size = vals[1];
199 ring_conf.tx_size = vals[2];
205 app_parse_rth_conf(const char *conf_str)
210 ret = app_parse_opt_vals(conf_str, ',', 3, vals);
214 rx_thresh.pthresh = (uint8_t)vals[0];
215 rx_thresh.hthresh = (uint8_t)vals[1];
216 rx_thresh.wthresh = (uint8_t)vals[2];
222 app_parse_tth_conf(const char *conf_str)
227 ret = app_parse_opt_vals(conf_str, ',', 3, vals);
231 tx_thresh.pthresh = (uint8_t)vals[0];
232 tx_thresh.hthresh = (uint8_t)vals[1];
233 tx_thresh.wthresh = (uint8_t)vals[2];
239 app_parse_flow_conf(const char *conf_str)
243 struct flow_conf *pconf;
246 ret = app_parse_opt_vals(conf_str, ',', 6, vals);
247 if (ret < 4 || ret > 5)
250 pconf = &qos_conf[nb_pfc];
252 pconf->rx_port = (uint8_t)vals[0];
253 pconf->tx_port = (uint8_t)vals[1];
254 pconf->rx_core = (uint8_t)vals[2];
255 pconf->wt_core = (uint8_t)vals[3];
257 pconf->tx_core = (uint8_t)vals[4];
259 pconf->tx_core = pconf->wt_core;
261 if (pconf->rx_core == pconf->wt_core) {
262 RTE_LOG(ERR, APP, "pfc %u: rx thread and worker thread cannot share same core\n", nb_pfc);
266 if (pconf->rx_port >= RTE_MAX_ETHPORTS) {
267 RTE_LOG(ERR, APP, "pfc %u: invalid rx port %hu index\n", nb_pfc, pconf->rx_port);
270 if (pconf->tx_port >= RTE_MAX_ETHPORTS) {
271 RTE_LOG(ERR, APP, "pfc %u: invalid tx port %hu index\n", nb_pfc, pconf->rx_port);
275 mask = 1lu << pconf->rx_port;
276 if (app_used_rx_port_mask & mask) {
277 RTE_LOG(ERR, APP, "pfc %u: rx port %hu is used already\n", nb_pfc, pconf->rx_port);
280 app_used_rx_port_mask |= mask;
281 app_used_port_mask |= mask;
283 mask = 1lu << pconf->tx_port;
284 if (app_used_tx_port_mask & mask) {
285 RTE_LOG(ERR, APP, "pfc %u: port %hu is used already\n", nb_pfc, pconf->tx_port);
288 app_used_tx_port_mask |= mask;
289 app_used_port_mask |= mask;
291 mask = 1lu << pconf->rx_core;
292 app_used_core_mask |= mask;
294 mask = 1lu << pconf->wt_core;
295 app_used_core_mask |= mask;
297 mask = 1lu << pconf->tx_core;
298 app_used_core_mask |= mask;
306 app_parse_burst_conf(const char *conf_str)
311 ret = app_parse_opt_vals(conf_str, ',', 4, vals);
315 burst_conf.rx_burst = (uint16_t)vals[0];
316 burst_conf.ring_burst = (uint16_t)vals[1];
317 burst_conf.qos_dequeue = (uint16_t)vals[2];
318 burst_conf.tx_burst = (uint16_t)vals[3];
324 * Parses the argument given in the command line of the application,
325 * calculates mask for used cores and initializes EAL with calculated core mask
328 app_parse_args(int argc, char **argv)
333 char *prgname = argv[0];
334 uint32_t i, nb_lcores;
336 static struct option lgopts[] = {
348 /* initialize EAL first */
349 ret = rte_eal_init(argc, argv);
356 /* set en_US locale to print big numbers with ',' */
357 setlocale(LC_NUMERIC, "en_US.utf-8");
359 while ((opt = getopt_long(argc, argv, "i",
360 lgopts, &option_index)) != EOF) {
364 printf("Interactive-mode selected\n");
369 optname = lgopts[option_index].name;
370 if (str_is(optname, "pfc")) {
371 ret = app_parse_flow_conf(optarg);
373 RTE_LOG(ERR, APP, "Invalid pipe configuration %s\n", optarg);
378 if (str_is(optname, "mst")) {
379 app_master_core = (uint32_t)atoi(optarg);
382 if (str_is(optname, "rsz")) {
383 ret = app_parse_ring_conf(optarg);
385 RTE_LOG(ERR, APP, "Invalid ring configuration %s\n", optarg);
390 if (str_is(optname, "bsz")) {
391 ret = app_parse_burst_conf(optarg);
393 RTE_LOG(ERR, APP, "Invalid burst configuration %s\n", optarg);
398 if (str_is(optname, "msz")) {
399 mp_size = atoi(optarg);
401 RTE_LOG(ERR, APP, "Invalid mempool size %s\n", optarg);
406 if (str_is(optname, "rth")) {
407 ret = app_parse_rth_conf(optarg);
409 RTE_LOG(ERR, APP, "Invalid RX threshold configuration %s\n", optarg);
414 if (str_is(optname, "tth")) {
415 ret = app_parse_tth_conf(optarg);
417 RTE_LOG(ERR, APP, "Invalid TX threshold configuration %s\n", optarg);
422 if (str_is(optname, "cfg")) {
423 cfg_profile = optarg;
434 /* check master core index validity */
435 for(i = 0; i <= app_master_core; i++) {
436 if (app_used_core_mask & (1u << app_master_core)) {
437 RTE_LOG(ERR, APP, "Master core index is not configured properly\n");
442 app_used_core_mask |= 1u << app_master_core;
444 if ((app_used_core_mask != app_eal_core_mask()) ||
445 (app_master_core != rte_get_master_lcore())) {
446 RTE_LOG(ERR, APP, "EAL core mask not configured properly, must be %" PRIx64
447 " instead of %" PRIx64 "\n" , app_used_core_mask, app_eal_core_mask());
452 RTE_LOG(ERR, APP, "Packet flow not configured!\n");
457 /* sanity check for cores assignment */
458 nb_lcores = app_cpu_core_count();
460 for(i = 0; i < nb_pfc; i++) {
461 if (qos_conf[i].rx_core >= nb_lcores) {
462 RTE_LOG(ERR, APP, "pfc %u: invalid RX lcore index %u\n", i + 1,
463 qos_conf[i].rx_core);
466 if (qos_conf[i].wt_core >= nb_lcores) {
467 RTE_LOG(ERR, APP, "pfc %u: invalid WT lcore index %u\n", i + 1,
468 qos_conf[i].wt_core);
471 uint32_t rx_sock = rte_lcore_to_socket_id(qos_conf[i].rx_core);
472 uint32_t wt_sock = rte_lcore_to_socket_id(qos_conf[i].wt_core);
473 if (rx_sock != wt_sock) {
474 RTE_LOG(ERR, APP, "pfc %u: RX and WT must be on the same socket\n", i + 1);
477 app_numa_mask |= 1 << rte_lcore_to_socket_id(qos_conf[i].rx_core);