1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2014 Intel Corporation
16 #include <rte_lcore.h>
17 #include <rte_string_fns.h>
21 #define APP_NAME "qos_sched"
22 #define MAX_OPT_VALUES 8
23 #define SYS_CPU_DIR "/sys/devices/system/cpu/cpu%u/topology/"
25 static uint32_t app_main_core = 1;
26 static uint32_t app_numa_mask;
27 static uint64_t app_used_core_mask = 0;
28 static uint64_t app_used_port_mask = 0;
29 static uint64_t app_used_rx_port_mask = 0;
30 static uint64_t app_used_tx_port_mask = 0;
33 static const char usage[] =
37 "Application mandatory parameters: \n"
38 " --pfc \"RX PORT, TX PORT, RX LCORE, WT LCORE\" : Packet flow configuration \n"
39 " multiple pfc can be configured in command line \n"
41 "Application optional parameters: \n"
42 " -i : run in interactive mode (default value is %u) \n"
43 " --mnc I : main core index (default value is %u) \n"
44 " --rsz \"A, B, C\" : Ring sizes \n"
45 " A = Size (in number of buffer descriptors) of each of the NIC RX \n"
46 " rings read by the I/O RX lcores (default value is %u) \n"
47 " B = Size (in number of elements) of each of the SW rings used by the\n"
48 " I/O RX lcores to send packets to worker lcores (default value is\n"
50 " C = Size (in number of buffer descriptors) of each of the NIC TX \n"
51 " rings written by worker lcores (default value is %u) \n"
52 " --bsz \"A, B, C, D\": Burst sizes \n"
53 " A = I/O RX lcore read burst size from NIC RX (default value is %u) \n"
54 " B = I/O RX lcore write burst size to output SW rings, \n"
55 " Worker lcore read burst size from input SW rings, \n"
56 " QoS enqueue size (default value is %u) \n"
57 " C = QoS dequeue size (default value is %u) \n"
58 " D = Worker lcore write burst size to NIC TX (default value is %u) \n"
59 " --msz M : Mempool size (in number of mbufs) for each pfc (default %u) \n"
60 " --rth \"A, B, C\" : RX queue threshold parameters \n"
61 " A = RX prefetch threshold (default value is %u) \n"
62 " B = RX host threshold (default value is %u) \n"
63 " C = RX write-back threshold (default value is %u) \n"
64 " --tth \"A, B, C\" : TX queue threshold parameters \n"
65 " A = TX prefetch threshold (default value is %u) \n"
66 " B = TX host threshold (default value is %u) \n"
67 " C = TX write-back threshold (default value is %u) \n"
68 " --cfg FILE : profile configuration to load \n"
73 app_usage(const char *prgname)
75 printf(usage, prgname, APP_INTERACTIVE_DEFAULT, app_main_core,
76 APP_RX_DESC_DEFAULT, APP_RING_SIZE, APP_TX_DESC_DEFAULT,
77 MAX_PKT_RX_BURST, PKT_ENQUEUE, PKT_DEQUEUE,
78 MAX_PKT_TX_BURST, NB_MBUF,
79 RX_PTHRESH, RX_HTHRESH, RX_WTHRESH,
80 TX_PTHRESH, TX_HTHRESH, TX_WTHRESH
85 /* returns core mask used by DPDK */
87 app_eal_core_mask(void)
92 for (i = 0; i < APP_MAX_LCORE; i++) {
93 if (rte_lcore_has_role(i, ROLE_RTE))
97 cm |= (1ULL << rte_get_main_lcore());
103 /* returns total number of cores presented in a system */
105 app_cpu_core_count(void)
111 for (i = 0; i < APP_MAX_LCORE; i++) {
112 len = snprintf(path, sizeof(path), SYS_CPU_DIR, i);
113 if (len <= 0 || (unsigned)len >= sizeof(path))
116 if (access(path, F_OK) == 0)
124 number of values parsed
128 app_parse_opt_vals(const char *conf_str, char separator, uint32_t n_vals, uint32_t *opt_vals)
132 char *tokens[MAX_OPT_VALUES];
134 if (conf_str == NULL || opt_vals == NULL || n_vals == 0 || n_vals > MAX_OPT_VALUES)
137 /* duplicate configuration string before splitting it to tokens */
138 string = strdup(conf_str);
142 n_tokens = rte_strsplit(string, strnlen(string, 32), tokens, n_vals, separator);
144 if (n_tokens > MAX_OPT_VALUES)
147 for (i = 0; i < n_tokens; i++)
148 opt_vals[i] = (uint32_t)atol(tokens[i]);
156 app_parse_ring_conf(const char *conf_str)
161 ret = app_parse_opt_vals(conf_str, ',', 3, vals);
165 ring_conf.rx_size = vals[0];
166 ring_conf.ring_size = vals[1];
167 ring_conf.tx_size = vals[2];
173 app_parse_rth_conf(const char *conf_str)
178 ret = app_parse_opt_vals(conf_str, ',', 3, vals);
182 rx_thresh.pthresh = (uint8_t)vals[0];
183 rx_thresh.hthresh = (uint8_t)vals[1];
184 rx_thresh.wthresh = (uint8_t)vals[2];
190 app_parse_tth_conf(const char *conf_str)
195 ret = app_parse_opt_vals(conf_str, ',', 3, vals);
199 tx_thresh.pthresh = (uint8_t)vals[0];
200 tx_thresh.hthresh = (uint8_t)vals[1];
201 tx_thresh.wthresh = (uint8_t)vals[2];
207 app_parse_flow_conf(const char *conf_str)
211 struct flow_conf *pconf;
214 memset(vals, 0, sizeof(vals));
215 ret = app_parse_opt_vals(conf_str, ',', 6, vals);
216 if (ret < 4 || ret > 5)
219 pconf = &qos_conf[nb_pfc];
221 pconf->rx_port = vals[0];
222 pconf->tx_port = vals[1];
223 pconf->rx_core = (uint8_t)vals[2];
224 pconf->wt_core = (uint8_t)vals[3];
226 pconf->tx_core = (uint8_t)vals[4];
228 pconf->tx_core = pconf->wt_core;
230 if (pconf->rx_core == pconf->wt_core) {
231 RTE_LOG(ERR, APP, "pfc %u: rx thread and worker thread cannot share same core\n", nb_pfc);
235 if (pconf->rx_port >= RTE_MAX_ETHPORTS) {
236 RTE_LOG(ERR, APP, "pfc %u: invalid rx port %"PRIu16" index\n",
237 nb_pfc, pconf->rx_port);
240 if (pconf->tx_port >= RTE_MAX_ETHPORTS) {
241 RTE_LOG(ERR, APP, "pfc %u: invalid tx port %"PRIu16" index\n",
242 nb_pfc, pconf->tx_port);
246 mask = 1lu << pconf->rx_port;
247 if (app_used_rx_port_mask & mask) {
248 RTE_LOG(ERR, APP, "pfc %u: rx port %"PRIu16" is used already\n",
249 nb_pfc, pconf->rx_port);
252 app_used_rx_port_mask |= mask;
253 app_used_port_mask |= mask;
255 mask = 1lu << pconf->tx_port;
256 if (app_used_tx_port_mask & mask) {
257 RTE_LOG(ERR, APP, "pfc %u: port %"PRIu16" is used already\n",
258 nb_pfc, pconf->tx_port);
261 app_used_tx_port_mask |= mask;
262 app_used_port_mask |= mask;
264 mask = 1lu << pconf->rx_core;
265 app_used_core_mask |= mask;
267 mask = 1lu << pconf->wt_core;
268 app_used_core_mask |= mask;
270 mask = 1lu << pconf->tx_core;
271 app_used_core_mask |= mask;
279 app_parse_burst_conf(const char *conf_str)
284 ret = app_parse_opt_vals(conf_str, ',', 4, vals);
288 burst_conf.rx_burst = (uint16_t)vals[0];
289 burst_conf.ring_burst = (uint16_t)vals[1];
290 burst_conf.qos_dequeue = (uint16_t)vals[2];
291 burst_conf.tx_burst = (uint16_t)vals[3];
297 #define OPT_PFC "pfc"
299 #define OPT_MNC "mnc"
301 #define OPT_RSZ "rsz"
303 #define OPT_BSZ "bsz"
305 #define OPT_MSZ "msz"
307 #define OPT_RTH "rth"
309 #define OPT_TTH "tth"
311 #define OPT_CFG "cfg"
316 * Parses the argument given in the command line of the application,
317 * calculates mask for used cores and initializes EAL with calculated core mask
320 app_parse_args(int argc, char **argv)
324 char *prgname = argv[0];
325 uint32_t i, nb_lcores;
327 static struct option lgopts[] = {
328 {OPT_PFC, 1, NULL, OPT_PFC_NUM},
329 {OPT_MNC, 1, NULL, OPT_MNC_NUM},
330 {OPT_RSZ, 1, NULL, OPT_RSZ_NUM},
331 {OPT_BSZ, 1, NULL, OPT_BSZ_NUM},
332 {OPT_MSZ, 1, NULL, OPT_MSZ_NUM},
333 {OPT_RTH, 1, NULL, OPT_RTH_NUM},
334 {OPT_TTH, 1, NULL, OPT_TTH_NUM},
335 {OPT_CFG, 1, NULL, OPT_CFG_NUM},
339 /* initialize EAL first */
340 ret = rte_eal_init(argc, argv);
347 /* set en_US locale to print big numbers with ',' */
348 setlocale(LC_NUMERIC, "en_US.utf-8");
350 while ((opt = getopt_long(argc, argv, "i",
351 lgopts, &option_index)) != EOF) {
355 printf("Interactive-mode selected\n");
361 ret = app_parse_flow_conf(optarg);
363 RTE_LOG(ERR, APP, "Invalid pipe configuration %s\n",
370 app_main_core = (uint32_t)atoi(optarg);
374 ret = app_parse_ring_conf(optarg);
376 RTE_LOG(ERR, APP, "Invalid ring configuration %s\n",
383 ret = app_parse_burst_conf(optarg);
385 RTE_LOG(ERR, APP, "Invalid burst configuration %s\n",
392 mp_size = atoi(optarg);
394 RTE_LOG(ERR, APP, "Invalid mempool size %s\n",
401 ret = app_parse_rth_conf(optarg);
403 RTE_LOG(ERR, APP, "Invalid RX threshold configuration %s\n",
410 ret = app_parse_tth_conf(optarg);
412 RTE_LOG(ERR, APP, "Invalid TX threshold configuration %s\n",
419 cfg_profile = optarg;
428 /* check main core index validity */
429 for (i = 0; i <= app_main_core; i++) {
430 if (app_used_core_mask & (1u << app_main_core)) {
431 RTE_LOG(ERR, APP, "Main core index is not configured properly\n");
436 app_used_core_mask |= 1u << app_main_core;
438 if ((app_used_core_mask != app_eal_core_mask()) ||
439 (app_main_core != rte_get_main_lcore())) {
440 RTE_LOG(ERR, APP, "EAL core mask not configured properly, must be %" PRIx64
441 " instead of %" PRIx64 "\n" , app_used_core_mask, app_eal_core_mask());
446 RTE_LOG(ERR, APP, "Packet flow not configured!\n");
451 /* sanity check for cores assignment */
452 nb_lcores = app_cpu_core_count();
454 for(i = 0; i < nb_pfc; i++) {
455 if (qos_conf[i].rx_core >= nb_lcores) {
456 RTE_LOG(ERR, APP, "pfc %u: invalid RX lcore index %u\n", i + 1,
457 qos_conf[i].rx_core);
460 if (qos_conf[i].wt_core >= nb_lcores) {
461 RTE_LOG(ERR, APP, "pfc %u: invalid WT lcore index %u\n", i + 1,
462 qos_conf[i].wt_core);
465 uint32_t rx_sock = rte_lcore_to_socket_id(qos_conf[i].rx_core);
466 uint32_t wt_sock = rte_lcore_to_socket_id(qos_conf[i].wt_core);
467 if (rx_sock != wt_sock) {
468 RTE_LOG(ERR, APP, "pfc %u: RX and WT must be on the same socket\n", i + 1);
471 app_numa_mask |= 1 << rte_lcore_to_socket_id(qos_conf[i].rx_core);