2 ******************************************************************************
3 * @file system_stm32f4xx.c
4 * @author MCD Application Team
6 * @date 30-September-2011
7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
8 * This file contains the system clock configuration for STM32F4xx devices,
9 * and is generated by the clock configuration tool
10 * stm32f4xx_Clock_Configuration_V1.0.0.xls
12 * 1. This file provides two functions and one global variable to be called from
14 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
15 * and Divider factors, AHB/APBx prescalers and Flash settings),
16 * depending on the configuration made in the clock xls tool.
17 * This function is called at startup just after reset and
18 * before branch to main program. This call is made inside
19 * the "startup_stm32f4xx.s" file.
21 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
22 * by the user application to setup the SysTick
23 * timer or configure other parameters.
25 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
26 * be called whenever the core clock is changed
27 * during program execution.
29 * 2. After each device reset the HSI (16 MHz) is used as system clock source.
30 * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
31 * configure the system clock before to branch to main program.
33 * 3. If the system clock source selected by user fails to startup, the SystemInit()
34 * function will do nothing and HSI still used as system clock source. User can
35 * add some code to deal with this issue inside the SetSysClock() function.
37 * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
38 * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
39 * through PLL, and you are using different crystal you have to adapt the HSE
40 * value to your own configuration.
42 * 5. This file configures the system clock as follows:
43 *=============================================================================
44 *=============================================================================
45 * Supported STM32F4xx device revision | Rev A
46 *-----------------------------------------------------------------------------
47 * System Clock source | PLL (HSE)
48 *-----------------------------------------------------------------------------
49 * SYSCLK(Hz) | 168000000
50 *-----------------------------------------------------------------------------
51 * HCLK(Hz) | 168000000
52 *-----------------------------------------------------------------------------
54 *-----------------------------------------------------------------------------
56 *-----------------------------------------------------------------------------
58 *-----------------------------------------------------------------------------
59 * HSE Frequency(Hz) | 25000000
60 *-----------------------------------------------------------------------------
62 *-----------------------------------------------------------------------------
64 *-----------------------------------------------------------------------------
66 *-----------------------------------------------------------------------------
68 *-----------------------------------------------------------------------------
70 *-----------------------------------------------------------------------------
72 *-----------------------------------------------------------------------------
73 * I2S input clock | NA
74 *-----------------------------------------------------------------------------
76 *-----------------------------------------------------------------------------
77 * Main regulator output voltage | Scale1 mode
78 *-----------------------------------------------------------------------------
79 * Flash Latency(WS) | 5
80 *-----------------------------------------------------------------------------
81 * Prefetch Buffer | OFF
82 *-----------------------------------------------------------------------------
83 * Instruction cache | ON
84 *-----------------------------------------------------------------------------
86 *-----------------------------------------------------------------------------
87 * Require 48MHz for USB OTG FS, | Enabled
88 * SDIO and RNG clock |
89 *-----------------------------------------------------------------------------
90 *=============================================================================
91 ******************************************************************************
94 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
95 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
96 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
97 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
98 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
99 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
101 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
102 ******************************************************************************
105 /** @addtogroup CMSIS
109 /** @addtogroup stm32f4xx_system
113 /** @addtogroup STM32F4xx_System_Private_Includes
117 #include "stm32f4xx.h"
123 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
131 /** @addtogroup STM32F4xx_System_Private_Defines
135 /************************* Miscellaneous Configuration ************************/
136 /*!< Uncomment the following line if you need to use external SRAM mounted
137 on STM324xG_EVAL board as data memory */
138 /* #define DATA_IN_ExtSRAM */
140 /*!< Uncomment the following line if you need to relocate your vector Table in
142 /* #define VECT_TAB_SRAM */
143 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
144 This value must be a multiple of 0x200. */
145 /******************************************************************************/
147 /************************* PLL Parameters *************************************/
148 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
152 /* SYSCLK = PLL_VCO / PLL_P */
155 /* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
158 /******************************************************************************/
164 /** @addtogroup STM32F4xx_System_Private_Macros
172 /** @addtogroup STM32F4xx_System_Private_Variables
176 uint32_t SystemCoreClock = 168000000;
178 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
184 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
188 static void SetSysClock(void);
189 #ifdef DATA_IN_ExtSRAM
190 static void SystemInit_ExtMemCtl(void);
191 #endif /* DATA_IN_ExtSRAM */
197 /** @addtogroup STM32F4xx_System_Private_Functions
202 * @brief Setup the microcontroller system
203 * Initialize the Embedded Flash Interface, the PLL and update the
204 * SystemFrequency variable.
208 void SystemInit(void)
210 /* FPU settings ------------------------------------------------------------*/
211 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
212 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
215 /* Reset the RCC clock configuration to the default reset state ------------*/
217 RCC->CR |= (uint32_t)0x00000001;
219 /* Reset CFGR register */
220 RCC->CFGR = 0x00000000;
222 /* Reset HSEON, CSSON and PLLON bits */
223 RCC->CR &= (uint32_t)0xFEF6FFFF;
225 /* Reset PLLCFGR register */
226 RCC->PLLCFGR = 0x24003010;
228 /* Reset HSEBYP bit */
229 RCC->CR &= (uint32_t)0xFFFBFFFF;
231 /* Disable all interrupts */
232 RCC->CIR = 0x00000000;
234 #ifdef DATA_IN_ExtSRAM
235 SystemInit_ExtMemCtl();
236 #endif /* DATA_IN_ExtSRAM */
238 /* Configure the System clock source, PLL Multiplier and Divider factors,
239 AHB/APBx prescalers and Flash settings ----------------------------------*/
242 /* Configure the Vector Table location add offset address ------------------*/
244 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
246 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
251 * @brief Update SystemCoreClock variable according to Clock Register Values.
252 * The SystemCoreClock variable contains the core clock (HCLK), it can
253 * be used by the user application to setup the SysTick timer or configure
256 * @note Each time the core clock (HCLK) changes, this function must be called
257 * to update SystemCoreClock variable value. Otherwise, any configuration
258 * based on this variable will be incorrect.
260 * @note - The system frequency computed by this function is not the real
261 * frequency in the chip. It is calculated based on the predefined
262 * constant and the selected clock source:
264 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
266 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
268 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
269 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
271 * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
272 * 16 MHz) but the real value may vary depending on the variations
273 * in voltage and temperature.
275 * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
276 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
277 * frequency of the crystal used. Otherwise, this function may
280 * - The result of this function could be not correct when using fractional
281 * value for HSE crystal.
286 void SystemCoreClockUpdate(void)
288 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
290 /* Get SYSCLK source -------------------------------------------------------*/
291 tmp = RCC->CFGR & RCC_CFGR_SWS;
295 case 0x00: /* HSI used as system clock source */
296 SystemCoreClock = HSI_VALUE;
298 case 0x04: /* HSE used as system clock source */
299 SystemCoreClock = HSE_VALUE;
301 case 0x08: /* PLL used as system clock source */
303 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
304 SYSCLK = PLL_VCO / PLL_P
306 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
307 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
311 /* HSE used as PLL clock source */
312 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
316 /* HSI used as PLL clock source */
317 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
320 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
321 SystemCoreClock = pllvco/pllp;
324 SystemCoreClock = HSI_VALUE;
327 /* Compute HCLK frequency --------------------------------------------------*/
328 /* Get HCLK prescaler */
329 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
331 SystemCoreClock >>= tmp;
335 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
336 * AHB/APBx prescalers and Flash settings
337 * @Note This function should be called only once the RCC clock configuration
338 * is reset to the default reset state (done in SystemInit() function).
342 static void SetSysClock(void)
344 /******************************************************************************/
345 /* PLL (clocked by HSE) used as System clock source */
346 /******************************************************************************/
347 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
350 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
352 /* Wait till HSE is ready and if Time out is reached exit */
355 HSEStatus = RCC->CR & RCC_CR_HSERDY;
357 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
359 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
361 HSEStatus = (uint32_t)0x01;
365 HSEStatus = (uint32_t)0x00;
368 if (HSEStatus == (uint32_t)0x01)
370 /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
371 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
372 PWR->CR |= PWR_CR_VOS;
374 /* HCLK = SYSCLK / 1*/
375 RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
377 /* PCLK2 = HCLK / 2*/
378 RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
380 /* PCLK1 = HCLK / 4*/
381 RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
383 /* Configure the main PLL */
384 RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
385 (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
387 /* Enable the main PLL */
388 RCC->CR |= RCC_CR_PLLON;
390 /* Wait till the main PLL is ready */
391 while((RCC->CR & RCC_CR_PLLRDY) == 0)
395 /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
396 FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
398 /* Select the main PLL as system clock source */
399 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
400 RCC->CFGR |= RCC_CFGR_SW_PLL;
402 /* Wait till the main PLL is used as system clock source */
403 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
408 { /* If HSE fails to start-up, the application will have wrong clock
409 configuration. User can add here some code to deal with this error */
415 * @brief Setup the external memory controller. Called in startup_stm32f4xx.s
416 * before jump to __main
420 #ifdef DATA_IN_ExtSRAM
422 * @brief Setup the external memory controller.
423 * Called in startup_stm32f4xx.s before jump to main.
424 * This function configures the external SRAM mounted on STM324xG_EVAL board
425 * This SRAM will be used as program data memory (including heap and stack).
429 void SystemInit_ExtMemCtl(void)
431 /*-- GPIOs Configuration -----------------------------------------------------*/
433 +-------------------+--------------------+------------------+------------------+
434 + SRAM pins assignment +
435 +-------------------+--------------------+------------------+------------------+
436 | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
437 | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
438 | PD4 <-> FSMC_NOE | PE3 <-> FSMC_A19 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
439 | PD5 <-> FSMC_NWE | PE4 <-> FSMC_A20 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
440 | PD8 <-> FSMC_D13 | PE7 <-> FSMC_D4 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
441 | PD9 <-> FSMC_D14 | PE8 <-> FSMC_D5 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
442 | PD10 <-> FSMC_D15 | PE9 <-> FSMC_D6 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
443 | PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7 | PF13 <-> FSMC_A7 |------------------+
444 | PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8 | PF14 <-> FSMC_A8 |
445 | PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9 | PF15 <-> FSMC_A9 |
446 | PD14 <-> FSMC_D0 | PE13 <-> FSMC_D10 |------------------+
447 | PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 |
448 | | PE15 <-> FSMC_D12 |
449 +-------------------+--------------------+
451 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
452 RCC->AHB1ENR = 0x00000078;
454 /* Connect PDx pins to FSMC Alternate function */
455 GPIOD->AFR[0] = 0x00cc00cc;
456 GPIOD->AFR[1] = 0xcc0ccccc;
457 /* Configure PDx pins in Alternate function mode */
458 GPIOD->MODER = 0xaaaa0a0a;
459 /* Configure PDx pins speed to 100 MHz */
460 GPIOD->OSPEEDR = 0xffff0f0f;
461 /* Configure PDx pins Output type to push-pull */
462 GPIOD->OTYPER = 0x00000000;
463 /* No pull-up, pull-down for PDx pins */
464 GPIOD->PUPDR = 0x00000000;
466 /* Connect PEx pins to FSMC Alternate function */
467 GPIOE->AFR[0] = 0xc00cc0cc;
468 GPIOE->AFR[1] = 0xcccccccc;
469 /* Configure PEx pins in Alternate function mode */
470 GPIOE->MODER = 0xaaaa828a;
471 /* Configure PEx pins speed to 100 MHz */
472 GPIOE->OSPEEDR = 0xffffc3cf;
473 /* Configure PEx pins Output type to push-pull */
474 GPIOE->OTYPER = 0x00000000;
475 /* No pull-up, pull-down for PEx pins */
476 GPIOE->PUPDR = 0x00000000;
478 /* Connect PFx pins to FSMC Alternate function */
479 GPIOF->AFR[0] = 0x00cccccc;
480 GPIOF->AFR[1] = 0xcccc0000;
481 /* Configure PFx pins in Alternate function mode */
482 GPIOF->MODER = 0xaa000aaa;
483 /* Configure PFx pins speed to 100 MHz */
484 GPIOF->OSPEEDR = 0xff000fff;
485 /* Configure PFx pins Output type to push-pull */
486 GPIOF->OTYPER = 0x00000000;
487 /* No pull-up, pull-down for PFx pins */
488 GPIOF->PUPDR = 0x00000000;
490 /* Connect PGx pins to FSMC Alternate function */
491 GPIOG->AFR[0] = 0x00cccccc;
492 GPIOG->AFR[1] = 0x000000c0;
493 /* Configure PGx pins in Alternate function mode */
494 GPIOG->MODER = 0x00080aaa;
495 /* Configure PGx pins speed to 100 MHz */
496 GPIOG->OSPEEDR = 0x000c0fff;
497 /* Configure PGx pins Output type to push-pull */
498 GPIOG->OTYPER = 0x00000000;
499 /* No pull-up, pull-down for PGx pins */
500 GPIOG->PUPDR = 0x00000000;
502 /*-- FSMC Configuration ------------------------------------------------------*/
503 /* Enable the FSMC interface clock */
504 RCC->AHB3ENR = 0x00000001;
506 /* Configure and enable Bank1_SRAM2 */
507 FSMC_Bank1->BTCR[2] = 0x00001015;
508 FSMC_Bank1->BTCR[3] = 0x00010603;
509 FSMC_Bank1E->BWTR[2] = 0x0fffffff;
511 Bank1_SRAM2 is configured as follow:
513 p.FSMC_AddressSetupTime = 3;
514 p.FSMC_AddressHoldTime = 0;
515 p.FSMC_DataSetupTime = 6;
516 p.FSMC_BusTurnAroundDuration = 1;
517 p.FSMC_CLKDivision = 0;
518 p.FSMC_DataLatency = 0;
519 p.FSMC_AccessMode = FSMC_AccessMode_A;
521 FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
522 FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
523 FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
524 FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
525 FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
526 FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
527 FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
528 FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
529 FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
530 FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
531 FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
532 FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
533 FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
534 FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
535 FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
539 #endif /* DATA_IN_ExtSRAM */
553 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/