1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
9 #include "oob_monitor.h"
10 #include "power_manager.h"
11 #include "channel_manager.h"
13 static volatile unsigned run_loop = 1;
14 static uint64_t g_branches, g_branch_misses;
17 void branch_monitor_exit(void)
22 /* Number of microseconds between each poll */
24 #define PRINT_LOOP_COUNT (1000000/INTERVAL)
25 #define IA32_PERFEVTSEL0 0x186
26 #define IA32_PERFEVTSEL1 0x187
27 #define IA32_PERFCTR0 0xc1
28 #define IA32_PERFCTR1 0xc2
29 #define IA32_PERFEVT_BRANCH_HITS 0x05300c4
30 #define IA32_PERFEVT_BRANCH_MISS 0x05300c5
33 apply_policy(int core)
37 uint64_t branches, branch_misses;
38 uint64_t last_branches, last_branch_misses;
39 int64_t hits_diff, miss_diff;
46 last_branches = ci->cd[core].last_branches;
47 last_branch_misses = ci->cd[core].last_branch_misses;
49 ret = pread(ci->cd[core].msr_fd, &counter,
50 sizeof(counter), IA32_PERFCTR0);
52 RTE_LOG(ERR, POWER_MANAGER,
53 "unable to read counter for core %u\n",
58 ret = pread(ci->cd[core].msr_fd, &counter,
59 sizeof(counter), IA32_PERFCTR1);
61 RTE_LOG(ERR, POWER_MANAGER,
62 "unable to read counter for core %u\n",
64 branch_misses = counter;
67 ci->cd[core].last_branches = branches;
68 ci->cd[core].last_branch_misses = branch_misses;
71 * Intentional right shift to make MSB 0 to avoid
72 * possible signed overflow or truncation.
76 hits_diff = (int64_t)branches - (int64_t)last_branches;
78 /* Likely a counter overflow condition, skip this round */
83 * Intentional right shift to make MSB 0 to avoid
84 * possible signed overflow or truncation.
87 last_branch_misses >>= 1;
88 miss_diff = (int64_t)branch_misses - (int64_t)last_branch_misses;
90 /* Likely a counter overflow condition, skip this round */
94 g_branches = hits_diff;
95 g_branch_misses = miss_diff;
97 if (hits_diff < (INTERVAL*100)) {
98 /* Likely no workload running on this core. Skip. */
102 ratio = (float)miss_diff * (float)100 / (float)hits_diff;
104 if (ratio < ci->branch_ratio_threshold)
105 power_manager_scale_core_min(core);
107 power_manager_scale_core_max(core);
114 add_core_to_monitor(int core)
116 struct core_info *ci;
117 char proc_file[UNIX_PATH_MAX];
120 ci = get_core_info();
122 if (core < ci->core_count) {
125 snprintf(proc_file, UNIX_PATH_MAX, "/dev/cpu/%d/msr", core);
126 ci->cd[core].msr_fd = open(proc_file, O_RDWR | O_SYNC);
127 if (ci->cd[core].msr_fd < 0) {
128 RTE_LOG(ERR, POWER_MANAGER,
129 "Error opening MSR file for core %d "
130 "(is msr kernel module loaded?)\n",
135 * Set up branch counters
137 setup = IA32_PERFEVT_BRANCH_HITS;
138 ret = pwrite(ci->cd[core].msr_fd, &setup,
139 sizeof(setup), IA32_PERFEVTSEL0);
141 RTE_LOG(ERR, POWER_MANAGER,
142 "unable to set counter for core %u\n",
146 setup = IA32_PERFEVT_BRANCH_MISS;
147 ret = pwrite(ci->cd[core].msr_fd, &setup,
148 sizeof(setup), IA32_PERFEVTSEL1);
150 RTE_LOG(ERR, POWER_MANAGER,
151 "unable to set counter for core %u\n",
156 * Close the file and re-open as read only so
157 * as not to hog the resource
159 close(ci->cd[core].msr_fd);
160 ci->cd[core].msr_fd = open(proc_file, O_RDONLY);
161 if (ci->cd[core].msr_fd < 0) {
162 RTE_LOG(ERR, POWER_MANAGER,
163 "Error opening MSR file for core %d "
164 "(is msr kernel module loaded?)\n",
168 ci->cd[core].oob_enabled = 1;
174 remove_core_from_monitor(int core)
176 struct core_info *ci;
177 char proc_file[UNIX_PATH_MAX];
180 ci = get_core_info();
182 if (ci->cd[core].oob_enabled) {
186 * close the msr file, then reopen rw so we can
187 * disable the counters
189 if (ci->cd[core].msr_fd != 0)
190 close(ci->cd[core].msr_fd);
191 snprintf(proc_file, UNIX_PATH_MAX, "/dev/cpu/%d/msr", core);
192 ci->cd[core].msr_fd = open(proc_file, O_RDWR | O_SYNC);
193 if (ci->cd[core].msr_fd < 0) {
194 RTE_LOG(ERR, POWER_MANAGER,
195 "Error opening MSR file for core %d "
196 "(is msr kernel module loaded?)\n",
200 setup = 0x0; /* clear event */
201 ret = pwrite(ci->cd[core].msr_fd, &setup,
202 sizeof(setup), IA32_PERFEVTSEL0);
204 RTE_LOG(ERR, POWER_MANAGER,
205 "unable to set counter for core %u\n",
209 setup = 0x0; /* clear event */
210 ret = pwrite(ci->cd[core].msr_fd, &setup,
211 sizeof(setup), IA32_PERFEVTSEL1);
213 RTE_LOG(ERR, POWER_MANAGER,
214 "unable to set counter for core %u\n",
219 close(ci->cd[core].msr_fd);
220 ci->cd[core].msr_fd = 0;
221 ci->cd[core].oob_enabled = 0;
227 branch_monitor_init(void)
233 run_branch_monitor(void)
235 struct core_info *ci;
241 ci = get_core_info();
251 for (j = 0; j < ci->core_count; j++) {
252 if (ci->cd[j].oob_enabled) {
253 ratio = apply_policy(j);
254 if ((print > PRINT_LOOP_COUNT) && (g_active)) {
255 printf(" %d: %.4f {%lu} {%d}", j,
265 if (print > PRINT_LOOP_COUNT) {