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44 #include <sys/types.h>
46 #include <rte_config.h>
48 #include <rte_power.h>
49 #include <rte_spinlock.h>
51 #include "power_manager.h"
53 #define RTE_LOGTYPE_POWER_MANAGER RTE_LOGTYPE_USER1
55 #define POWER_SCALE_CORE(DIRECTION, core_num , ret) do { \
56 if (core_num >= POWER_MGR_MAX_CPUS) \
58 if (!(global_enabled_cpus & (1ULL << core_num))) \
60 rte_spinlock_lock(&global_core_freq_info[core_num].power_sl); \
61 ret = rte_power_freq_##DIRECTION(core_num); \
62 rte_spinlock_unlock(&global_core_freq_info[core_num].power_sl); \
65 #define POWER_SCALE_MASK(DIRECTION, core_mask, ret) do { \
67 for (i = 0; core_mask; core_mask &= ~(1 << i++)) { \
68 if ((core_mask >> i) & 1) { \
69 if (!(global_enabled_cpus & (1ULL << i))) \
71 rte_spinlock_lock(&global_core_freq_info[i].power_sl); \
72 if (rte_power_freq_##DIRECTION(i) != 1) \
74 rte_spinlock_unlock(&global_core_freq_info[i].power_sl); \
80 rte_spinlock_t power_sl;
81 uint32_t freqs[RTE_MAX_LCORE_FREQS];
83 } __rte_cache_aligned;
85 static struct freq_info global_core_freq_info[POWER_MGR_MAX_CPUS];
87 static uint64_t global_enabled_cpus;
89 #define SYSFS_CPU_PATH "/sys/devices/system/cpu/cpu%u/topology/core_id"
92 set_host_cpus_mask(void)
96 unsigned num_cpus = 0;
98 for (i = 0; i < POWER_MGR_MAX_CPUS; i++) {
99 snprintf(path, sizeof(path), SYSFS_CPU_PATH, i);
100 if (access(path, F_OK) == 0) {
101 global_enabled_cpus |= 1ULL << i;
110 power_manager_init(void)
112 unsigned i, num_cpus;
116 num_cpus = set_host_cpus_mask();
118 RTE_LOG(ERR, POWER_MANAGER, "Unable to detected host CPUs, please "
119 "ensure that sufficient privileges exist to inspect sysfs\n");
122 rte_power_set_env(PM_ENV_ACPI_CPUFREQ);
123 cpu_mask = global_enabled_cpus;
124 for (i = 0; cpu_mask; cpu_mask &= ~(1 << i++)) {
125 if (rte_power_init(i) < 0 || rte_power_freqs(i,
126 global_core_freq_info[i].freqs,
127 RTE_MAX_LCORE_FREQS) == 0) {
128 RTE_LOG(ERR, POWER_MANAGER, "Unable to initialize power manager "
130 global_enabled_cpus &= ~(1 << i);
134 rte_spinlock_init(&global_core_freq_info[i].power_sl);
136 RTE_LOG(INFO, POWER_MANAGER, "Detected %u host CPUs , enabled core mask:"
137 " 0x%"PRIx64"\n", num_cpus, global_enabled_cpus);
143 power_manager_get_current_frequency(unsigned core_num)
145 uint32_t freq, index;
147 if (core_num >= POWER_MGR_MAX_CPUS) {
148 RTE_LOG(ERR, POWER_MANAGER, "Core(%u) is out of range 0...%d\n",
149 core_num, POWER_MGR_MAX_CPUS-1);
152 if (!(global_enabled_cpus & (1ULL << core_num)))
155 rte_spinlock_lock(&global_core_freq_info[core_num].power_sl);
156 index = rte_power_get_freq(core_num);
157 rte_spinlock_unlock(&global_core_freq_info[core_num].power_sl);
158 if (index >= POWER_MGR_MAX_CPUS)
161 freq = global_core_freq_info[core_num].freqs[index];
167 power_manager_exit(void)
172 for (i = 0; global_enabled_cpus; global_enabled_cpus &= ~(1 << i++)) {
173 if (rte_power_exit(i) < 0) {
174 RTE_LOG(ERR, POWER_MANAGER, "Unable to shutdown power manager "
179 global_enabled_cpus = 0;
184 power_manager_scale_mask_up(uint64_t core_mask)
188 POWER_SCALE_MASK(up, core_mask, ret);
193 power_manager_scale_mask_down(uint64_t core_mask)
197 POWER_SCALE_MASK(down, core_mask, ret);
202 power_manager_scale_mask_min(uint64_t core_mask)
206 POWER_SCALE_MASK(min, core_mask, ret);
211 power_manager_scale_mask_max(uint64_t core_mask)
215 POWER_SCALE_MASK(max, core_mask, ret);
220 power_manager_scale_core_up(unsigned core_num)
224 POWER_SCALE_CORE(up, core_num, ret);
229 power_manager_scale_core_down(unsigned core_num)
233 POWER_SCALE_CORE(down, core_num, ret);
238 power_manager_scale_core_min(unsigned core_num)
242 POWER_SCALE_CORE(min, core_num, ret);
247 power_manager_scale_core_max(unsigned core_num)
251 POWER_SCALE_CORE(max, core_num, ret);