crypto/mlx5: add maximum segments configuration
[dpdk.git] / examples / vm_power_manager / power_manager.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2010-2014 Intel Corporation
3  */
4
5 #include <stdio.h>
6 #include <stdlib.h>
7 #include <stdint.h>
8 #include <inttypes.h>
9 #include <fcntl.h>
10 #include <unistd.h>
11 #include <dirent.h>
12 #include <errno.h>
13
14 #include <sys/sysinfo.h>
15 #include <sys/types.h>
16
17 #include <rte_log.h>
18 #include <rte_power.h>
19 #include <rte_spinlock.h>
20
21 #include "channel_manager.h"
22 #include "power_manager.h"
23 #include "oob_monitor.h"
24
25 #define POWER_SCALE_CORE(DIRECTION, core_num , ret) do { \
26         if (core_num >= ci.core_count) \
27                 return -1; \
28         if (!(ci.cd[core_num].global_enabled_cpus)) \
29                 return -1; \
30         rte_spinlock_lock(&global_core_freq_info[core_num].power_sl); \
31         ret = rte_power_freq_##DIRECTION(core_num); \
32         rte_spinlock_unlock(&global_core_freq_info[core_num].power_sl); \
33 } while (0)
34
35 struct freq_info {
36         rte_spinlock_t power_sl;
37         uint32_t freqs[RTE_MAX_LCORE_FREQS];
38         unsigned num_freqs;
39 } __rte_cache_aligned;
40
41 static struct freq_info global_core_freq_info[RTE_MAX_LCORE];
42
43 struct core_info ci;
44
45 #define SYSFS_CPU_PATH "/sys/devices/system/cpu/cpu%u/topology/core_id"
46
47 struct core_info *
48 get_core_info(void)
49 {
50         return &ci;
51 }
52
53 int
54 core_info_init(void)
55 {
56         struct core_info *ci;
57         int i;
58
59         ci = get_core_info();
60
61         ci->core_count = get_nprocs_conf();
62         ci->cd = malloc(ci->core_count * sizeof(struct core_details));
63         memset(ci->cd, 0, ci->core_count * sizeof(struct core_details));
64         if (!ci->cd) {
65                 RTE_LOG(ERR, POWER_MANAGER, "Failed to allocate memory for core info.");
66                 return -1;
67         }
68         for (i = 0; i < ci->core_count; i++) {
69                 ci->cd[i].global_enabled_cpus = 1;
70                 ci->cd[i].branch_ratio_threshold = BRANCH_RATIO_THRESHOLD;
71         }
72         printf("%d cores in system\n", ci->core_count);
73         return 0;
74 }
75
76 int
77 power_manager_init(void)
78 {
79         unsigned int i, num_cpus = 0, num_freqs = 0;
80         int ret = 0;
81         struct core_info *ci;
82         unsigned int max_core_num;
83
84         rte_power_set_env(PM_ENV_NOT_SET);
85
86         ci = get_core_info();
87         if (!ci) {
88                 RTE_LOG(ERR, POWER_MANAGER,
89                                 "Failed to get core info!\n");
90                 return -1;
91         }
92
93         if (ci->core_count > RTE_MAX_LCORE)
94                 max_core_num = RTE_MAX_LCORE;
95         else
96                 max_core_num = ci->core_count;
97
98         for (i = 0; i < max_core_num; i++) {
99                 if (rte_lcore_index(i) == -1)
100                         continue;
101
102                 if (ci->cd[i].global_enabled_cpus) {
103                         if (rte_power_init(i) < 0)
104                                 RTE_LOG(ERR, POWER_MANAGER,
105                                                 "Unable to initialize power manager "
106                                                 "for core %u\n", i);
107                         num_cpus++;
108                         num_freqs = rte_power_freqs(i,
109                                         global_core_freq_info[i].freqs,
110                                         RTE_MAX_LCORE_FREQS);
111                         if (num_freqs == 0) {
112                                 RTE_LOG(ERR, POWER_MANAGER,
113                                         "Unable to get frequency list for core %u\n",
114                                         i);
115                                 ci->cd[i].oob_enabled = 0;
116                                 ret = -1;
117                         }
118                         global_core_freq_info[i].num_freqs = num_freqs;
119
120                         rte_spinlock_init(&global_core_freq_info[i].power_sl);
121                 }
122                 if (ci->cd[i].oob_enabled)
123                         add_core_to_monitor(i);
124         }
125         RTE_LOG(INFO, POWER_MANAGER, "Managing %u cores out of %u available host cores\n",
126                         num_cpus, ci->core_count);
127         return ret;
128
129 }
130
131 uint32_t
132 power_manager_get_current_frequency(unsigned core_num)
133 {
134         uint32_t freq, index;
135
136         if (core_num >= RTE_MAX_LCORE) {
137                 RTE_LOG(ERR, POWER_MANAGER, "Core(%u) is out of range 0...%d\n",
138                                 core_num, RTE_MAX_LCORE-1);
139                 return -1;
140         }
141         if (!(ci.cd[core_num].global_enabled_cpus))
142                 return 0;
143
144         rte_spinlock_lock(&global_core_freq_info[core_num].power_sl);
145         index = rte_power_get_freq(core_num);
146         rte_spinlock_unlock(&global_core_freq_info[core_num].power_sl);
147         if (index >= RTE_MAX_LCORE_FREQS)
148                 freq = 0;
149         else
150                 freq = global_core_freq_info[core_num].freqs[index];
151
152         return freq;
153 }
154
155 int
156 power_manager_exit(void)
157 {
158         unsigned int i;
159         int ret = 0;
160         struct core_info *ci;
161         unsigned int max_core_num;
162
163         ci = get_core_info();
164         if (!ci) {
165                 RTE_LOG(ERR, POWER_MANAGER,
166                                 "Failed to get core info!\n");
167                 return -1;
168         }
169
170         if (ci->core_count > RTE_MAX_LCORE)
171                 max_core_num = RTE_MAX_LCORE;
172         else
173                 max_core_num = ci->core_count;
174
175         for (i = 0; i < max_core_num; i++) {
176                 if (rte_lcore_index(i) == -1)
177                         continue;
178
179                 if (ci->cd[i].global_enabled_cpus) {
180                         if (rte_power_exit(i) < 0) {
181                                 RTE_LOG(ERR, POWER_MANAGER, "Unable to shutdown power manager "
182                                                 "for core %u\n", i);
183                                 ret = -1;
184                         }
185                         ci->cd[i].global_enabled_cpus = 0;
186                 }
187                 remove_core_from_monitor(i);
188         }
189         return ret;
190 }
191
192 int
193 power_manager_scale_core_up(unsigned core_num)
194 {
195         int ret = 0;
196
197         POWER_SCALE_CORE(up, core_num, ret);
198         return ret;
199 }
200
201 int
202 power_manager_scale_core_down(unsigned core_num)
203 {
204         int ret = 0;
205
206         POWER_SCALE_CORE(down, core_num, ret);
207         return ret;
208 }
209
210 int
211 power_manager_scale_core_min(unsigned core_num)
212 {
213         int ret = 0;
214
215         POWER_SCALE_CORE(min, core_num, ret);
216         return ret;
217 }
218
219 int
220 power_manager_scale_core_max(unsigned core_num)
221 {
222         int ret = 0;
223
224         POWER_SCALE_CORE(max, core_num, ret);
225         return ret;
226 }
227
228 int
229 power_manager_enable_turbo_core(unsigned int core_num)
230 {
231         int ret = 0;
232
233         POWER_SCALE_CORE(enable_turbo, core_num, ret);
234         return ret;
235 }
236
237 int
238 power_manager_disable_turbo_core(unsigned int core_num)
239 {
240         int ret = 0;
241
242         POWER_SCALE_CORE(disable_turbo, core_num, ret);
243         return ret;
244 }
245
246 int
247 power_manager_scale_core_med(unsigned int core_num)
248 {
249         int ret = 0;
250         struct core_info *ci;
251
252         ci = get_core_info();
253         if (core_num >= RTE_MAX_LCORE)
254                 return -1;
255         if (!(ci->cd[core_num].global_enabled_cpus))
256                 return -1;
257         rte_spinlock_lock(&global_core_freq_info[core_num].power_sl);
258         ret = rte_power_set_freq(core_num,
259                                 global_core_freq_info[core_num].num_freqs / 2);
260         rte_spinlock_unlock(&global_core_freq_info[core_num].power_sl);
261         return ret;
262 }