1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2014 Intel Corporation
15 #include <sys/sysinfo.h>
16 #include <sys/types.h>
19 #include <rte_power.h>
20 #include <rte_spinlock.h>
22 #include "channel_manager.h"
23 #include "power_manager.h"
24 #include "oob_monitor.h"
26 #define POWER_SCALE_CORE(DIRECTION, core_num , ret) do { \
27 if (core_num >= ci.core_count) \
29 if (!(ci.cd[core_num].global_enabled_cpus)) \
31 rte_spinlock_lock(&global_core_freq_info[core_num].power_sl); \
32 ret = rte_power_freq_##DIRECTION(core_num); \
33 rte_spinlock_unlock(&global_core_freq_info[core_num].power_sl); \
36 #define POWER_SCALE_MASK(DIRECTION, core_mask, ret) do { \
38 for (i = 0; core_mask; core_mask &= ~(1 << i++)) { \
39 if ((core_mask >> i) & 1) { \
40 if (!(ci.cd[i].global_enabled_cpus)) \
42 rte_spinlock_lock(&global_core_freq_info[i].power_sl); \
43 if (rte_power_freq_##DIRECTION(i) != 1) \
45 rte_spinlock_unlock(&global_core_freq_info[i].power_sl); \
51 rte_spinlock_t power_sl;
52 uint32_t freqs[RTE_MAX_LCORE_FREQS];
54 } __rte_cache_aligned;
56 static struct freq_info global_core_freq_info[POWER_MGR_MAX_CPUS];
60 #define SYSFS_CPU_PATH "/sys/devices/system/cpu/cpu%u/topology/core_id"
76 ci->core_count = get_nprocs_conf();
77 ci->branch_ratio_threshold = BRANCH_RATIO_THRESHOLD;
78 ci->cd = malloc(ci->core_count * sizeof(struct core_details));
80 RTE_LOG(ERR, POWER_MANAGER, "Failed to allocate memory for core info.");
83 for (i = 0; i < ci->core_count; i++) {
84 ci->cd[i].global_enabled_cpus = 1;
85 ci->cd[i].oob_enabled = 0;
88 printf("%d cores in system\n", ci->core_count);
93 power_manager_init(void)
95 unsigned int i, num_cpus = 0, num_freqs = 0;
99 rte_power_set_env(PM_ENV_ACPI_CPUFREQ);
101 ci = get_core_info();
103 RTE_LOG(ERR, POWER_MANAGER,
104 "Failed to get core info!\n");
108 for (i = 0; i < ci->core_count; i++) {
109 if (ci->cd[i].global_enabled_cpus) {
110 if (rte_power_init(i) < 0)
111 RTE_LOG(ERR, POWER_MANAGER,
112 "Unable to initialize power manager "
115 num_freqs = rte_power_freqs(i,
116 global_core_freq_info[i].freqs,
117 RTE_MAX_LCORE_FREQS);
118 if (num_freqs == 0) {
119 RTE_LOG(ERR, POWER_MANAGER,
120 "Unable to get frequency list for core %u\n",
122 ci->cd[i].oob_enabled = 0;
125 global_core_freq_info[i].num_freqs = num_freqs;
127 rte_spinlock_init(&global_core_freq_info[i].power_sl);
129 if (ci->cd[i].oob_enabled)
130 add_core_to_monitor(i);
132 RTE_LOG(INFO, POWER_MANAGER, "Managing %u cores out of %u available host cores\n",
133 num_cpus, ci->core_count);
139 power_manager_get_current_frequency(unsigned core_num)
141 uint32_t freq, index;
143 if (core_num >= POWER_MGR_MAX_CPUS) {
144 RTE_LOG(ERR, POWER_MANAGER, "Core(%u) is out of range 0...%d\n",
145 core_num, POWER_MGR_MAX_CPUS-1);
148 if (!(ci.cd[core_num].global_enabled_cpus))
151 rte_spinlock_lock(&global_core_freq_info[core_num].power_sl);
152 index = rte_power_get_freq(core_num);
153 rte_spinlock_unlock(&global_core_freq_info[core_num].power_sl);
154 if (index >= POWER_MGR_MAX_CPUS)
157 freq = global_core_freq_info[core_num].freqs[index];
163 power_manager_exit(void)
167 struct core_info *ci;
169 ci = get_core_info();
171 RTE_LOG(ERR, POWER_MANAGER,
172 "Failed to get core info!\n");
176 for (i = 0; i < ci->core_count; i++) {
177 if (ci->cd[i].global_enabled_cpus) {
178 if (rte_power_exit(i) < 0) {
179 RTE_LOG(ERR, POWER_MANAGER, "Unable to shutdown power manager "
183 ci->cd[i].global_enabled_cpus = 0;
185 remove_core_from_monitor(i);
191 power_manager_scale_mask_up(uint64_t core_mask)
195 POWER_SCALE_MASK(up, core_mask, ret);
200 power_manager_scale_mask_down(uint64_t core_mask)
204 POWER_SCALE_MASK(down, core_mask, ret);
209 power_manager_scale_mask_min(uint64_t core_mask)
213 POWER_SCALE_MASK(min, core_mask, ret);
218 power_manager_scale_mask_max(uint64_t core_mask)
222 POWER_SCALE_MASK(max, core_mask, ret);
227 power_manager_enable_turbo_mask(uint64_t core_mask)
231 POWER_SCALE_MASK(enable_turbo, core_mask, ret);
236 power_manager_disable_turbo_mask(uint64_t core_mask)
240 POWER_SCALE_MASK(disable_turbo, core_mask, ret);
245 power_manager_scale_core_up(unsigned core_num)
249 POWER_SCALE_CORE(up, core_num, ret);
254 power_manager_scale_core_down(unsigned core_num)
258 POWER_SCALE_CORE(down, core_num, ret);
263 power_manager_scale_core_min(unsigned core_num)
267 POWER_SCALE_CORE(min, core_num, ret);
272 power_manager_scale_core_max(unsigned core_num)
276 POWER_SCALE_CORE(max, core_num, ret);
281 power_manager_enable_turbo_core(unsigned int core_num)
285 POWER_SCALE_CORE(enable_turbo, core_num, ret);
290 power_manager_disable_turbo_core(unsigned int core_num)
294 POWER_SCALE_CORE(disable_turbo, core_num, ret);
299 power_manager_scale_core_med(unsigned int core_num)
302 struct core_info *ci;
304 ci = get_core_info();
305 if (core_num >= POWER_MGR_MAX_CPUS)
307 if (!(ci->cd[core_num].global_enabled_cpus))
309 rte_spinlock_lock(&global_core_freq_info[core_num].power_sl);
310 ret = rte_power_set_freq(core_num,
311 global_core_freq_info[core_num].num_freqs / 2);
312 rte_spinlock_unlock(&global_core_freq_info[core_num].power_sl);