1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2014 Intel Corporation
15 #include <sys/sysinfo.h>
16 #include <sys/types.h>
19 #include <rte_power.h>
20 #include <rte_spinlock.h>
22 #include "channel_manager.h"
23 #include "power_manager.h"
24 #include "oob_monitor.h"
26 #define POWER_SCALE_CORE(DIRECTION, core_num , ret) do { \
27 if (core_num >= ci.core_count) \
29 if (!(ci.cd[core_num].global_enabled_cpus)) \
31 rte_spinlock_lock(&global_core_freq_info[core_num].power_sl); \
32 ret = rte_power_freq_##DIRECTION(core_num); \
33 rte_spinlock_unlock(&global_core_freq_info[core_num].power_sl); \
36 #define POWER_SCALE_MASK(DIRECTION, core_mask, ret) do { \
38 for (i = 0; core_mask; core_mask &= ~(1 << i++)) { \
39 if ((core_mask >> i) & 1) { \
40 if (!(ci.cd[i].global_enabled_cpus)) \
42 rte_spinlock_lock(&global_core_freq_info[i].power_sl); \
43 if (rte_power_freq_##DIRECTION(i) != 1) \
45 rte_spinlock_unlock(&global_core_freq_info[i].power_sl); \
51 rte_spinlock_t power_sl;
52 uint32_t freqs[RTE_MAX_LCORE_FREQS];
54 } __rte_cache_aligned;
56 static struct freq_info global_core_freq_info[POWER_MGR_MAX_CPUS];
60 #define SYSFS_CPU_PATH "/sys/devices/system/cpu/cpu%u/topology/core_id"
76 ci->core_count = get_nprocs_conf();
77 ci->branch_ratio_threshold = BRANCH_RATIO_THRESHOLD;
78 ci->cd = malloc(ci->core_count * sizeof(struct core_details));
80 RTE_LOG(ERR, POWER_MANAGER, "Failed to allocate memory for core info.");
83 for (i = 0; i < ci->core_count; i++) {
84 ci->cd[i].global_enabled_cpus = 1;
85 ci->cd[i].oob_enabled = 0;
88 printf("%d cores in system\n", ci->core_count);
93 power_manager_init(void)
95 unsigned int i, num_cpus = 0, num_freqs = 0;
98 unsigned int max_core_num;
100 rte_power_set_env(PM_ENV_ACPI_CPUFREQ);
102 ci = get_core_info();
104 RTE_LOG(ERR, POWER_MANAGER,
105 "Failed to get core info!\n");
109 if (ci->core_count > POWER_MGR_MAX_CPUS)
110 max_core_num = POWER_MGR_MAX_CPUS;
112 max_core_num = ci->core_count;
114 for (i = 0; i < max_core_num; i++) {
115 if (ci->cd[i].global_enabled_cpus) {
116 if (rte_power_init(i) < 0)
117 RTE_LOG(ERR, POWER_MANAGER,
118 "Unable to initialize power manager "
121 num_freqs = rte_power_freqs(i,
122 global_core_freq_info[i].freqs,
123 RTE_MAX_LCORE_FREQS);
124 if (num_freqs == 0) {
125 RTE_LOG(ERR, POWER_MANAGER,
126 "Unable to get frequency list for core %u\n",
128 ci->cd[i].oob_enabled = 0;
131 global_core_freq_info[i].num_freqs = num_freqs;
133 rte_spinlock_init(&global_core_freq_info[i].power_sl);
135 if (ci->cd[i].oob_enabled)
136 add_core_to_monitor(i);
138 RTE_LOG(INFO, POWER_MANAGER, "Managing %u cores out of %u available host cores\n",
139 num_cpus, ci->core_count);
145 power_manager_get_current_frequency(unsigned core_num)
147 uint32_t freq, index;
149 if (core_num >= POWER_MGR_MAX_CPUS) {
150 RTE_LOG(ERR, POWER_MANAGER, "Core(%u) is out of range 0...%d\n",
151 core_num, POWER_MGR_MAX_CPUS-1);
154 if (!(ci.cd[core_num].global_enabled_cpus))
157 rte_spinlock_lock(&global_core_freq_info[core_num].power_sl);
158 index = rte_power_get_freq(core_num);
159 rte_spinlock_unlock(&global_core_freq_info[core_num].power_sl);
160 if (index >= POWER_MGR_MAX_CPUS)
163 freq = global_core_freq_info[core_num].freqs[index];
169 power_manager_exit(void)
173 struct core_info *ci;
174 unsigned int max_core_num;
176 ci = get_core_info();
178 RTE_LOG(ERR, POWER_MANAGER,
179 "Failed to get core info!\n");
183 if (ci->core_count > POWER_MGR_MAX_CPUS)
184 max_core_num = POWER_MGR_MAX_CPUS;
186 max_core_num = ci->core_count;
188 for (i = 0; i < max_core_num; i++) {
189 if (ci->cd[i].global_enabled_cpus) {
190 if (rte_power_exit(i) < 0) {
191 RTE_LOG(ERR, POWER_MANAGER, "Unable to shutdown power manager "
195 ci->cd[i].global_enabled_cpus = 0;
197 remove_core_from_monitor(i);
203 power_manager_scale_mask_up(uint64_t core_mask)
207 POWER_SCALE_MASK(up, core_mask, ret);
212 power_manager_scale_mask_down(uint64_t core_mask)
216 POWER_SCALE_MASK(down, core_mask, ret);
221 power_manager_scale_mask_min(uint64_t core_mask)
225 POWER_SCALE_MASK(min, core_mask, ret);
230 power_manager_scale_mask_max(uint64_t core_mask)
234 POWER_SCALE_MASK(max, core_mask, ret);
239 power_manager_enable_turbo_mask(uint64_t core_mask)
243 POWER_SCALE_MASK(enable_turbo, core_mask, ret);
248 power_manager_disable_turbo_mask(uint64_t core_mask)
252 POWER_SCALE_MASK(disable_turbo, core_mask, ret);
257 power_manager_scale_core_up(unsigned core_num)
261 POWER_SCALE_CORE(up, core_num, ret);
266 power_manager_scale_core_down(unsigned core_num)
270 POWER_SCALE_CORE(down, core_num, ret);
275 power_manager_scale_core_min(unsigned core_num)
279 POWER_SCALE_CORE(min, core_num, ret);
284 power_manager_scale_core_max(unsigned core_num)
288 POWER_SCALE_CORE(max, core_num, ret);
293 power_manager_enable_turbo_core(unsigned int core_num)
297 POWER_SCALE_CORE(enable_turbo, core_num, ret);
302 power_manager_disable_turbo_core(unsigned int core_num)
306 POWER_SCALE_CORE(disable_turbo, core_num, ret);
311 power_manager_scale_core_med(unsigned int core_num)
314 struct core_info *ci;
316 ci = get_core_info();
317 if (core_num >= POWER_MGR_MAX_CPUS)
319 if (!(ci->cd[core_num].global_enabled_cpus))
321 rte_spinlock_lock(&global_core_freq_info[core_num].power_sl);
322 ret = rte_power_set_freq(core_num,
323 global_core_freq_info[core_num].num_freqs / 2);
324 rte_spinlock_unlock(&global_core_freq_info[core_num].power_sl);