1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
10 #define HNS3_CMDQ_TX_TIMEOUT 30000
11 #define HNS3_CMDQ_CLEAR_WAIT_TIME 200
12 #define HNS3_CMDQ_RX_INVLD_B 0
13 #define HNS3_CMDQ_RX_OUTVLD_B 1
14 #define HNS3_CMD_DESC_ALIGNMENT 4096
15 #define HNS3_CMD_FLAG_NEXT BIT(2)
19 #define HNS3_CMD_DESC_DATA_NUM 6
20 struct hns3_cmd_desc {
25 uint32_t data[HNS3_CMD_DESC_DATA_NUM];
28 struct hns3_cmq_ring {
29 uint64_t desc_dma_addr;
30 struct hns3_cmd_desc *desc;
34 uint16_t desc_num; /* max number of cmq descriptor */
36 uint32_t next_to_clean;
37 uint8_t ring_type; /* cmq ring type */
38 rte_spinlock_t lock; /* Command queue lock */
40 const void *zone; /* memory zone */
43 enum hns3_cmd_return_status {
44 HNS3_CMD_EXEC_SUCCESS = 0,
46 HNS3_CMD_NOT_SUPPORTED = 2,
47 HNS3_CMD_QUEUE_FULL = 3,
48 HNS3_CMD_NEXT_ERR = 4,
49 HNS3_CMD_UNEXE_ERR = 5,
50 HNS3_CMD_PARA_ERR = 6,
51 HNS3_CMD_RESULT_ERR = 7,
53 HNS3_CMD_HILINK_ERR = 9,
54 HNS3_CMD_QUEUE_ILLEGAL = 10,
55 HNS3_CMD_INVALID = 11,
56 HNS3_CMD_ROH_CHECK_FAIL = 12
59 enum hns3_cmd_status {
60 HNS3_STATUS_SUCCESS = 0,
61 HNS3_ERR_CSQ_FULL = -1,
62 HNS3_ERR_CSQ_TIMEOUT = -2,
63 HNS3_ERR_CSQ_ERROR = -3,
66 struct hns3_misc_vector {
72 struct hns3_cmq_ring csq;
73 struct hns3_cmq_ring crq;
75 enum hns3_cmd_status last_status;
78 enum hns3_opcode_type {
79 /* Generic commands */
80 HNS3_OPC_QUERY_FW_VER = 0x0001,
81 HNS3_OPC_CFG_RST_TRIGGER = 0x0020,
82 HNS3_OPC_GBL_RST_STATUS = 0x0021,
83 HNS3_OPC_QUERY_FUNC_STATUS = 0x0022,
84 HNS3_OPC_QUERY_PF_RSRC = 0x0023,
85 HNS3_OPC_QUERY_VF_RSRC = 0x0024,
86 HNS3_OPC_GET_CFG_PARAM = 0x0025,
87 HNS3_OPC_PF_RST_DONE = 0x0026,
89 HNS3_OPC_STATS_64_BIT = 0x0030,
90 HNS3_OPC_STATS_32_BIT = 0x0031,
91 HNS3_OPC_STATS_MAC = 0x0032,
92 HNS3_OPC_QUERY_MAC_REG_NUM = 0x0033,
93 HNS3_OPC_STATS_MAC_ALL = 0x0034,
95 HNS3_OPC_QUERY_REG_NUM = 0x0040,
96 HNS3_OPC_QUERY_32_BIT_REG = 0x0041,
97 HNS3_OPC_QUERY_64_BIT_REG = 0x0042,
98 HNS3_OPC_DFX_BD_NUM = 0x0043,
99 HNS3_OPC_DFX_BIOS_COMMON_REG = 0x0044,
100 HNS3_OPC_DFX_SSU_REG_0 = 0x0045,
101 HNS3_OPC_DFX_SSU_REG_1 = 0x0046,
102 HNS3_OPC_DFX_IGU_EGU_REG = 0x0047,
103 HNS3_OPC_DFX_RPU_REG_0 = 0x0048,
104 HNS3_OPC_DFX_RPU_REG_1 = 0x0049,
105 HNS3_OPC_DFX_NCSI_REG = 0x004A,
106 HNS3_OPC_DFX_RTC_REG = 0x004B,
107 HNS3_OPC_DFX_PPP_REG = 0x004C,
108 HNS3_OPC_DFX_RCB_REG = 0x004D,
109 HNS3_OPC_DFX_TQP_REG = 0x004E,
110 HNS3_OPC_DFX_SSU_REG_2 = 0x004F,
112 HNS3_OPC_QUERY_DEV_SPECS = 0x0050,
115 HNS3_OPC_CONFIG_MAC_MODE = 0x0301,
116 HNS3_OPC_QUERY_LINK_STATUS = 0x0307,
117 HNS3_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
118 HNS3_OPC_CONFIG_SPEED_DUP = 0x0309,
119 HNS3_OPC_QUERY_MAC_TNL_INT = 0x0310,
120 HNS3_OPC_MAC_TNL_INT_EN = 0x0311,
121 HNS3_OPC_CLEAR_MAC_TNL_INT = 0x0312,
122 HNS3_OPC_CONFIG_FEC_MODE = 0x031A,
124 /* PFC/Pause commands */
125 HNS3_OPC_CFG_MAC_PAUSE_EN = 0x0701,
126 HNS3_OPC_CFG_PFC_PAUSE_EN = 0x0702,
127 HNS3_OPC_CFG_MAC_PARA = 0x0703,
128 HNS3_OPC_CFG_PFC_PARA = 0x0704,
129 HNS3_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705,
130 HNS3_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706,
131 HNS3_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707,
132 HNS3_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708,
133 HNS3_OPC_PRI_TO_TC_MAPPING = 0x0709,
134 HNS3_OPC_QOS_MAP = 0x070A,
136 /* ETS/scheduler commands */
137 HNS3_OPC_TM_PG_TO_PRI_LINK = 0x0804,
138 HNS3_OPC_TM_QS_TO_PRI_LINK = 0x0805,
139 HNS3_OPC_TM_NQ_TO_QS_LINK = 0x0806,
140 HNS3_OPC_TM_RQ_TO_QS_LINK = 0x0807,
141 HNS3_OPC_TM_PORT_WEIGHT = 0x0808,
142 HNS3_OPC_TM_PG_WEIGHT = 0x0809,
143 HNS3_OPC_TM_QS_WEIGHT = 0x080A,
144 HNS3_OPC_TM_PRI_WEIGHT = 0x080B,
145 HNS3_OPC_TM_PRI_C_SHAPPING = 0x080C,
146 HNS3_OPC_TM_PRI_P_SHAPPING = 0x080D,
147 HNS3_OPC_TM_PG_C_SHAPPING = 0x080E,
148 HNS3_OPC_TM_PG_P_SHAPPING = 0x080F,
149 HNS3_OPC_TM_PORT_SHAPPING = 0x0810,
150 HNS3_OPC_TM_PG_SCH_MODE_CFG = 0x0812,
151 HNS3_OPC_TM_PRI_SCH_MODE_CFG = 0x0813,
152 HNS3_OPC_TM_QS_SCH_MODE_CFG = 0x0814,
153 HNS3_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
154 HNS3_OPC_ETS_TC_WEIGHT = 0x0843,
155 HNS3_OPC_QSET_DFX_STS = 0x0844,
156 HNS3_OPC_PRI_DFX_STS = 0x0845,
157 HNS3_OPC_PG_DFX_STS = 0x0846,
158 HNS3_OPC_PORT_DFX_STS = 0x0847,
159 HNS3_OPC_SCH_NQ_CNT = 0x0848,
160 HNS3_OPC_SCH_RQ_CNT = 0x0849,
161 HNS3_OPC_TM_INTERNAL_STS = 0x0850,
162 HNS3_OPC_TM_INTERNAL_CNT = 0x0851,
163 HNS3_OPC_TM_INTERNAL_STS_1 = 0x0852,
166 HNS3_OPC_MBX_VF_TO_PF = 0x2001,
168 /* Packet buffer allocate commands */
169 HNS3_OPC_TX_BUFF_ALLOC = 0x0901,
170 HNS3_OPC_RX_PRIV_BUFF_ALLOC = 0x0902,
171 HNS3_OPC_RX_PRIV_WL_ALLOC = 0x0903,
172 HNS3_OPC_RX_COM_THRD_ALLOC = 0x0904,
173 HNS3_OPC_RX_COM_WL_ALLOC = 0x0905,
175 /* TQP management command */
176 HNS3_OPC_SET_TQP_MAP = 0x0A01,
179 HNS3_OPC_QUERY_TX_STATUS = 0x0B03,
180 HNS3_OPC_QUERY_RX_STATUS = 0x0B13,
181 HNS3_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
182 HNS3_OPC_RESET_TQP_QUEUE = 0x0B22,
183 HNS3_OPC_RESET_TQP_QUEUE_INDEP = 0x0B23,
186 HNS3_OPC_TSO_GENERIC_CONFIG = 0x0C01,
187 HNS3_OPC_GRO_GENERIC_CONFIG = 0x0C10,
190 HNS3_OPC_RSS_GENERIC_CONFIG = 0x0D01,
191 HNS3_OPC_RSS_INPUT_TUPLE = 0x0D02,
192 HNS3_OPC_RSS_INDIR_TABLE = 0x0D07,
193 HNS3_OPC_RSS_TC_MODE = 0x0D08,
195 /* Promisuous mode command */
196 HNS3_OPC_CFG_PROMISC_MODE = 0x0E01,
198 /* Vlan offload commands */
199 HNS3_OPC_VLAN_PORT_TX_CFG = 0x0F01,
200 HNS3_OPC_VLAN_PORT_RX_CFG = 0x0F02,
203 HNS3_OPC_MAC_VLAN_ADD = 0x1000,
204 HNS3_OPC_MAC_VLAN_REMOVE = 0x1001,
205 HNS3_OPC_MAC_VLAN_TYPE_ID = 0x1002,
206 HNS3_OPC_MAC_VLAN_INSERT = 0x1003,
207 HNS3_OPC_MAC_VLAN_ALLOCATE = 0x1004,
208 HNS3_OPC_MAC_ETHTYPE_ADD = 0x1010,
211 HNS3_OPC_VLAN_FILTER_CTRL = 0x1100,
212 HNS3_OPC_VLAN_FILTER_PF_CFG = 0x1101,
213 HNS3_OPC_VLAN_FILTER_VF_CFG = 0x1102,
215 /* Flow Director command */
216 HNS3_OPC_FD_MODE_CTRL = 0x1200,
217 HNS3_OPC_FD_GET_ALLOCATION = 0x1201,
218 HNS3_OPC_FD_KEY_CONFIG = 0x1202,
219 HNS3_OPC_FD_TCAM_OP = 0x1203,
220 HNS3_OPC_FD_AD_OP = 0x1204,
221 HNS3_OPC_FD_COUNTER_OP = 0x1205,
223 /* Clear hardware state command */
224 HNS3_OPC_CLEAR_HW_STATE = 0x700B,
226 /* Firmware stats command */
227 HNS3_OPC_FIRMWARE_COMPAT_CFG = 0x701A,
228 /* Firmware control phy command */
229 HNS3_OPC_PHY_PARAM_CFG = 0x7025,
232 HNS3_OPC_GET_SFP_EEPROM = 0x7100,
233 HNS3_OPC_GET_SFP_EXIST = 0x7101,
234 HNS3_OPC_SFP_GET_SPEED = 0x7104,
236 /* Interrupts commands */
237 HNS3_OPC_ADD_RING_TO_VECTOR = 0x1503,
238 HNS3_OPC_DEL_RING_TO_VECTOR = 0x1504,
240 /* Error INT commands */
241 HNS3_OPC_MAC_COMMON_INT_EN = 0x030E,
242 HNS3_OPC_TM_SCH_ECC_INT_EN = 0x0829,
243 HNS3_OPC_SSU_ECC_INT_CMD = 0x0989,
244 HNS3_OPC_SSU_COMMON_INT_CMD = 0x098C,
245 HNS3_OPC_PPU_MPF_ECC_INT_CMD = 0x0B40,
246 HNS3_OPC_PPU_MPF_OTHER_INT_CMD = 0x0B41,
247 HNS3_OPC_PPU_PF_OTHER_INT_CMD = 0x0B42,
248 HNS3_OPC_COMMON_ECC_INT_CFG = 0x1505,
249 HNS3_OPC_QUERY_RAS_INT_STS_BD_NUM = 0x1510,
250 HNS3_OPC_QUERY_CLEAR_MPF_RAS_INT = 0x1511,
251 HNS3_OPC_QUERY_CLEAR_PF_RAS_INT = 0x1512,
252 HNS3_OPC_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
253 HNS3_OPC_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,
254 HNS3_OPC_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,
255 HNS3_OPC_IGU_EGU_TNL_INT_EN = 0x1803,
256 HNS3_OPC_IGU_COMMON_INT_EN = 0x1806,
257 HNS3_OPC_TM_QCN_MEM_INT_CFG = 0x1A14,
258 HNS3_OPC_PPP_CMD0_INT_CMD = 0x2100,
259 HNS3_OPC_PPP_CMD1_INT_CMD = 0x2101,
260 HNS3_OPC_NCSI_INT_EN = 0x2401,
263 #define HNS3_CMD_FLAG_IN BIT(0)
264 #define HNS3_CMD_FLAG_OUT BIT(1)
265 #define HNS3_CMD_FLAG_NEXT BIT(2)
266 #define HNS3_CMD_FLAG_WR BIT(3)
267 #define HNS3_CMD_FLAG_NO_INTR BIT(4)
268 #define HNS3_CMD_FLAG_ERR_INTR BIT(5)
270 #define HNS3_MPF_RAS_INT_MIN_BD_NUM 10
271 #define HNS3_PF_RAS_INT_MIN_BD_NUM 4
272 #define HNS3_MPF_MSIX_INT_MIN_BD_NUM 10
273 #define HNS3_PF_MSIX_INT_MIN_BD_NUM 4
275 #define HNS3_BUF_SIZE_UNIT 256
276 #define HNS3_BUF_MUL_BY 2
277 #define HNS3_BUF_DIV_BY 2
278 #define NEED_RESERVE_TC_NUM 2
279 #define BUF_MAX_PERCENT 100
280 #define BUF_RESERVE_PERCENT 90
282 #define HNS3_MAX_TC_NUM 8
283 #define HNS3_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */
284 #define HNS3_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */
285 #define HNS3_TX_BUFF_RSV_NUM 8
286 struct hns3_tx_buff_alloc_cmd {
287 uint16_t tx_pkt_buff[HNS3_MAX_TC_NUM];
288 uint8_t tx_buff_rsv[HNS3_TX_BUFF_RSV_NUM];
291 struct hns3_rx_priv_buff_cmd {
292 uint16_t buf_num[HNS3_MAX_TC_NUM];
297 #define HNS3_FW_VERSION_BYTE3_S 24
298 #define HNS3_FW_VERSION_BYTE3_M GENMASK(31, 24)
299 #define HNS3_FW_VERSION_BYTE2_S 16
300 #define HNS3_FW_VERSION_BYTE2_M GENMASK(23, 16)
301 #define HNS3_FW_VERSION_BYTE1_S 8
302 #define HNS3_FW_VERSION_BYTE1_M GENMASK(15, 8)
303 #define HNS3_FW_VERSION_BYTE0_S 0
304 #define HNS3_FW_VERSION_BYTE0_M GENMASK(7, 0)
306 enum HNS3_CAPS_BITS {
309 HNS3_CAPS_FD_QUEUE_REGION_B,
312 HNS3_CAPS_SIMPLE_BD_B,
315 HNS3_CAPS_TQP_TXRX_INDEP_B,
318 HNS3_CAPS_UDP_TUNNEL_CSUM_B,
322 HNS3_CAPS_RXD_ADV_LAYOUT_B,
325 enum HNS3_API_CAP_BITS {
326 HNS3_API_CAP_FLEX_RSS_TBL_B,
329 #define HNS3_QUERY_CAP_LENGTH 3
330 struct hns3_query_version_cmd {
334 uint32_t caps[HNS3_QUERY_CAP_LENGTH]; /* capabilities of device */
337 #define HNS3_RX_PRIV_EN_B 15
338 #define HNS3_TC_NUM_ONE_DESC 4
339 struct hns3_priv_wl {
344 struct hns3_rx_priv_wl_buf {
345 struct hns3_priv_wl tc_wl[HNS3_TC_NUM_ONE_DESC];
348 struct hns3_rx_com_thrd {
349 struct hns3_priv_wl com_thrd[HNS3_TC_NUM_ONE_DESC];
352 struct hns3_rx_com_wl {
353 struct hns3_priv_wl com_wl;
356 struct hns3_waterline {
361 struct hns3_tc_thrd {
366 struct hns3_priv_buf {
367 struct hns3_waterline wl; /* Waterline for low and high */
368 uint32_t buf_size; /* TC private buffer size */
369 uint32_t tx_buf_size;
370 uint32_t enable; /* Enable TC private buffer or not */
373 struct hns3_shared_buf {
374 struct hns3_waterline self;
375 struct hns3_tc_thrd tc_thrd[HNS3_MAX_TC_NUM];
379 struct hns3_pkt_buf_alloc {
380 struct hns3_priv_buf priv_buf[HNS3_MAX_TC_NUM];
381 struct hns3_shared_buf s_buf;
384 #define HNS3_RX_COM_WL_EN_B 15
385 struct hns3_rx_com_wl_buf_cmd {
391 #define HNS3_RX_PKT_EN_B 15
392 struct hns3_rx_pkt_buf_cmd {
398 #define HNS3_PF_STATE_DONE_B 0
399 #define HNS3_PF_STATE_MAIN_B 1
400 #define HNS3_PF_STATE_BOND_B 2
401 #define HNS3_PF_STATE_MAC_N_B 6
402 #define HNS3_PF_MAC_NUM_MASK 0x3
403 #define HNS3_PF_STATE_MAIN BIT(HNS3_PF_STATE_MAIN_B)
404 #define HNS3_PF_STATE_DONE BIT(HNS3_PF_STATE_DONE_B)
405 #define HNS3_VF_RST_STATE_NUM 4
406 struct hns3_func_status_cmd {
407 uint32_t vf_rst_state[HNS3_VF_RST_STATE_NUM];
411 uint8_t pf_cnt_in_mac;
417 #define HNS3_PF_VEC_NUM_S 0
418 #define HNS3_PF_VEC_NUM_M GENMASK(15, 0)
419 #define HNS3_MIN_VECTOR_NUM 2 /* one for msi-x, another for IO */
420 struct hns3_pf_res_cmd {
423 uint16_t msixcap_localid_ba_nic;
424 uint16_t nic_pf_intr_vector_number;
425 uint16_t roce_pf_intr_vector_number;
426 uint16_t pf_own_fun_number;
427 uint16_t tx_buf_size;
428 uint16_t dv_buf_size;
429 /* number of queues that exceed 1024 */
430 uint16_t ext_tqp_num;
431 uint16_t roh_pf_intr_vector_number;
435 #define HNS3_VF_VEC_NUM_S 0
436 #define HNS3_VF_VEC_NUM_M GENMASK(7, 0)
437 struct hns3_vf_res_cmd {
440 uint16_t msixcap_localid_ba_nic;
441 uint16_t msixcap_localid_ba_rocee;
442 uint16_t vf_intr_vector_number;
446 #define HNS3_UMV_SPC_ALC_B 0
447 struct hns3_umv_spc_alc_cmd {
454 #define HNS3_CFG_OFFSET_S 0
455 #define HNS3_CFG_OFFSET_M GENMASK(19, 0)
456 #define HNS3_CFG_RD_LEN_S 24
457 #define HNS3_CFG_RD_LEN_M GENMASK(27, 24)
458 #define HNS3_CFG_RD_LEN_BYTES 16
459 #define HNS3_CFG_RD_LEN_UNIT 4
461 #define HNS3_CFG_VMDQ_S 0
462 #define HNS3_CFG_VMDQ_M GENMASK(7, 0)
463 #define HNS3_CFG_TC_NUM_S 8
464 #define HNS3_CFG_TC_NUM_M GENMASK(15, 8)
465 #define HNS3_CFG_TQP_DESC_N_S 16
466 #define HNS3_CFG_TQP_DESC_N_M GENMASK(31, 16)
467 #define HNS3_CFG_PHY_ADDR_S 0
468 #define HNS3_CFG_PHY_ADDR_M GENMASK(7, 0)
469 #define HNS3_CFG_MEDIA_TP_S 8
470 #define HNS3_CFG_MEDIA_TP_M GENMASK(15, 8)
471 #define HNS3_CFG_RX_BUF_LEN_S 16
472 #define HNS3_CFG_RX_BUF_LEN_M GENMASK(31, 16)
473 #define HNS3_CFG_MAC_ADDR_H_S 0
474 #define HNS3_CFG_MAC_ADDR_H_M GENMASK(15, 0)
475 #define HNS3_CFG_DEFAULT_SPEED_S 16
476 #define HNS3_CFG_DEFAULT_SPEED_M GENMASK(23, 16)
477 #define HNS3_CFG_RSS_SIZE_S 24
478 #define HNS3_CFG_RSS_SIZE_M GENMASK(31, 24)
479 #define HNS3_CFG_SPEED_ABILITY_S 0
480 #define HNS3_CFG_SPEED_ABILITY_M GENMASK(7, 0)
481 #define HNS3_CFG_UMV_TBL_SPACE_S 16
482 #define HNS3_CFG_UMV_TBL_SPACE_M GENMASK(31, 16)
483 #define HNS3_CFG_EXT_RSS_SIZE_S 0
484 #define HNS3_CFG_EXT_RSS_SIZE_M GENMASK(3, 0)
486 #define HNS3_ACCEPT_TAG1_B 0
487 #define HNS3_ACCEPT_UNTAG1_B 1
488 #define HNS3_PORT_INS_TAG1_EN_B 2
489 #define HNS3_PORT_INS_TAG2_EN_B 3
490 #define HNS3_CFG_NIC_ROCE_SEL_B 4
491 #define HNS3_ACCEPT_TAG2_B 5
492 #define HNS3_ACCEPT_UNTAG2_B 6
493 #define HNS3_TAG_SHIFT_MODE_EN_B 7
495 #define HNS3_REM_TAG1_EN_B 0
496 #define HNS3_REM_TAG2_EN_B 1
497 #define HNS3_SHOW_TAG1_EN_B 2
498 #define HNS3_SHOW_TAG2_EN_B 3
499 #define HNS3_DISCARD_TAG1_EN_B 5
500 #define HNS3_DISCARD_TAG2_EN_B 6
502 /* Factor used to calculate offset and bitmap of VF num */
503 #define HNS3_VF_NUM_PER_CMD 64
504 #define HNS3_VF_NUM_PER_BYTE 8
506 struct hns3_cfg_param_cmd {
512 #define HNS3_VPORT_VTAG_RX_CFG_CMD_VF_BITMAP_NUM 8
513 struct hns3_vport_vtag_rx_cfg_cmd {
514 uint8_t vport_vlan_cfg;
517 uint8_t vf_bitmap[HNS3_VPORT_VTAG_RX_CFG_CMD_VF_BITMAP_NUM];
521 struct hns3_vport_vtag_tx_cfg_cmd {
522 uint8_t vport_vlan_cfg;
525 uint16_t def_vlan_tag1;
526 uint16_t def_vlan_tag2;
527 uint8_t vf_bitmap[8];
532 struct hns3_vlan_filter_ctrl_cmd {
540 #define HNS3_VLAN_OFFSET_BITMAP_NUM 20
541 struct hns3_vlan_filter_pf_cfg_cmd {
545 uint8_t vlan_offset_bitmap[HNS3_VLAN_OFFSET_BITMAP_NUM];
548 #define HNS3_VLAN_FILTER_VF_CFG_CMD_VF_BITMAP_NUM 16
549 struct hns3_vlan_filter_vf_cfg_cmd {
555 uint8_t vf_bitmap[HNS3_VLAN_FILTER_VF_CFG_CMD_VF_BITMAP_NUM];
558 struct hns3_tx_vlan_type_cfg_cmd {
559 uint16_t ot_vlan_type;
560 uint16_t in_vlan_type;
564 struct hns3_rx_vlan_type_cfg_cmd {
565 uint16_t ot_fst_vlan_type;
566 uint16_t ot_sec_vlan_type;
567 uint16_t in_fst_vlan_type;
568 uint16_t in_sec_vlan_type;
572 #define HNS3_TSO_MSS_MIN_S 0
573 #define HNS3_TSO_MSS_MIN_M GENMASK(13, 0)
575 #define HNS3_TSO_MSS_MAX_S 16
576 #define HNS3_TSO_MSS_MAX_M GENMASK(29, 16)
578 struct hns3_cfg_tso_status_cmd {
579 rte_le16_t tso_mss_min;
580 rte_le16_t tso_mss_max;
584 #define HNS3_GRO_EN_B 0
585 struct hns3_cfg_gro_status_cmd {
590 #define HNS3_TSO_MSS_MIN 256
591 #define HNS3_TSO_MSS_MAX 9668
593 #define HNS3_RSS_HASH_KEY_OFFSET_B 4
595 #define HNS3_RSS_CFG_TBL_SIZE 16
596 #define HNS3_RSS_HASH_KEY_NUM 16
597 /* Configure the algorithm mode and Hash Key, opcode:0x0D01 */
598 struct hns3_rss_generic_config_cmd {
599 /* Hash_algorithm(8.0~8.3), hash_key_offset(8.4~8.7) */
602 uint8_t hash_key[HNS3_RSS_HASH_KEY_NUM];
605 /* Configure the tuple selection for RSS hash input, opcode:0x0D02 */
606 struct hns3_rss_input_tuple_cmd {
607 uint64_t tuple_field;
611 #define HNS3_RSS_CFG_TBL_SIZE 16
612 #define HNS3_RSS_CFG_TBL_SIZE_H 4
613 #define HNS3_RSS_CFG_TBL_BW_H 2
614 #define HNS3_RSS_CFG_TBL_BW_L 8
616 /* Configure the indirection table, opcode:0x0D07 */
617 struct hns3_rss_indirection_table_cmd {
618 uint16_t start_table_index; /* Bit3~0 must be 0x0. */
619 uint16_t rss_set_bitmap;
620 uint8_t rss_result_h[HNS3_RSS_CFG_TBL_SIZE_H];
621 uint8_t rss_result_l[HNS3_RSS_CFG_TBL_SIZE];
624 #define HNS3_RSS_TC_OFFSET_S 0
625 #define HNS3_RSS_TC_OFFSET_M GENMASK(10, 0)
626 #define HNS3_RSS_TC_SIZE_MSB_S 11
627 #define HNS3_RSS_TC_SIZE_MSB_OFFSET 3
628 #define HNS3_RSS_TC_SIZE_S 12
629 #define HNS3_RSS_TC_SIZE_M GENMASK(14, 12)
630 #define HNS3_RSS_TC_VALID_B 15
632 /* Configure the tc_size and tc_offset, opcode:0x0D08 */
633 struct hns3_rss_tc_mode_cmd {
634 uint16_t rss_tc_mode[HNS3_MAX_TC_NUM];
638 #define HNS3_LINK_STATUS_UP_B 0
639 #define HNS3_LINK_STATUS_UP_M BIT(HNS3_LINK_STATUS_UP_B)
640 struct hns3_link_status_cmd {
645 struct hns3_promisc_param {
650 #define HNS3_PROMISC_TX_EN_B BIT(4)
651 #define HNS3_PROMISC_RX_EN_B BIT(5)
652 #define HNS3_PROMISC_EN_B 1
653 #define HNS3_PROMISC_EN_ALL 0x7
654 #define HNS3_PROMISC_EN_UC 0x1
655 #define HNS3_PROMISC_EN_MC 0x2
656 #define HNS3_PROMISC_EN_BC 0x4
657 struct hns3_promisc_cfg_cmd {
664 enum hns3_promisc_type {
670 #define HNS3_LINK_EVENT_REPORT_EN_B 0
671 #define HNS3_NCSI_ERROR_REPORT_EN_B 1
672 #define HNS3_FIRMWARE_PHY_DRIVER_EN_B 2
673 struct hns3_firmware_compat_cmd {
678 /* Bitmap flags in supported, advertising and lp_advertising */
679 #define HNS3_PHY_LINK_SPEED_10M_HD_BIT BIT(0)
680 #define HNS3_PHY_LINK_SPEED_10M_BIT BIT(1)
681 #define HNS3_PHY_LINK_SPEED_100M_HD_BIT BIT(2)
682 #define HNS3_PHY_LINK_SPEED_100M_BIT BIT(3)
683 #define HNS3_PHY_LINK_MODE_AUTONEG_BIT BIT(6)
684 #define HNS3_PHY_LINK_MODE_PAUSE_BIT BIT(13)
685 #define HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT BIT(14)
687 #define HNS3_PHY_PARAM_CFG_BD_NUM 2
688 struct hns3_phy_params_bd0_cmd {
690 #define HNS3_PHY_DUPLEX_CFG_B 0
692 #define HNS3_PHY_AUTONEG_CFG_B 0
695 uint8_t eth_tp_mdix_ctrl;
701 uint32_t advertising;
702 uint32_t lp_advertising;
705 struct hns3_phy_params_bd1_cmd {
706 uint8_t master_slave_cfg;
707 uint8_t master_slave_state;
712 #define HNS3_MAC_TX_EN_B 6
713 #define HNS3_MAC_RX_EN_B 7
714 #define HNS3_MAC_PAD_TX_B 11
715 #define HNS3_MAC_PAD_RX_B 12
716 #define HNS3_MAC_1588_TX_B 13
717 #define HNS3_MAC_1588_RX_B 14
718 #define HNS3_MAC_APP_LP_B 15
719 #define HNS3_MAC_LINE_LP_B 16
720 #define HNS3_MAC_FCS_TX_B 17
721 #define HNS3_MAC_RX_OVERSIZE_TRUNCATE_B 18
722 #define HNS3_MAC_RX_FCS_STRIP_B 19
723 #define HNS3_MAC_RX_FCS_B 20
724 #define HNS3_MAC_TX_UNDER_MIN_ERR_B 21
725 #define HNS3_MAC_TX_OVERSIZE_TRUNCATE_B 22
727 struct hns3_config_mac_mode_cmd {
728 uint32_t txrx_pad_fcs_loop_en;
732 #define HNS3_CFG_SPEED_10M 6
733 #define HNS3_CFG_SPEED_100M 7
734 #define HNS3_CFG_SPEED_1G 0
735 #define HNS3_CFG_SPEED_10G 1
736 #define HNS3_CFG_SPEED_25G 2
737 #define HNS3_CFG_SPEED_40G 3
738 #define HNS3_CFG_SPEED_50G 4
739 #define HNS3_CFG_SPEED_100G 5
740 #define HNS3_CFG_SPEED_200G 8
742 #define HNS3_CFG_SPEED_S 0
743 #define HNS3_CFG_SPEED_M GENMASK(5, 0)
744 #define HNS3_CFG_DUPLEX_B 7
745 #define HNS3_CFG_DUPLEX_M BIT(HNS3_CFG_DUPLEX_B)
747 #define HNS3_CFG_MAC_SPEED_CHANGE_EN_B 0
749 struct hns3_config_mac_speed_dup_cmd {
751 uint8_t mac_change_fec_en;
755 #define HNS3_TQP_ENABLE_B 0
757 #define HNS3_MAC_CFG_AN_EN_B 0
758 #define HNS3_MAC_CFG_AN_INT_EN_B 1
759 #define HNS3_MAC_CFG_AN_INT_MSK_B 2
760 #define HNS3_MAC_CFG_AN_INT_CLR_B 3
761 #define HNS3_MAC_CFG_AN_RST_B 4
763 #define HNS3_MAC_CFG_AN_EN BIT(HNS3_MAC_CFG_AN_EN_B)
765 struct hns3_config_auto_neg_cmd {
766 uint32_t cfg_an_cmd_flag;
770 #define HNS3_MAC_CFG_FEC_AUTO_EN_B 0
771 #define HNS3_MAC_CFG_FEC_MODE_S 1
772 #define HNS3_MAC_CFG_FEC_MODE_M GENMASK(3, 1)
773 #define HNS3_MAC_FEC_OFF 0
774 #define HNS3_MAC_FEC_BASER 1
775 #define HNS3_MAC_FEC_RS 2
777 #define HNS3_SFP_INFO_BD0_LEN 20UL
778 #define HNS3_SFP_INFO_BDX_LEN 24UL
780 struct hns3_sfp_info_bd0_cmd {
783 uint8_t data[HNS3_SFP_INFO_BD0_LEN];
786 struct hns3_sfp_type {
791 struct hns3_sfp_speed_cmd {
793 uint8_t query_type; /* 0: sfp speed, 1: active fec */
794 uint8_t active_fec; /* current FEC mode */
799 /* Configure FEC mode, opcode:0x031A */
800 struct hns3_config_fec_cmd {
805 #define HNS3_MAC_MGR_MASK_VLAN_B BIT(0)
806 #define HNS3_MAC_MGR_MASK_MAC_B BIT(1)
807 #define HNS3_MAC_MGR_MASK_ETHERTYPE_B BIT(2)
808 #define HNS3_MAC_ETHERTYPE_LLDP 0x88cc
810 struct hns3_mac_mgr_tbl_entry_cmd {
814 uint32_t mac_addr_hi32;
815 uint16_t mac_addr_lo16;
817 uint16_t ethter_type;
818 uint16_t egress_port;
819 uint16_t egress_queue;
820 uint8_t sw_port_id_aware;
822 uint8_t i_port_bitmap;
823 uint8_t i_port_direction;
827 struct hns3_cfg_com_tqp_queue_cmd {
834 #define HNS3_TQP_MAP_TYPE_PF 0
835 #define HNS3_TQP_MAP_TYPE_VF 1
836 #define HNS3_TQP_MAP_TYPE_B 0
837 #define HNS3_TQP_MAP_EN_B 1
839 struct hns3_tqp_map_cmd {
840 uint16_t tqp_id; /* Absolute tqp id for in this pf */
841 uint8_t tqp_vf; /* VF id */
842 uint8_t tqp_flag; /* Indicate it's pf or vf tqp */
843 uint16_t tqp_vid; /* Virtual id in this pf/vf */
847 enum hns3_ring_type {
852 enum hns3_int_gl_idx {
855 HNS3_RING_GL_IMMEDIATE = 3
858 #define HNS3_RING_GL_IDX_S 0
859 #define HNS3_RING_GL_IDX_M GENMASK(1, 0)
861 #define HNS3_VECTOR_ELEMENTS_PER_CMD 10
863 #define HNS3_INT_TYPE_S 0
864 #define HNS3_INT_TYPE_M GENMASK(1, 0)
865 #define HNS3_TQP_ID_S 2
866 #define HNS3_TQP_ID_M GENMASK(12, 2)
867 #define HNS3_INT_GL_IDX_S 13
868 #define HNS3_INT_GL_IDX_M GENMASK(14, 13)
869 #define HNS3_TQP_INT_ID_L_S 0
870 #define HNS3_TQP_INT_ID_L_M GENMASK(7, 0)
871 #define HNS3_TQP_INT_ID_H_S 8
872 #define HNS3_TQP_INT_ID_H_M GENMASK(15, 8)
873 struct hns3_ctrl_vector_chain_cmd {
874 uint8_t int_vector_id; /* the low order of the interrupt id */
875 uint8_t int_cause_num;
876 uint16_t tqp_type_and_id[HNS3_VECTOR_ELEMENTS_PER_CMD];
878 uint8_t int_vector_id_h; /* the high order of the interrupt id */
881 struct hns3_config_max_frm_size_cmd {
882 uint16_t max_frm_size;
883 uint8_t min_frm_size;
887 enum hns3_mac_vlan_tbl_opcode {
888 HNS3_MAC_VLAN_ADD, /* Add new or modify mac_vlan */
889 HNS3_MAC_VLAN_UPDATE, /* Modify other fields of this table */
890 HNS3_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */
891 HNS3_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */
894 enum hns3_mac_vlan_add_resp_code {
895 HNS3_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */
896 HNS3_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */
899 #define HNS3_MC_MAC_VLAN_ADD_DESC_NUM 3
901 #define HNS3_MAC_VLAN_BIT0_EN_B 0
902 #define HNS3_MAC_VLAN_BIT1_EN_B 1
903 #define HNS3_MAC_EPORT_SW_EN_B 12
904 #define HNS3_MAC_EPORT_TYPE_B 11
905 #define HNS3_MAC_EPORT_VFID_S 3
906 #define HNS3_MAC_EPORT_VFID_M GENMASK(10, 3)
907 #define HNS3_MAC_EPORT_PFID_S 0
908 #define HNS3_MAC_EPORT_PFID_M GENMASK(2, 0)
909 struct hns3_mac_vlan_tbl_entry_cmd {
913 uint32_t mac_addr_hi32;
914 uint16_t mac_addr_lo16;
918 uint16_t egress_port;
919 uint16_t egress_queue;
923 #define HNS3_TQP_RESET_B 0
924 struct hns3_reset_tqp_queue_cmd {
927 uint8_t ready_to_reset;
928 uint8_t queue_direction;
932 #define HNS3_CFG_RESET_MAC_B 3
933 #define HNS3_CFG_RESET_FUNC_B 7
934 struct hns3_reset_cmd {
935 uint8_t mac_func_reset;
936 uint8_t fun_reset_vfid;
940 #define HNS3_QUERY_DEV_SPECS_BD_NUM 4
941 struct hns3_dev_specs_0_cmd {
943 uint32_t mac_entry_num;
944 uint32_t mng_entry_num;
945 uint16_t rss_ind_tbl_size;
946 uint16_t rss_key_size;
947 uint16_t intr_ql_max;
948 uint8_t max_non_tso_bd_num;
950 uint32_t max_tm_rate;
953 struct hns3_query_rpu_cmd {
954 uint32_t tc_queue_num;
956 uint32_t rpu_rx_pkt_drop_cnt;
960 #define HNS3_MAX_TQP_NUM_HIP08_PF 64
961 #define HNS3_DEFAULT_TX_BUF 0x4000 /* 16k bytes */
962 #define HNS3_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
963 #define HNS3_DEFAULT_DV 0xA000 /* 40k byte */
964 #define HNS3_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */
965 #define HNS3_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */
967 #define HNS3_TYPE_CRQ 0
968 #define HNS3_TYPE_CSQ 1
970 #define HNS3_NIC_SW_RST_RDY_B 16
971 #define HNS3_NIC_SW_RST_RDY BIT(HNS3_NIC_SW_RST_RDY_B)
972 #define HNS3_NIC_CMQ_DESC_NUM 1024
973 #define HNS3_NIC_CMQ_DESC_NUM_S 3
975 #define HNS3_CMD_SEND_SYNC(flag) \
976 ((flag) & HNS3_CMD_FLAG_NO_INTR)
978 void hns3_cmd_reuse_desc(struct hns3_cmd_desc *desc, bool is_read);
979 void hns3_cmd_setup_basic_desc(struct hns3_cmd_desc *desc,
980 enum hns3_opcode_type opcode, bool is_read);
981 int hns3_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc, int num);
982 int hns3_cmd_init_queue(struct hns3_hw *hw);
983 int hns3_cmd_init(struct hns3_hw *hw);
984 void hns3_cmd_destroy_queue(struct hns3_hw *hw);
985 void hns3_cmd_uninit(struct hns3_hw *hw);
987 #endif /* _HNS3_CMD_H_ */