1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
8 #define HNS3_ETHER_MAX_RATE 100000
11 #define HNS3_TX_MAC_PAUSE_EN_MSK BIT(0)
12 #define HNS3_RX_MAC_PAUSE_EN_MSK BIT(1)
14 #define HNS3_DEFAULT_PAUSE_TRANS_GAP 0x18
15 #define HNS3_DEFAULT_PAUSE_TRANS_TIME 0xFFFF
18 #define HNS3_DCB_TX_SCHD_DWRR_MSK BIT(0)
19 #define HNS3_DCB_TX_SCHD_SP_MSK 0xFE
21 enum hns3_shap_bucket {
22 HNS3_DCB_SHAP_C_BUCKET = 0,
23 HNS3_DCB_SHAP_P_BUCKET,
26 struct hns3_priority_weight_cmd {
32 struct hns3_qs_weight_cmd {
38 struct hns3_pg_weight_cmd {
44 struct hns3_ets_tc_weight_cmd {
45 uint8_t tc_weight[HNS3_MAX_TC_NUM];
46 uint8_t weight_offset;
50 struct hns3_qs_to_pri_link_cmd {
54 #define HNS3_DCB_QS_PRI_LINK_VLD_MSK BIT(0)
55 #define HNS3_DCB_QS_ID_L_MSK GENMASK(9, 0)
56 #define HNS3_DCB_QS_ID_L_S 0
57 #define HNS3_DCB_QS_ID_H_MSK GENMASK(14, 10)
58 #define HNS3_DCB_QS_ID_H_S 10
59 #define HNS3_DCB_QS_ID_H_EXT_S 11
60 #define HNS3_DCB_QS_ID_H_EXT_MSK GENMASK(15, 11)
65 struct hns3_nq_to_qs_link_cmd {
68 #define HNS3_DCB_Q_QS_LINK_VLD_MSK BIT(10)
73 #define HNS3_DCB_SHAP_IR_B_MSK GENMASK(7, 0)
74 #define HNS3_DCB_SHAP_IR_B_LSH 0
75 #define HNS3_DCB_SHAP_IR_U_MSK GENMASK(11, 8)
76 #define HNS3_DCB_SHAP_IR_U_LSH 8
77 #define HNS3_DCB_SHAP_IR_S_MSK GENMASK(15, 12)
78 #define HNS3_DCB_SHAP_IR_S_LSH 12
79 #define HNS3_DCB_SHAP_BS_B_MSK GENMASK(20, 16)
80 #define HNS3_DCB_SHAP_BS_B_LSH 16
81 #define HNS3_DCB_SHAP_BS_S_MSK GENMASK(25, 21)
82 #define HNS3_DCB_SHAP_BS_S_LSH 21
85 * For more flexible selection of shapping algorithm in different network
86 * engine, the algorithm calculating shapping parameter is moved to firmware to
87 * execute. Bit HNS3_TM_RATE_VLD_B of flag field in hns3_pri_shapping_cmd,
88 * hns3_pg_shapping_cmd or hns3_port_shapping_cmd is set to 1 to require
89 * firmware to recalculate shapping parameters. However, whether the parameters
90 * are recalculated depends on the firmware version. If firmware doesn't support
91 * the calculation of shapping parameters, such as on network engine with
92 * revision id 0x21, the value driver calculated will be used to configure to
93 * hardware. On the contrary, firmware ignores configuration of driver
94 * and recalculates the parameter.
96 #define HNS3_TM_RATE_VLD_B 0
98 struct hns3_pri_shapping_cmd {
101 uint32_t pri_shapping_para;
104 uint32_t pri_rate; /* Unit Mbps */
108 struct hns3_pg_shapping_cmd {
111 uint32_t pg_shapping_para;
114 uint32_t pg_rate; /* Unit Mbps */
118 struct hns3_port_shapping_cmd {
119 uint32_t port_shapping_para;
122 uint32_t port_rate; /* Unit Mbps */
126 #define HNS3_BP_GRP_NUM 32
127 #define HNS3_BP_SUB_GRP_ID_S 0
128 #define HNS3_BP_SUB_GRP_ID_M GENMASK(4, 0)
129 #define HNS3_BP_GRP_ID_S 5
130 #define HNS3_BP_GRP_ID_M GENMASK(9, 5)
132 struct hns3_bp_to_qs_map_cmd {
140 struct hns3_pfc_en_cmd {
141 uint8_t tx_rx_en_bitmap;
142 uint8_t pri_en_bitmap;
146 struct hns3_cfg_pause_param_cmd {
147 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
148 uint8_t pause_trans_gap;
150 uint16_t pause_trans_time;
152 /* extra mac address to do double check for pause frame */
153 uint8_t mac_addr_extra[RTE_ETHER_ADDR_LEN];
157 struct hns3_pg_to_pri_link_cmd {
164 enum hns3_shaper_level {
165 HNS3_SHAPER_LVL_PRI = 0,
166 HNS3_SHAPER_LVL_PG = 1,
167 HNS3_SHAPER_LVL_PORT = 2,
168 HNS3_SHAPER_LVL_QSET = 3,
169 HNS3_SHAPER_LVL_CNT = 4,
170 HNS3_SHAPER_LVL_VF = 0,
171 HNS3_SHAPER_LVL_PF = 1,
174 struct hns3_shaper_parameter {
175 uint32_t ir_b; /* IR_B parameter of IR shaper */
176 uint32_t ir_u; /* IR_U parameter of IR shaper */
177 uint32_t ir_s; /* IR_S parameter of IR shaper */
180 #define hns3_dcb_set_field(dest, string, val) \
181 hns3_set_field((dest), \
182 (HNS3_DCB_SHAP_##string##_MSK), \
183 (HNS3_DCB_SHAP_##string##_LSH), val)
184 #define hns3_dcb_get_field(src, string) \
185 hns3_get_field((src), (HNS3_DCB_SHAP_##string##_MSK), \
186 (HNS3_DCB_SHAP_##string##_LSH))
188 int hns3_pause_addr_cfg(struct hns3_hw *hw, const uint8_t *mac_addr);
190 int hns3_dcb_configure(struct hns3_adapter *hns);
192 int hns3_dcb_init(struct hns3_hw *hw);
194 int hns3_dcb_init_hw(struct hns3_hw *hw);
196 int hns3_dcb_info_init(struct hns3_hw *hw);
198 int hns3_fc_enable(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);
200 int hns3_dcb_pfc_enable(struct rte_eth_dev *dev,
201 struct rte_eth_pfc_conf *pfc_conf);
203 int hns3_queue_to_tc_mapping(struct hns3_hw *hw, uint16_t nb_rx_q,
206 int hns3_dcb_cfg_update(struct hns3_adapter *hns);
208 #endif /* _HNS3_DCB_H_ */