1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
5 #ifndef _HNS3_ETHDEV_H_
6 #define _HNS3_ETHDEV_H_
9 #include <ethdev_driver.h>
10 #include <rte_byteorder.h>
12 #include <rte_spinlock.h>
17 #include "hns3_fdir.h"
18 #include "hns3_stats.h"
22 #define PCI_VENDOR_ID_HUAWEI 0x19e5
25 #define HNS3_DEV_ID_GE 0xA220
26 #define HNS3_DEV_ID_25GE 0xA221
27 #define HNS3_DEV_ID_25GE_RDMA 0xA222
28 #define HNS3_DEV_ID_50GE_RDMA 0xA224
29 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226
30 #define HNS3_DEV_ID_200G_RDMA 0xA228
31 #define HNS3_DEV_ID_100G_VF 0xA22E
32 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F
34 /* PCI Config offsets */
35 #define HNS3_PCI_REVISION_ID 0x08
36 #define HNS3_PCI_REVISION_ID_LEN 1
38 #define PCI_REVISION_ID_HIP08_B 0x21
39 #define PCI_REVISION_ID_HIP09_A 0x30
41 #define HNS3_PF_FUNC_ID 0
42 #define HNS3_1ST_VF_FUNC_ID 1
44 #define HNS3_SW_SHIFT_AND_DISCARD_MODE 0
45 #define HNS3_HW_SHIFT_AND_DISCARD_MODE 1
47 #define HNS3_UNLIMIT_PROMISC_MODE 0
48 #define HNS3_LIMIT_PROMISC_MODE 1
50 #define HNS3_UC_MACADDR_NUM 128
51 #define HNS3_VF_UC_MACADDR_NUM 48
52 #define HNS3_MC_MACADDR_NUM 128
54 #define HNS3_MAX_BD_SIZE 65535
55 #define HNS3_MAX_NON_TSO_BD_PER_PKT 8
56 #define HNS3_MAX_TSO_BD_PER_PKT 63
57 #define HNS3_MAX_FRAME_LEN 9728
58 #define HNS3_VLAN_TAG_SIZE 4
59 #define HNS3_DEFAULT_RX_BUF_LEN 2048
60 #define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1)
61 #define HNS3_MAX_TSO_HDR_SIZE 512
62 #define HNS3_MAX_TSO_HDR_BD_NUM 3
63 #define HNS3_MAX_LRO_SIZE 64512
65 #define HNS3_ETH_OVERHEAD \
66 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2)
67 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD)
68 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD)
69 #define HNS3_DEFAULT_MTU 1500UL
70 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD)
71 #define HNS3_HIP08_MIN_TX_PKT_LEN 33
72 #define HNS3_HIP09_MIN_TX_PKT_LEN 9
74 #define HNS3_BITS_PER_BYTE 8
79 #define HNS3_MAX_PF_NUM 8
80 #define HNS3_UMV_TBL_SIZE 3072
81 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \
82 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM)
84 #define HNS3_PF_CFG_BLOCK_SIZE 32
85 #define HNS3_PF_CFG_DESC_NUM \
86 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES)
88 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0
90 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5
91 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500
93 #define HNS3_QUIT_RESET_CNT 10
94 #define HNS3_QUIT_RESET_DELAY_MS 100
96 #define HNS3_POLL_RESPONE_MS 1
98 #define HNS3_MAX_USER_PRIO 8
108 #define HNS3_SCH_MODE_SP 0
109 #define HNS3_SCH_MODE_DWRR 1
110 struct hns3_pg_info {
112 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */
115 uint8_t tc_dwrr[HNS3_MAX_TC_NUM];
118 struct hns3_tc_info {
120 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */
123 uint8_t up_to_tc_map; /* user priority maping on the TC */
126 struct hns3_dcb_info {
128 uint8_t num_pg; /* It must be 1 if vNET-Base schd */
129 uint8_t pg_dwrr[HNS3_PG_NUM];
130 uint8_t prio_tc[HNS3_MAX_USER_PRIO];
131 struct hns3_pg_info pg_info[HNS3_PG_NUM];
132 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM];
133 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */
134 uint8_t pfc_en; /* Pfc enabled or not for user priority */
137 enum hns3_fc_status {
139 HNS3_FC_STATUS_MAC_PAUSE,
143 struct hns3_tc_queue_info {
144 uint16_t tqp_offset; /* TQP offset from base TQP */
145 uint16_t tqp_count; /* Total TQPs */
146 uint8_t tc; /* TC index */
147 bool enable; /* If this TC is enable or not */
151 uint8_t vmdq_vport_num;
153 uint16_t tqp_desc_num;
155 uint16_t rss_size_max;
158 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
159 uint8_t default_speed;
160 uint32_t numa_node_map;
161 uint8_t speed_ability;
166 enum hns3_media_type {
167 HNS3_MEDIA_TYPE_UNKNOWN,
168 HNS3_MEDIA_TYPE_FIBER,
169 HNS3_MEDIA_TYPE_COPPER,
170 HNS3_MEDIA_TYPE_BACKPLANE,
171 HNS3_MEDIA_TYPE_NONE,
175 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
176 bool default_addr_setted; /* whether default addr(mac_addr) is set */
179 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */
180 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */
181 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */
182 uint32_t link_speed; /* ETH_SPEED_NUM_ */
183 uint32_t supported_capa; /* supported capability for current media */
184 uint32_t advertising; /* advertised capability in the local part */
185 /* advertised capability in the link partner */
186 uint32_t lp_advertising;
187 uint8_t support_autoneg;
190 struct hns3_fake_queue_data {
191 void **rx_queues; /* Array of pointers to fake RX queues. */
192 void **tx_queues; /* Array of pointers to fake TX queues. */
193 uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */
194 uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */
197 #define HNS3_PORT_BASE_VLAN_DISABLE 0
198 #define HNS3_PORT_BASE_VLAN_ENABLE 1
199 struct hns3_port_base_vlan_config {
204 /* Primary process maintains driver state in main thread.
207 * | UNINITIALIZED |<-----------+
208 * +---------------+ |
209 * |.eth_dev_init |.eth_dev_uninit
211 * +---------------+------------+
213 * +---------------+<-----------<---------------+
214 * |.dev_configure | |
216 * +---------------+------------+ |
218 * +---------------+----+ |
220 * | | +---------------+
222 * | | +---------------+
224 * V |.dev_configure |
225 * +---------------+----+ |.dev_close
226 * | CONFIGURED |----------------------------+
227 * +---------------+<-----------+
230 * +---------------+ |
231 * | STARTING |------------^
232 * +---------------+ failed |
234 * | +---------------+
236 * | +---------------+
239 * +---------------+------------+
243 enum hns3_adapter_state {
244 HNS3_NIC_UNINITIALIZED = 0,
245 HNS3_NIC_INITIALIZED,
246 HNS3_NIC_CONFIGURING,
257 /* Reset various stages, execute in order */
258 enum hns3_reset_stage {
259 /* Stop query services, stop transceiver, disable MAC */
261 /* Clear reset completion flags, disable send command */
263 /* Inform IMP to start resetting */
264 RESET_STAGE_REQ_HW_RESET,
265 /* Waiting for hardware reset to complete */
267 /* Reinitialize hardware */
268 RESET_STAGE_DEV_INIT,
269 /* Restore user settings and enable MAC */
271 /* Restart query services, start transceiver */
273 /* Not in reset state */
277 enum hns3_reset_level {
279 HNS3_VF_FUNC_RESET, /* A VF function reset */
281 * All VFs under a PF perform function reset.
282 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
283 * of the reset level and the one defined in kernel driver should be
286 HNS3_VF_PF_FUNC_RESET = 2,
288 * All VFs under a PF perform FLR reset.
289 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
290 * of the reset level and the one defined in kernel driver should be
293 * According to the protocol of PCIe, FLR to a PF resets the PF state as
294 * well as the SR-IOV extended capability including VF Enable which
295 * means that VFs no longer exist.
297 * In PF FLR, the register state of VF is not reliable, VF's driver
298 * should not access the registers of the VF device.
300 HNS3_VF_FULL_RESET = 3,
301 HNS3_FLR_RESET, /* A VF perform FLR reset */
302 /* All VFs under the rootport perform a global or IMP reset */
304 HNS3_FUNC_RESET, /* A PF function reset */
305 /* All PFs under the rootport perform a global reset */
307 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */
311 enum hns3_wait_result {
318 #define HNS3_RESET_SYNC_US 100000
320 struct hns3_reset_stats {
321 uint64_t request_cnt; /* Total request reset times */
322 uint64_t global_cnt; /* Total GLOBAL reset times */
323 uint64_t imp_cnt; /* Total IMP reset times */
324 uint64_t exec_cnt; /* Total reset executive times */
325 uint64_t success_cnt; /* Total reset successful times */
326 uint64_t fail_cnt; /* Total reset failed times */
327 uint64_t merge_cnt; /* Total merged in high reset times */
330 typedef bool (*check_completion_func)(struct hns3_hw *hw);
332 struct hns3_wait_data {
337 enum hns3_wait_result result;
338 check_completion_func check_completion;
341 struct hns3_reset_ops {
342 void (*reset_service)(void *arg);
343 int (*stop_service)(struct hns3_adapter *hns);
344 int (*prepare_reset)(struct hns3_adapter *hns);
345 int (*wait_hardware_ready)(struct hns3_adapter *hns);
346 int (*reinit_dev)(struct hns3_adapter *hns);
347 int (*restore_conf)(struct hns3_adapter *hns);
348 int (*start_service)(struct hns3_adapter *hns);
358 struct hns3_reset_data {
359 enum hns3_reset_stage stage;
361 /* Reset flag, covering the entire reset process */
363 /* Used to disable sending cmds during reset */
364 uint16_t disable_cmd;
365 /* The reset level being processed */
366 enum hns3_reset_level level;
367 /* Reset level set, each bit represents a reset level */
369 /* Request reset level set, from interrupt or mailbox */
371 int attempts; /* Reset failure retry */
372 int retries; /* Timeout failure retry in reset_post */
374 * At the time of global or IMP reset, the command cannot be sent to
375 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the
376 * reset process, so the mbuf is required to be released after the reset
377 * is completed.The mbuf_deferred_free is used to mark whether mbuf
378 * needs to be released.
380 bool mbuf_deferred_free;
381 struct timeval start_time;
382 struct hns3_reset_stats stats;
383 const struct hns3_reset_ops *ops;
384 struct hns3_wait_data *wait_data;
387 #define HNS3_INTR_MAPPING_VEC_RSV_ONE 0
388 #define HNS3_INTR_MAPPING_VEC_ALL 1
390 #define HNS3_INTR_COALESCE_GL_UINT_2US 0
391 #define HNS3_INTR_COALESCE_GL_UINT_1US 1
393 #define HNS3_INTR_QL_NONE 0
395 struct hns3_queue_intr {
397 * interrupt mapping mode.
399 * HNS3_INTR_MAPPING_VEC_RSV_ONE/HNS3_INTR_MAPPING_VEC_ALL
401 * - HNS3_INTR_MAPPING_VEC_RSV_ONE
402 * For some versions of hardware network engine, because of the
403 * hardware constraint, we need implement clearing the mapping
404 * relationship configurations by binding all queues to the last
405 * interrupt vector and reserving the last interrupt vector. This
406 * method results in a decrease of the maximum queues when upper
407 * applications call the rte_eth_dev_configure API function to
408 * enable Rx interrupt.
410 * - HNS3_INTR_MAPPING_VEC_ALL
411 * PMD driver can map/unmmap all interrupt vectors with queues When
412 * Rx interrupt in enabled.
414 uint8_t mapping_mode;
416 * The unit of GL(gap limiter) configuration for interrupt coalesce of
419 * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US
422 /* The max QL(quantity limiter) value */
426 #define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0
427 #define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1
430 struct rte_eth_dev_data *data;
432 uint8_t revision; /* PCI revision, low byte of class word */
434 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */
435 struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */
436 pthread_t irq_thread_id;
438 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
439 struct hns3_tqp_stats tqp_stats;
440 /* Include Mac stats | Rx stats | Tx stats */
441 struct hns3_mac_stats mac_stats;
442 struct hns3_rx_missed_stats imissed_stats;
446 uint16_t total_tqps_num; /* total task queue pairs of this PF */
447 uint16_t tqps_num; /* num task queue pairs of this function */
448 uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */
449 uint16_t rss_size_max; /* HW defined max RSS task queue */
450 uint16_t rx_buf_len; /* hold min hardware rx buf len */
451 uint16_t num_tx_desc; /* desc num of per tx queue */
452 uint16_t num_rx_desc; /* desc num of per rx queue */
453 uint32_t mng_entry_num; /* number of manager table entry */
454 uint32_t mac_entry_num; /* number of mac-vlan table entry */
456 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM];
457 int mc_addrs_num; /* Multicast mac addresses number */
459 /* The configuration info of RSS */
460 struct hns3_rss_conf rss_info;
461 bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */
462 uint16_t rss_ind_tbl_size;
463 uint16_t rss_key_size;
465 uint8_t num_tc; /* Total number of enabled TCs */
467 enum hns3_fc_mode current_mode;
468 enum hns3_fc_mode requested_mode;
469 struct hns3_dcb_info dcb_info;
470 enum hns3_fc_status current_fc_status; /* current flow control status */
471 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM];
472 uint16_t used_rx_queues;
473 uint16_t used_tx_queues;
475 /* Config max queue numbers between rx and tx queues from user */
476 uint16_t cfg_max_queues;
477 struct hns3_fake_queue_data fkq_data; /* fake queue data */
478 uint16_t alloc_rss_size; /* RX queue number per TC */
479 uint16_t tx_qnum_per_tc; /* TX queue number per TC */
482 uint32_t max_tm_rate;
484 * The minimum length of the packet supported by hardware in the Tx
487 uint32_t min_tx_pkt_len;
489 struct hns3_queue_intr intr;
493 * HNS3_TSO_SW_CAL_PSEUDO_H_CSUM/HNS3_TSO_HW_CAL_PSEUDO_H_CSUM
495 * - HNS3_TSO_SW_CAL_PSEUDO_H_CSUM
496 * In this mode, because of the hardware constraint, network driver
497 * software need erase the L4 len value of the TCP pseudo header
498 * and recalculate the TCP pseudo header checksum of packets that
501 * - HNS3_TSO_HW_CAL_PSEUDO_H_CSUM
502 * In this mode, hardware support recalculate the TCP pseudo header
503 * checksum of packets that need TSO, so network driver software
504 * not need to recalculate it.
510 * HNS3_SW_SHIFT_AND_DISCARD_MODE/HNS3_HW_SHFIT_AND_DISCARD_MODE
512 * - HNS3_SW_SHIFT_AND_DISCARD_MODE
513 * For some versions of hardware network engine, because of the
514 * hardware limitation, PMD driver needs to detect the PVID status
515 * to work with haredware to implement PVID-related functions.
516 * For example, driver need discard the stripped PVID tag to ensure
517 * the PVID will not report to mbuf and shift the inserted VLAN tag
518 * to avoid port based VLAN covering it.
520 * - HNS3_HW_SHIT_AND_DISCARD_MODE
521 * PMD driver does not need to process PVID-related functions in
522 * I/O process, Hardware will adjust the sequence between port based
523 * VLAN tag and BD VLAN tag automatically and VLAN tag stripped by
524 * PVID will be invisible to driver. And in this mode, hns3 is able
525 * to send a multi-layer VLAN packets when hw VLAN insert offload
532 * HNS3_UNLIMIT_PROMISC_MODE/HNS3_LIMIT_PROMISC_MODE
534 * - HNS3_UNLIMIT_PROMISC_MODE
535 * In this mode, TX unicast promisc will be configured when promisc
536 * is set, driver can receive all the ingress and outgoing traffic.
537 * In the words, all the ingress packets, all the packets sent from
538 * the PF and other VFs on the same physical port.
540 * - HNS3_LIMIT_PROMISC_MODE
541 * In this mode, TX unicast promisc is shutdown when promisc mode
542 * is set. So, driver will only receive all the ingress traffic.
543 * The packets sent from the PF and other VFs on the same physical
544 * port won't be copied to the function which has set promisc mode.
546 uint8_t promisc_mode;
547 uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */
549 struct hns3_port_base_vlan_config port_base_vlan_cfg;
551 * PMD setup and configuration is not thread safe. Since it is not
552 * performance sensitive, it is better to guarantee thread-safety
553 * and add device level lock. Adapter control operations which
554 * change its state should acquire the lock.
557 enum hns3_adapter_state adapter_state;
558 struct hns3_reset_data reset;
561 #define HNS3_FLAG_TC_BASE_SCH_MODE 1
562 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2
564 struct hns3_err_msix_intr_stats {
565 uint64_t mac_afifo_tnl_int_cnt;
566 uint64_t ppu_mpf_abn_int_st2_msix_cnt;
567 uint64_t ssu_port_based_pf_int_cnt;
568 uint64_t ppp_pf_abnormal_int_cnt;
569 uint64_t ppu_pf_abnormal_int_msix_cnt;
571 uint64_t imp_tcm_ecc_int_cnt;
572 uint64_t cmdq_mem_ecc_int_cnt;
573 uint64_t imp_rd_poison_int_cnt;
574 uint64_t tqp_int_ecc_int_cnt;
575 uint64_t msix_ecc_int_cnt;
576 uint64_t ssu_ecc_multi_bit_int_0_cnt;
577 uint64_t ssu_ecc_multi_bit_int_1_cnt;
578 uint64_t ssu_common_ecc_int_cnt;
579 uint64_t igu_int_cnt;
580 uint64_t ppp_mpf_abnormal_int_st1_cnt;
581 uint64_t ppp_mpf_abnormal_int_st3_cnt;
582 uint64_t ppu_mpf_abnormal_int_st1_cnt;
583 uint64_t ppu_mpf_abn_int_st2_ras_cnt;
584 uint64_t ppu_mpf_abnormal_int_st3_cnt;
585 uint64_t tm_sch_int_cnt;
586 uint64_t qcn_fifo_int_cnt;
587 uint64_t qcn_ecc_int_cnt;
588 uint64_t ncsi_ecc_int_cnt;
589 uint64_t ssu_port_based_err_int_cnt;
590 uint64_t ssu_fifo_overflow_int_cnt;
591 uint64_t ssu_ets_tcg_int_cnt;
592 uint64_t igu_egu_tnl_int_cnt;
593 uint64_t ppu_pf_abnormal_int_ras_cnt;
596 /* vlan entry information. */
597 struct hns3_user_vlan_table {
598 LIST_ENTRY(hns3_user_vlan_table) next;
603 /* Vlan tag configuration for RX direction */
604 struct hns3_rx_vtag_cfg {
605 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */
606 bool strip_tag1_en; /* Whether strip inner vlan tag */
607 bool strip_tag2_en; /* Whether strip outer vlan tag */
609 * If strip_tag_en is enabled, this bit decide whether to map the vlan
612 bool strip_tag1_discard_en;
613 bool strip_tag2_discard_en;
615 * If this bit is enabled, only map inner/outer priority to descriptor
616 * and the vlan tag is always 0.
618 bool vlan1_vlan_prionly;
619 bool vlan2_vlan_prionly;
622 /* Vlan tag configuration for TX direction */
623 struct hns3_tx_vtag_cfg {
624 bool accept_tag1; /* Whether accept tag1 packet from host */
625 bool accept_untag1; /* Whether accept untag1 packet from host */
628 bool insert_tag1_en; /* Whether insert outer vlan tag */
629 bool insert_tag2_en; /* Whether insert inner vlan tag */
631 * In shift mode, hw will shift the sequence of port based VLAN and
634 bool tag_shift_mode_en; /* hw shift vlan tag automatically */
635 uint16_t default_tag1; /* The default outer vlan tag to insert */
636 uint16_t default_tag2; /* The default inner vlan tag to insert */
639 struct hns3_vtag_cfg {
640 struct hns3_rx_vtag_cfg rx_vcfg;
641 struct hns3_tx_vtag_cfg tx_vcfg;
644 /* Request types for IPC. */
645 enum hns3_mp_req_type {
646 HNS3_MP_REQ_START_RXTX = 1,
647 HNS3_MP_REQ_STOP_RXTX,
651 /* Pameters for IPC. */
652 struct hns3_mp_param {
653 enum hns3_mp_req_type type;
658 /* Request timeout for IPC. */
659 #define HNS3_MP_REQ_TIMEOUT_SEC 5
661 /* Key string for IPC. */
662 #define HNS3_MP_NAME "net_hns3_mp"
664 #define HNS3_L2TBL_NUM 4
665 #define HNS3_L3TBL_NUM 16
666 #define HNS3_L4TBL_NUM 16
667 #define HNS3_OL2TBL_NUM 4
668 #define HNS3_OL3TBL_NUM 16
669 #define HNS3_OL4TBL_NUM 16
670 #define HNS3_PTYPE_NUM 256
672 struct hns3_ptype_table {
674 * The next fields used to calc packet-type by the
675 * L3_ID/L4_ID/OL3_ID/OL4_ID from the Rx descriptor.
677 uint32_t l2l3table[HNS3_L2TBL_NUM][HNS3_L3TBL_NUM];
678 uint32_t l4table[HNS3_L4TBL_NUM];
679 uint32_t inner_l2table[HNS3_L2TBL_NUM];
680 uint32_t inner_l3table[HNS3_L3TBL_NUM];
681 uint32_t inner_l4table[HNS3_L4TBL_NUM];
682 uint32_t ol2table[HNS3_OL2TBL_NUM];
683 uint32_t ol3table[HNS3_OL3TBL_NUM];
684 uint32_t ol4table[HNS3_OL4TBL_NUM];
687 * The next field used to calc packet-type by the PTYPE from the Rx
688 * descriptor, it functions only when firmware report the capability of
689 * HNS3_CAPS_RXD_ADV_LAYOUT_B and driver enabled it.
691 uint32_t ptype[HNS3_PTYPE_NUM] __rte_cache_min_aligned;
694 #define HNS3_FIXED_MAX_TQP_NUM_MODE 0
695 #define HNS3_FLEX_MAX_TQP_NUM_MODE 1
698 struct hns3_adapter *adapter;
700 uint16_t func_num; /* num functions of this pf, include pf and vfs */
704 * tqp_config_mode value range:
705 * HNS3_FIXED_MAX_TQP_NUM_MODE,
706 * HNS3_FLEX_MAX_TQP_NUM_MODE
708 * - HNS3_FIXED_MAX_TQP_NUM_MODE
709 * There is a limitation on the number of pf interrupts available for
710 * on some versions of network engines. In this case, the maximum
711 * queue number of pf can not be greater than the interrupt number,
712 * such as pf of network engine with revision_id 0x21. So the maximum
713 * number of queues must be fixed.
715 * - HNS3_FLEX_MAX_TQP_NUM_MODE
716 * In this mode, the maximum queue number of pf has not any constraint
717 * and comes from the macro RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF
718 * in the config file. Users can modify the macro according to their
719 * own application scenarios, which is more flexible to use.
721 uint8_t tqp_config_mode;
723 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */
724 uint32_t tx_buf_size; /* Tx buffer size for each TC */
725 uint32_t dv_buf_size; /* Dv buffer size for each TC */
727 uint16_t mps; /* Max packet size */
730 uint8_t tc_max; /* max number of tc driver supported */
731 uint8_t local_max_tc; /* max number of local tc */
733 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */
735 bool support_fc_autoneg; /* support FC autonegotiate */
737 uint16_t wanted_umv_size;
738 uint16_t max_umv_size;
739 uint16_t used_umv_size;
741 /* Statistics information for abnormal interrupt */
742 struct hns3_err_msix_intr_stats abn_int_stats;
744 bool support_sfp_query;
745 uint32_t fec_mode; /* current FEC mode for ethdev */
747 struct hns3_vtag_cfg vtag_config;
748 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list;
750 struct hns3_fdir_info fdir; /* flow director info */
751 LIST_HEAD(counters, hns3_flow_counter) flow_counters;
753 struct hns3_tm_conf tm_conf;
757 struct hns3_adapter *adapter;
760 struct hns3_adapter {
763 /* Specific for PF or VF */
764 bool is_vf; /* false - PF, true - VF */
770 bool rx_simple_allowed;
772 bool tx_simple_allowed;
775 struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned;
778 #define HNS3_DEV_SUPPORT_DCB_B 0x0
779 #define HNS3_DEV_SUPPORT_COPPER_B 0x1
780 #define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2
781 #define HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B 0x3
782 #define HNS3_DEV_SUPPORT_PTP_B 0x4
783 #define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5
784 #define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6
785 #define HNS3_DEV_SUPPORT_STASH_B 0x7
786 #define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B 0x9
788 #define hns3_dev_dcb_supported(hw) \
789 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)
791 /* Support copper media type */
792 #define hns3_dev_copper_supported(hw) \
793 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B)
795 /* Support UDP GSO offload */
796 #define hns3_dev_udp_gso_supported(hw) \
797 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B)
799 /* Support the queue region action rule of flow directory */
800 #define hns3_dev_fd_queue_region_supported(hw) \
801 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B)
803 /* Support PTP timestamp offload */
804 #define hns3_dev_ptp_supported(hw) \
805 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B)
807 #define hns3_dev_tx_push_supported(hw) \
808 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B)
810 /* Support to Independently enable/disable/reset Tx or Rx queues */
811 #define hns3_dev_indep_txrx_supported(hw) \
812 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B)
814 #define hns3_dev_stash_supported(hw) \
815 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B)
817 #define hns3_dev_rxd_adv_layout_supported(hw) \
818 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B)
820 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \
821 (&((struct hns3_adapter *)adapter)->hw)
822 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \
823 (&((struct hns3_adapter *)adapter)->pf)
824 #define HNS3_DEV_HW_TO_ADAPTER(hw) \
825 container_of(hw, struct hns3_adapter, hw)
827 static inline struct hns3_pf *HNS3_DEV_HW_TO_PF(struct hns3_hw *hw)
829 struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw);
833 #define hns3_set_field(origin, mask, shift, val) \
835 (origin) &= (~(mask)); \
836 (origin) |= ((val) << (shift)) & (mask); \
838 #define hns3_get_field(origin, mask, shift) \
839 (((origin) & (mask)) >> (shift))
840 #define hns3_set_bit(origin, shift, val) \
841 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val))
842 #define hns3_get_bit(origin, shift) \
843 hns3_get_field((origin), (0x1UL << (shift)), (shift))
845 #define hns3_gen_field_val(mask, shift, val) (((val) << (shift)) & (mask))
848 * upper_32_bits - return bits 32-63 of a number
849 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
850 * the "right shift count >= width of type" warning when that quantity is
853 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
855 /* lower_32_bits - return bits 0-31 of a number */
856 #define lower_32_bits(n) ((uint32_t)(n))
858 #define BIT(nr) (1UL << (nr))
860 #define BIT_ULL(x) (1ULL << (x))
862 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
863 #define GENMASK(h, l) \
864 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
866 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
867 #define rounddown(x, y) ((x) - ((x) % (y)))
869 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
872 * Because hardware always access register in little-endian mode based on hns3
873 * network engine, so driver should also call rte_cpu_to_le_32 to convert data
874 * in little-endian mode before writing register and call rte_le_to_cpu_32 to
875 * convert data after reading from register.
877 * Here the driver encapsulates the data conversion operation in the register
878 * read/write operation function as below:
882 * Therefore, when calling these functions, conversion is not required again.
884 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value)
886 rte_write32(rte_cpu_to_le_32(value),
887 (volatile void *)((char *)base + reg));
891 * The optimized function for writing registers used in the '.rx_pkt_burst' and
892 * '.tx_pkt_burst' ops implementation function.
894 static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value)
897 rte_write32_relaxed(rte_cpu_to_le_32(value), addr);
900 static inline uint32_t hns3_read_reg(void *base, uint32_t reg)
902 uint32_t read_val = rte_read32((volatile void *)((char *)base + reg));
903 return rte_le_to_cpu_32(read_val);
906 #define hns3_write_dev(a, reg, value) \
907 hns3_write_reg((a)->io_base, (reg), (value))
909 #define hns3_read_dev(a, reg) \
910 hns3_read_reg((a)->io_base, (reg))
912 #define ARRAY_SIZE(x) RTE_DIM(x)
914 #define NEXT_ITEM_OF_ACTION(act, actions, index) \
916 act = (actions) + (index); \
917 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \
919 act = actions + index; \
923 #define MSEC_PER_SEC 1000L
924 #define USEC_PER_MSEC 1000L
926 static inline uint64_t
927 get_timeofday_ms(void)
931 (void)gettimeofday(&tv, NULL);
933 return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC;
936 static inline uint64_t
937 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr)
941 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0;
946 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr)
948 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED);
952 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr)
954 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED);
957 static inline int64_t
958 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr)
960 uint64_t mask = (1UL << nr);
962 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask;
965 int hns3_buffer_alloc(struct hns3_hw *hw);
966 int hns3_dev_filter_ctrl(struct rte_eth_dev *dev,
967 enum rte_filter_type filter_type,
968 enum rte_filter_op filter_op, void *arg);
969 bool hns3_is_reset_pending(struct hns3_adapter *hns);
970 bool hns3vf_is_reset_pending(struct hns3_adapter *hns);
971 void hns3_update_link_status_and_event(struct hns3_hw *hw);
972 void hns3_ether_format_addr(char *buf, uint16_t size,
973 const struct rte_ether_addr *ether_addr);
974 int hns3_dev_infos_get(struct rte_eth_dev *eth_dev,
975 struct rte_eth_dev_info *info);
976 void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
977 uint32_t link_speed, uint8_t link_duplex);
980 is_reset_pending(struct hns3_adapter *hns)
984 ret = hns3vf_is_reset_pending(hns);
986 ret = hns3_is_reset_pending(hns);
990 static inline uint64_t
991 hns3_txvlan_cap_get(struct hns3_hw *hw)
993 if (hw->port_base_vlan_cfg.state)
994 return DEV_TX_OFFLOAD_VLAN_INSERT;
996 return DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT;
999 #endif /* _HNS3_ETHDEV_H_ */