1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
6 #include <rte_cycles.h>
7 #include <rte_ethdev.h>
9 #include <rte_malloc.h>
11 #include "hns3_ethdev.h"
12 #include "hns3_logs.h"
13 #include "hns3_intr.h"
14 #include "hns3_regs.h"
15 #include "hns3_rxtx.h"
17 #define SWITCH_CONTEXT_US 10
19 #define HNS3_CHECK_MERGE_CNT(val) \
22 hw->reset.stats.merge_cnt++; \
25 static const char *reset_string[HNS3_MAX_RESET] = {
26 "none", "vf_func", "vf_pf_func", "vf_full", "flr",
27 "vf_global", "pf_func", "global", "IMP",
30 static const struct hns3_hw_error mac_afifo_tnl_int[] = {
32 .msg = "egu_cge_afifo_ecc_1bit_err",
33 .reset_level = HNS3_NONE_RESET },
35 .msg = "egu_cge_afifo_ecc_mbit_err",
36 .reset_level = HNS3_GLOBAL_RESET },
38 .msg = "egu_lge_afifo_ecc_1bit_err",
39 .reset_level = HNS3_NONE_RESET },
41 .msg = "egu_lge_afifo_ecc_mbit_err",
42 .reset_level = HNS3_GLOBAL_RESET },
44 .msg = "cge_igu_afifo_ecc_1bit_err",
45 .reset_level = HNS3_NONE_RESET },
47 .msg = "cge_igu_afifo_ecc_mbit_err",
48 .reset_level = HNS3_GLOBAL_RESET },
50 .msg = "lge_igu_afifo_ecc_1bit_err",
51 .reset_level = HNS3_NONE_RESET },
53 .msg = "lge_igu_afifo_ecc_mbit_err",
54 .reset_level = HNS3_GLOBAL_RESET },
56 .msg = "cge_igu_afifo_overflow_err",
57 .reset_level = HNS3_GLOBAL_RESET },
59 .msg = "lge_igu_afifo_overflow_err",
60 .reset_level = HNS3_GLOBAL_RESET },
62 .msg = "egu_cge_afifo_underrun_err",
63 .reset_level = HNS3_GLOBAL_RESET },
65 .msg = "egu_lge_afifo_underrun_err",
66 .reset_level = HNS3_GLOBAL_RESET },
68 .msg = "egu_ge_afifo_underrun_err",
69 .reset_level = HNS3_GLOBAL_RESET },
71 .msg = "ge_igu_afifo_overflow_err",
72 .reset_level = HNS3_GLOBAL_RESET },
75 .reset_level = HNS3_NONE_RESET}
78 static const struct hns3_hw_error ppu_mpf_abnormal_int_st1[] = {
79 { .int_msk = 0xFFFFFFFF,
80 .msg = "rpu_rx_pkt_ecc_mbit_err",
81 .reset_level = HNS3_GLOBAL_RESET },
84 .reset_level = HNS3_NONE_RESET}
87 static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_ras[] = {
89 .msg = "rpu_rx_pkt_bit32_ecc_mbit_err",
90 .reset_level = HNS3_GLOBAL_RESET },
92 .msg = "rpu_rx_pkt_bit33_ecc_mbit_err",
93 .reset_level = HNS3_GLOBAL_RESET },
95 .msg = "rpu_rx_pkt_bit34_ecc_mbit_err",
96 .reset_level = HNS3_GLOBAL_RESET },
98 .msg = "rpu_rx_pkt_bit35_ecc_mbit_err",
99 .reset_level = HNS3_GLOBAL_RESET },
100 { .int_msk = BIT(17),
101 .msg = "rcb_tx_ring_ecc_mbit_err",
102 .reset_level = HNS3_GLOBAL_RESET },
103 { .int_msk = BIT(18),
104 .msg = "rcb_rx_ring_ecc_mbit_err",
105 .reset_level = HNS3_GLOBAL_RESET },
106 { .int_msk = BIT(19),
107 .msg = "rcb_tx_fbd_ecc_mbit_err",
108 .reset_level = HNS3_GLOBAL_RESET },
109 { .int_msk = BIT(20),
110 .msg = "rcb_rx_ebd_ecc_mbit_err",
111 .reset_level = HNS3_GLOBAL_RESET },
112 { .int_msk = BIT(21),
113 .msg = "rcb_tso_info_ecc_mbit_err",
114 .reset_level = HNS3_GLOBAL_RESET },
115 { .int_msk = BIT(22),
116 .msg = "rcb_tx_int_info_ecc_mbit_err",
117 .reset_level = HNS3_GLOBAL_RESET },
118 { .int_msk = BIT(23),
119 .msg = "rcb_rx_int_info_ecc_mbit_err",
120 .reset_level = HNS3_GLOBAL_RESET },
121 { .int_msk = BIT(24),
122 .msg = "tpu_tx_pkt_0_ecc_mbit_err",
123 .reset_level = HNS3_GLOBAL_RESET },
124 { .int_msk = BIT(25),
125 .msg = "tpu_tx_pkt_1_ecc_mbit_err",
126 .reset_level = HNS3_GLOBAL_RESET },
127 { .int_msk = BIT(26),
129 .reset_level = HNS3_GLOBAL_RESET },
130 { .int_msk = BIT(27),
132 .reset_level = HNS3_GLOBAL_RESET },
133 { .int_msk = BIT(30),
134 .msg = "ooo_ecc_err_detect",
135 .reset_level = HNS3_NONE_RESET },
136 { .int_msk = BIT(31),
137 .msg = "ooo_ecc_err_multpl",
138 .reset_level = HNS3_GLOBAL_RESET },
141 .reset_level = HNS3_NONE_RESET}
144 static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_msix[] = {
145 { .int_msk = BIT(29),
146 .msg = "rx_q_search_miss",
147 .reset_level = HNS3_NONE_RESET },
150 .reset_level = HNS3_NONE_RESET}
153 static const struct hns3_hw_error ssu_port_based_pf_int[] = {
155 .msg = "roc_pkt_without_key_port",
156 .reset_level = HNS3_GLOBAL_RESET },
158 .msg = "low_water_line_err_port",
159 .reset_level = HNS3_NONE_RESET },
162 .reset_level = HNS3_NONE_RESET}
165 static const struct hns3_hw_error ppp_pf_abnormal_int[] = {
167 .msg = "tx_vlan_tag_err",
168 .reset_level = HNS3_NONE_RESET },
170 .msg = "rss_list_tc_unassigned_queue_err",
171 .reset_level = HNS3_NONE_RESET },
174 .reset_level = HNS3_NONE_RESET}
177 static const struct hns3_hw_error ppu_pf_abnormal_int_ras[] = {
179 .msg = "tx_rd_fbd_poison",
180 .reset_level = HNS3_FUNC_RESET },
182 .msg = "rx_rd_ebd_poison",
183 .reset_level = HNS3_FUNC_RESET },
186 .reset_level = HNS3_NONE_RESET}
189 static const struct hns3_hw_error ppu_pf_abnormal_int_msix[] = {
191 .msg = "over_8bd_no_fe",
192 .reset_level = HNS3_FUNC_RESET },
194 .msg = "tso_mss_cmp_min_err",
195 .reset_level = HNS3_NONE_RESET },
197 .msg = "tso_mss_cmp_max_err",
198 .reset_level = HNS3_NONE_RESET },
200 .msg = "buf_wait_timeout",
201 .reset_level = HNS3_NONE_RESET },
204 .reset_level = HNS3_NONE_RESET}
207 static const struct hns3_hw_error imp_tcm_ecc_int[] = {
209 .msg = "imp_itcm0_ecc_mbit_err",
210 .reset_level = HNS3_NONE_RESET },
212 .msg = "imp_itcm1_ecc_mbit_err",
213 .reset_level = HNS3_NONE_RESET },
215 .msg = "imp_itcm2_ecc_mbit_err",
216 .reset_level = HNS3_NONE_RESET },
218 .msg = "imp_itcm3_ecc_mbit_err",
219 .reset_level = HNS3_NONE_RESET },
221 .msg = "imp_dtcm0_mem0_ecc_mbit_err",
222 .reset_level = HNS3_NONE_RESET },
223 { .int_msk = BIT(11),
224 .msg = "imp_dtcm0_mem1_ecc_mbit_err",
225 .reset_level = HNS3_NONE_RESET },
226 { .int_msk = BIT(13),
227 .msg = "imp_dtcm1_mem0_ecc_mbit_err",
228 .reset_level = HNS3_NONE_RESET },
229 { .int_msk = BIT(15),
230 .msg = "imp_dtcm1_mem1_ecc_mbit_err",
231 .reset_level = HNS3_NONE_RESET },
232 { .int_msk = BIT(17),
233 .msg = "imp_itcm4_ecc_mbit_err",
234 .reset_level = HNS3_NONE_RESET },
237 .reset_level = HNS3_NONE_RESET}
240 static const struct hns3_hw_error cmdq_mem_ecc_int[] = {
242 .msg = "cmdq_nic_rx_depth_ecc_mbit_err",
243 .reset_level = HNS3_NONE_RESET },
245 .msg = "cmdq_nic_tx_depth_ecc_mbit_err",
246 .reset_level = HNS3_NONE_RESET },
248 .msg = "cmdq_nic_rx_tail_ecc_mbit_err",
249 .reset_level = HNS3_NONE_RESET },
251 .msg = "cmdq_nic_tx_tail_ecc_mbit_err",
252 .reset_level = HNS3_NONE_RESET },
254 .msg = "cmdq_nic_rx_head_ecc_mbit_err",
255 .reset_level = HNS3_NONE_RESET },
256 { .int_msk = BIT(11),
257 .msg = "cmdq_nic_tx_head_ecc_mbit_err",
258 .reset_level = HNS3_NONE_RESET },
259 { .int_msk = BIT(13),
260 .msg = "cmdq_nic_rx_addr_ecc_mbit_err",
261 .reset_level = HNS3_NONE_RESET },
262 { .int_msk = BIT(15),
263 .msg = "cmdq_nic_tx_addr_ecc_mbit_err",
264 .reset_level = HNS3_NONE_RESET },
267 .reset_level = HNS3_NONE_RESET}
270 static const struct hns3_hw_error tqp_int_ecc_int[] = {
272 .msg = "tqp_int_cfg_even_ecc_mbit_err",
273 .reset_level = HNS3_NONE_RESET },
275 .msg = "tqp_int_cfg_odd_ecc_mbit_err",
276 .reset_level = HNS3_NONE_RESET },
278 .msg = "tqp_int_ctrl_even_ecc_mbit_err",
279 .reset_level = HNS3_NONE_RESET },
281 .msg = "tqp_int_ctrl_odd_ecc_mbit_err",
282 .reset_level = HNS3_NONE_RESET },
283 { .int_msk = BIT(10),
284 .msg = "tx_queue_scan_int_ecc_mbit_err",
285 .reset_level = HNS3_NONE_RESET },
286 { .int_msk = BIT(11),
287 .msg = "rx_queue_scan_int_ecc_mbit_err",
288 .reset_level = HNS3_NONE_RESET },
291 .reset_level = HNS3_NONE_RESET}
294 static const struct hns3_hw_error imp_rd_poison_int[] = {
296 .msg = "imp_rd_poison_int",
297 .reset_level = HNS3_NONE_RESET },
300 .reset_level = HNS3_NONE_RESET}
303 #define HNS3_SSU_MEM_ECC_ERR(x) \
304 { .int_msk = BIT(x), \
305 .msg = "ssu_mem" #x "_ecc_mbit_err", \
306 .reset_level = HNS3_GLOBAL_RESET }
308 static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = {
309 HNS3_SSU_MEM_ECC_ERR(0),
310 HNS3_SSU_MEM_ECC_ERR(1),
311 HNS3_SSU_MEM_ECC_ERR(2),
312 HNS3_SSU_MEM_ECC_ERR(3),
313 HNS3_SSU_MEM_ECC_ERR(4),
314 HNS3_SSU_MEM_ECC_ERR(5),
315 HNS3_SSU_MEM_ECC_ERR(6),
316 HNS3_SSU_MEM_ECC_ERR(7),
317 HNS3_SSU_MEM_ECC_ERR(8),
318 HNS3_SSU_MEM_ECC_ERR(9),
319 HNS3_SSU_MEM_ECC_ERR(10),
320 HNS3_SSU_MEM_ECC_ERR(11),
321 HNS3_SSU_MEM_ECC_ERR(12),
322 HNS3_SSU_MEM_ECC_ERR(13),
323 HNS3_SSU_MEM_ECC_ERR(14),
324 HNS3_SSU_MEM_ECC_ERR(15),
325 HNS3_SSU_MEM_ECC_ERR(16),
326 HNS3_SSU_MEM_ECC_ERR(17),
327 HNS3_SSU_MEM_ECC_ERR(18),
328 HNS3_SSU_MEM_ECC_ERR(19),
329 HNS3_SSU_MEM_ECC_ERR(20),
330 HNS3_SSU_MEM_ECC_ERR(21),
331 HNS3_SSU_MEM_ECC_ERR(22),
332 HNS3_SSU_MEM_ECC_ERR(23),
333 HNS3_SSU_MEM_ECC_ERR(24),
334 HNS3_SSU_MEM_ECC_ERR(25),
335 HNS3_SSU_MEM_ECC_ERR(26),
336 HNS3_SSU_MEM_ECC_ERR(27),
337 HNS3_SSU_MEM_ECC_ERR(28),
338 HNS3_SSU_MEM_ECC_ERR(29),
339 HNS3_SSU_MEM_ECC_ERR(30),
340 HNS3_SSU_MEM_ECC_ERR(31),
343 .reset_level = HNS3_NONE_RESET}
346 static const struct hns3_hw_error ssu_ecc_multi_bit_int_1[] = {
348 .msg = "ssu_mem32_ecc_mbit_err",
349 .reset_level = HNS3_GLOBAL_RESET },
352 .reset_level = HNS3_NONE_RESET}
355 static const struct hns3_hw_error ssu_common_ecc_int[] = {
357 .msg = "buf_sum_err",
358 .reset_level = HNS3_NONE_RESET },
360 .msg = "ppp_mb_num_err",
361 .reset_level = HNS3_NONE_RESET },
363 .msg = "ppp_mbid_err",
364 .reset_level = HNS3_GLOBAL_RESET },
366 .msg = "ppp_rlt_mac_err",
367 .reset_level = HNS3_GLOBAL_RESET },
369 .msg = "ppp_rlt_host_err",
370 .reset_level = HNS3_GLOBAL_RESET },
372 .msg = "cks_edit_position_err",
373 .reset_level = HNS3_GLOBAL_RESET },
375 .msg = "cks_edit_condition_err",
376 .reset_level = HNS3_GLOBAL_RESET },
378 .msg = "vlan_edit_condition_err",
379 .reset_level = HNS3_GLOBAL_RESET },
381 .msg = "vlan_num_ot_err",
382 .reset_level = HNS3_GLOBAL_RESET },
384 .msg = "vlan_num_in_err",
385 .reset_level = HNS3_GLOBAL_RESET },
388 .reset_level = HNS3_NONE_RESET}
391 static const struct hns3_hw_error igu_int[] = {
393 .msg = "igu_rx_buf0_ecc_mbit_err",
394 .reset_level = HNS3_GLOBAL_RESET },
396 .msg = "igu_rx_buf1_ecc_mbit_err",
397 .reset_level = HNS3_GLOBAL_RESET },
400 .reset_level = HNS3_NONE_RESET}
403 static const struct hns3_hw_error msix_ecc_int[] = {
405 .msg = "msix_nic_ecc_mbit_err",
406 .reset_level = HNS3_NONE_RESET },
409 .reset_level = HNS3_NONE_RESET}
412 static const struct hns3_hw_error ppp_mpf_abnormal_int_st1[] = {
414 .msg = "vf_vlan_ad_mem_ecc_mbit_err",
415 .reset_level = HNS3_GLOBAL_RESET },
417 .msg = "umv_mcast_group_mem_ecc_mbit_err",
418 .reset_level = HNS3_GLOBAL_RESET },
420 .msg = "umv_key_mem0_ecc_mbit_err",
421 .reset_level = HNS3_GLOBAL_RESET },
423 .msg = "umv_key_mem1_ecc_mbit_err",
424 .reset_level = HNS3_GLOBAL_RESET },
426 .msg = "umv_key_mem2_ecc_mbit_err",
427 .reset_level = HNS3_GLOBAL_RESET },
429 .msg = "umv_key_mem3_ecc_mbit_err",
430 .reset_level = HNS3_GLOBAL_RESET },
432 .msg = "umv_ad_mem_ecc_mbit_err",
433 .reset_level = HNS3_GLOBAL_RESET },
435 .msg = "rss_tc_mode_mem_ecc_mbit_err",
436 .reset_level = HNS3_GLOBAL_RESET },
438 .msg = "rss_idt_mem0_ecc_mbit_err",
439 .reset_level = HNS3_GLOBAL_RESET },
441 .msg = "rss_idt_mem1_ecc_mbit_err",
442 .reset_level = HNS3_GLOBAL_RESET },
443 { .int_msk = BIT(10),
444 .msg = "rss_idt_mem2_ecc_mbit_err",
445 .reset_level = HNS3_GLOBAL_RESET },
446 { .int_msk = BIT(11),
447 .msg = "rss_idt_mem3_ecc_mbit_err",
448 .reset_level = HNS3_GLOBAL_RESET },
449 { .int_msk = BIT(12),
450 .msg = "rss_idt_mem4_ecc_mbit_err",
451 .reset_level = HNS3_GLOBAL_RESET },
452 { .int_msk = BIT(13),
453 .msg = "rss_idt_mem5_ecc_mbit_err",
454 .reset_level = HNS3_GLOBAL_RESET },
455 { .int_msk = BIT(14),
456 .msg = "rss_idt_mem6_ecc_mbit_err",
457 .reset_level = HNS3_GLOBAL_RESET },
458 { .int_msk = BIT(15),
459 .msg = "rss_idt_mem7_ecc_mbit_err",
460 .reset_level = HNS3_GLOBAL_RESET },
461 { .int_msk = BIT(16),
462 .msg = "rss_idt_mem8_ecc_mbit_err",
463 .reset_level = HNS3_GLOBAL_RESET },
464 { .int_msk = BIT(17),
465 .msg = "rss_idt_mem9_ecc_mbit_err",
466 .reset_level = HNS3_GLOBAL_RESET },
467 { .int_msk = BIT(18),
468 .msg = "rss_idt_mem10_ecc_m1bit_err",
469 .reset_level = HNS3_GLOBAL_RESET },
470 { .int_msk = BIT(19),
471 .msg = "rss_idt_mem11_ecc_mbit_err",
472 .reset_level = HNS3_GLOBAL_RESET },
473 { .int_msk = BIT(20),
474 .msg = "rss_idt_mem12_ecc_mbit_err",
475 .reset_level = HNS3_GLOBAL_RESET },
476 { .int_msk = BIT(21),
477 .msg = "rss_idt_mem13_ecc_mbit_err",
478 .reset_level = HNS3_GLOBAL_RESET },
479 { .int_msk = BIT(22),
480 .msg = "rss_idt_mem14_ecc_mbit_err",
481 .reset_level = HNS3_GLOBAL_RESET },
482 { .int_msk = BIT(23),
483 .msg = "rss_idt_mem15_ecc_mbit_err",
484 .reset_level = HNS3_GLOBAL_RESET },
485 { .int_msk = BIT(24),
486 .msg = "port_vlan_mem_ecc_mbit_err",
487 .reset_level = HNS3_GLOBAL_RESET },
488 { .int_msk = BIT(25),
489 .msg = "mcast_linear_table_mem_ecc_mbit_err",
490 .reset_level = HNS3_GLOBAL_RESET },
491 { .int_msk = BIT(26),
492 .msg = "mcast_result_mem_ecc_mbit_err",
493 .reset_level = HNS3_GLOBAL_RESET },
494 { .int_msk = BIT(27),
495 .msg = "flow_director_ad_mem0_ecc_mbit_err",
496 .reset_level = HNS3_GLOBAL_RESET },
497 { .int_msk = BIT(28),
498 .msg = "flow_director_ad_mem1_ecc_mbit_err",
499 .reset_level = HNS3_GLOBAL_RESET },
500 { .int_msk = BIT(29),
501 .msg = "rx_vlan_tag_memory_ecc_mbit_err",
502 .reset_level = HNS3_GLOBAL_RESET },
503 { .int_msk = BIT(30),
504 .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err",
505 .reset_level = HNS3_GLOBAL_RESET },
508 .reset_level = HNS3_NONE_RESET}
511 static const struct hns3_hw_error ppp_mpf_abnormal_int_st3[] = {
513 .msg = "hfs_fifo_mem_ecc_mbit_err",
514 .reset_level = HNS3_GLOBAL_RESET },
516 .msg = "rslt_descr_fifo_mem_ecc_mbit_err",
517 .reset_level = HNS3_GLOBAL_RESET },
519 .msg = "tx_vlan_tag_mem_ecc_mbit_err",
520 .reset_level = HNS3_GLOBAL_RESET },
522 .msg = "FD_CN0_memory_ecc_mbit_err",
523 .reset_level = HNS3_GLOBAL_RESET },
525 .msg = "FD_CN1_memory_ecc_mbit_err",
526 .reset_level = HNS3_GLOBAL_RESET },
528 .msg = "GRO_AD_memory_ecc_mbit_err",
529 .reset_level = HNS3_GLOBAL_RESET },
532 .reset_level = HNS3_NONE_RESET}
535 static const struct hns3_hw_error ppu_mpf_abnormal_int_st3[] = {
537 .msg = "gro_bd_ecc_mbit_err",
538 .reset_level = HNS3_GLOBAL_RESET },
540 .msg = "gro_context_ecc_mbit_err",
541 .reset_level = HNS3_GLOBAL_RESET },
543 .msg = "rx_stash_cfg_ecc_mbit_err",
544 .reset_level = HNS3_GLOBAL_RESET },
546 .msg = "axi_rd_fbd_ecc_mbit_err",
547 .reset_level = HNS3_GLOBAL_RESET },
550 .reset_level = HNS3_NONE_RESET}
553 static const struct hns3_hw_error tm_sch_int[] = {
555 .msg = "tm_sch_ecc_mbit_err",
556 .reset_level = HNS3_GLOBAL_RESET },
558 .msg = "tm_sch_port_shap_sub_fifo_wr_err",
559 .reset_level = HNS3_GLOBAL_RESET },
561 .msg = "tm_sch_port_shap_sub_fifo_rd_err",
562 .reset_level = HNS3_GLOBAL_RESET },
564 .msg = "tm_sch_pg_pshap_sub_fifo_wr_err",
565 .reset_level = HNS3_GLOBAL_RESET },
567 .msg = "tm_sch_pg_pshap_sub_fifo_rd_err",
568 .reset_level = HNS3_GLOBAL_RESET },
570 .msg = "tm_sch_pg_cshap_sub_fifo_wr_err",
571 .reset_level = HNS3_GLOBAL_RESET },
573 .msg = "tm_sch_pg_cshap_sub_fifo_rd_err",
574 .reset_level = HNS3_GLOBAL_RESET },
576 .msg = "tm_sch_pri_pshap_sub_fifo_wr_err",
577 .reset_level = HNS3_GLOBAL_RESET },
579 .msg = "tm_sch_pri_pshap_sub_fifo_rd_err",
580 .reset_level = HNS3_GLOBAL_RESET },
581 { .int_msk = BIT(10),
582 .msg = "tm_sch_pri_cshap_sub_fifo_wr_err",
583 .reset_level = HNS3_GLOBAL_RESET },
584 { .int_msk = BIT(11),
585 .msg = "tm_sch_pri_cshap_sub_fifo_rd_err",
586 .reset_level = HNS3_GLOBAL_RESET },
587 { .int_msk = BIT(12),
588 .msg = "tm_sch_port_shap_offset_fifo_wr_err",
589 .reset_level = HNS3_GLOBAL_RESET },
590 { .int_msk = BIT(13),
591 .msg = "tm_sch_port_shap_offset_fifo_rd_err",
592 .reset_level = HNS3_GLOBAL_RESET },
593 { .int_msk = BIT(14),
594 .msg = "tm_sch_pg_pshap_offset_fifo_wr_err",
595 .reset_level = HNS3_GLOBAL_RESET },
596 { .int_msk = BIT(15),
597 .msg = "tm_sch_pg_pshap_offset_fifo_rd_err",
598 .reset_level = HNS3_GLOBAL_RESET },
599 { .int_msk = BIT(16),
600 .msg = "tm_sch_pg_cshap_offset_fifo_wr_err",
601 .reset_level = HNS3_GLOBAL_RESET },
602 { .int_msk = BIT(17),
603 .msg = "tm_sch_pg_cshap_offset_fifo_rd_err",
604 .reset_level = HNS3_GLOBAL_RESET },
605 { .int_msk = BIT(18),
606 .msg = "tm_sch_pri_pshap_offset_fifo_wr_err",
607 .reset_level = HNS3_GLOBAL_RESET },
608 { .int_msk = BIT(19),
609 .msg = "tm_sch_pri_pshap_offset_fifo_rd_err",
610 .reset_level = HNS3_GLOBAL_RESET },
611 { .int_msk = BIT(20),
612 .msg = "tm_sch_pri_cshap_offset_fifo_wr_err",
613 .reset_level = HNS3_GLOBAL_RESET },
614 { .int_msk = BIT(21),
615 .msg = "tm_sch_pri_cshap_offset_fifo_rd_err",
616 .reset_level = HNS3_GLOBAL_RESET },
617 { .int_msk = BIT(22),
618 .msg = "tm_sch_rq_fifo_wr_err",
619 .reset_level = HNS3_GLOBAL_RESET },
620 { .int_msk = BIT(23),
621 .msg = "tm_sch_rq_fifo_rd_err",
622 .reset_level = HNS3_GLOBAL_RESET },
623 { .int_msk = BIT(24),
624 .msg = "tm_sch_nq_fifo_wr_err",
625 .reset_level = HNS3_GLOBAL_RESET },
626 { .int_msk = BIT(25),
627 .msg = "tm_sch_nq_fifo_rd_err",
628 .reset_level = HNS3_GLOBAL_RESET },
629 { .int_msk = BIT(26),
630 .msg = "tm_sch_roce_up_fifo_wr_err",
631 .reset_level = HNS3_GLOBAL_RESET },
632 { .int_msk = BIT(27),
633 .msg = "tm_sch_roce_up_fifo_rd_err",
634 .reset_level = HNS3_GLOBAL_RESET },
635 { .int_msk = BIT(28),
636 .msg = "tm_sch_rcb_byte_fifo_wr_err",
637 .reset_level = HNS3_GLOBAL_RESET },
638 { .int_msk = BIT(29),
639 .msg = "tm_sch_rcb_byte_fifo_rd_err",
640 .reset_level = HNS3_GLOBAL_RESET },
641 { .int_msk = BIT(30),
642 .msg = "tm_sch_ssu_byte_fifo_wr_err",
643 .reset_level = HNS3_GLOBAL_RESET },
644 { .int_msk = BIT(31),
645 .msg = "tm_sch_ssu_byte_fifo_rd_err",
646 .reset_level = HNS3_GLOBAL_RESET },
649 .reset_level = HNS3_NONE_RESET}
652 static const struct hns3_hw_error qcn_fifo_int[] = {
654 .msg = "qcn_shap_gp0_sch_fifo_rd_err",
655 .reset_level = HNS3_GLOBAL_RESET },
657 .msg = "qcn_shap_gp0_sch_fifo_wr_err",
658 .reset_level = HNS3_GLOBAL_RESET },
660 .msg = "qcn_shap_gp1_sch_fifo_rd_err",
661 .reset_level = HNS3_GLOBAL_RESET },
663 .msg = "qcn_shap_gp1_sch_fifo_wr_err",
664 .reset_level = HNS3_GLOBAL_RESET },
666 .msg = "qcn_shap_gp2_sch_fifo_rd_err",
667 .reset_level = HNS3_GLOBAL_RESET },
669 .msg = "qcn_shap_gp2_sch_fifo_wr_err",
670 .reset_level = HNS3_GLOBAL_RESET },
672 .msg = "qcn_shap_gp3_sch_fifo_rd_err",
673 .reset_level = HNS3_GLOBAL_RESET },
675 .msg = "qcn_shap_gp3_sch_fifo_wr_err",
676 .reset_level = HNS3_GLOBAL_RESET },
678 .msg = "qcn_shap_gp0_offset_fifo_rd_err",
679 .reset_level = HNS3_GLOBAL_RESET },
681 .msg = "qcn_shap_gp0_offset_fifo_wr_err",
682 .reset_level = HNS3_GLOBAL_RESET },
683 { .int_msk = BIT(10),
684 .msg = "qcn_shap_gp1_offset_fifo_rd_err",
685 .reset_level = HNS3_GLOBAL_RESET },
686 { .int_msk = BIT(11),
687 .msg = "qcn_shap_gp1_offset_fifo_wr_err",
688 .reset_level = HNS3_GLOBAL_RESET },
689 { .int_msk = BIT(12),
690 .msg = "qcn_shap_gp2_offset_fifo_rd_err",
691 .reset_level = HNS3_GLOBAL_RESET },
692 { .int_msk = BIT(13),
693 .msg = "qcn_shap_gp2_offset_fifo_wr_err",
694 .reset_level = HNS3_GLOBAL_RESET },
695 { .int_msk = BIT(14),
696 .msg = "qcn_shap_gp3_offset_fifo_rd_err",
697 .reset_level = HNS3_GLOBAL_RESET },
698 { .int_msk = BIT(15),
699 .msg = "qcn_shap_gp3_offset_fifo_wr_err",
700 .reset_level = HNS3_GLOBAL_RESET },
701 { .int_msk = BIT(16),
702 .msg = "qcn_byte_info_fifo_rd_err",
703 .reset_level = HNS3_GLOBAL_RESET },
704 { .int_msk = BIT(17),
705 .msg = "qcn_byte_info_fifo_wr_err",
706 .reset_level = HNS3_GLOBAL_RESET },
709 .reset_level = HNS3_NONE_RESET}
712 static const struct hns3_hw_error qcn_ecc_int[] = {
714 .msg = "qcn_byte_mem_ecc_mbit_err",
715 .reset_level = HNS3_GLOBAL_RESET },
717 .msg = "qcn_time_mem_ecc_mbit_err",
718 .reset_level = HNS3_GLOBAL_RESET },
720 .msg = "qcn_fb_mem_ecc_mbit_err",
721 .reset_level = HNS3_GLOBAL_RESET },
723 .msg = "qcn_link_mem_ecc_mbit_err",
724 .reset_level = HNS3_GLOBAL_RESET },
726 .msg = "qcn_rate_mem_ecc_mbit_err",
727 .reset_level = HNS3_GLOBAL_RESET },
728 { .int_msk = BIT(11),
729 .msg = "qcn_tmplt_mem_ecc_mbit_err",
730 .reset_level = HNS3_GLOBAL_RESET },
731 { .int_msk = BIT(13),
732 .msg = "qcn_shap_cfg_mem_ecc_mbit_err",
733 .reset_level = HNS3_GLOBAL_RESET },
734 { .int_msk = BIT(15),
735 .msg = "qcn_gp0_barrel_mem_ecc_mbit_err",
736 .reset_level = HNS3_GLOBAL_RESET },
737 { .int_msk = BIT(17),
738 .msg = "qcn_gp1_barrel_mem_ecc_mbit_err",
739 .reset_level = HNS3_GLOBAL_RESET },
740 { .int_msk = BIT(19),
741 .msg = "qcn_gp2_barrel_mem_ecc_mbit_err",
742 .reset_level = HNS3_GLOBAL_RESET },
743 { .int_msk = BIT(21),
744 .msg = "qcn_gp3_barral_mem_ecc_mbit_err",
745 .reset_level = HNS3_GLOBAL_RESET },
748 .reset_level = HNS3_NONE_RESET}
751 static const struct hns3_hw_error ncsi_ecc_int[] = {
753 .msg = "ncsi_tx_ecc_mbit_err",
754 .reset_level = HNS3_NONE_RESET },
757 .reset_level = HNS3_NONE_RESET}
760 static const struct hns3_hw_error ssu_fifo_overflow_int[] = {
762 .msg = "ig_mac_inf_int",
763 .reset_level = HNS3_GLOBAL_RESET },
765 .msg = "ig_host_inf_int",
766 .reset_level = HNS3_GLOBAL_RESET },
768 .msg = "ig_roc_buf_int",
769 .reset_level = HNS3_GLOBAL_RESET },
771 .msg = "ig_host_data_fifo_int",
772 .reset_level = HNS3_GLOBAL_RESET },
774 .msg = "ig_host_key_fifo_int",
775 .reset_level = HNS3_GLOBAL_RESET },
777 .msg = "tx_qcn_fifo_int",
778 .reset_level = HNS3_GLOBAL_RESET },
780 .msg = "rx_qcn_fifo_int",
781 .reset_level = HNS3_GLOBAL_RESET },
783 .msg = "tx_pf_rd_fifo_int",
784 .reset_level = HNS3_GLOBAL_RESET },
786 .msg = "rx_pf_rd_fifo_int",
787 .reset_level = HNS3_GLOBAL_RESET },
789 .msg = "qm_eof_fifo_int",
790 .reset_level = HNS3_GLOBAL_RESET },
791 { .int_msk = BIT(10),
792 .msg = "mb_rlt_fifo_int",
793 .reset_level = HNS3_GLOBAL_RESET },
794 { .int_msk = BIT(11),
795 .msg = "dup_uncopy_fifo_int",
796 .reset_level = HNS3_GLOBAL_RESET },
797 { .int_msk = BIT(12),
798 .msg = "dup_cnt_rd_fifo_int",
799 .reset_level = HNS3_GLOBAL_RESET },
800 { .int_msk = BIT(13),
801 .msg = "dup_cnt_drop_fifo_int",
802 .reset_level = HNS3_GLOBAL_RESET },
803 { .int_msk = BIT(14),
804 .msg = "dup_cnt_wrb_fifo_int",
805 .reset_level = HNS3_GLOBAL_RESET },
806 { .int_msk = BIT(15),
807 .msg = "host_cmd_fifo_int",
808 .reset_level = HNS3_GLOBAL_RESET },
809 { .int_msk = BIT(16),
810 .msg = "mac_cmd_fifo_int",
811 .reset_level = HNS3_GLOBAL_RESET },
812 { .int_msk = BIT(17),
813 .msg = "host_cmd_bitmap_empty_int",
814 .reset_level = HNS3_GLOBAL_RESET },
815 { .int_msk = BIT(18),
816 .msg = "mac_cmd_bitmap_empty_int",
817 .reset_level = HNS3_GLOBAL_RESET },
818 { .int_msk = BIT(19),
819 .msg = "dup_bitmap_empty_int",
820 .reset_level = HNS3_GLOBAL_RESET },
821 { .int_msk = BIT(20),
822 .msg = "out_queue_bitmap_empty_int",
823 .reset_level = HNS3_GLOBAL_RESET },
824 { .int_msk = BIT(21),
825 .msg = "bank2_bitmap_empty_int",
826 .reset_level = HNS3_GLOBAL_RESET },
827 { .int_msk = BIT(22),
828 .msg = "bank1_bitmap_empty_int",
829 .reset_level = HNS3_GLOBAL_RESET },
830 { .int_msk = BIT(23),
831 .msg = "bank0_bitmap_empty_int",
832 .reset_level = HNS3_GLOBAL_RESET },
835 .reset_level = HNS3_NONE_RESET}
838 static const struct hns3_hw_error ssu_ets_tcg_int[] = {
840 .msg = "ets_rd_int_rx_tcg",
841 .reset_level = HNS3_GLOBAL_RESET },
843 .msg = "ets_wr_int_rx_tcg",
844 .reset_level = HNS3_GLOBAL_RESET },
846 .msg = "ets_rd_int_tx_tcg",
847 .reset_level = HNS3_GLOBAL_RESET },
849 .msg = "ets_wr_int_tx_tcg",
850 .reset_level = HNS3_GLOBAL_RESET },
853 .reset_level = HNS3_NONE_RESET}
856 static const struct hns3_hw_error igu_egu_tnl_int[] = {
858 .msg = "rx_buf_overflow",
859 .reset_level = HNS3_GLOBAL_RESET },
861 .msg = "rx_stp_fifo_overflow",
862 .reset_level = HNS3_GLOBAL_RESET },
864 .msg = "rx_stp_fifo_underflow",
865 .reset_level = HNS3_GLOBAL_RESET },
867 .msg = "tx_buf_overflow",
868 .reset_level = HNS3_GLOBAL_RESET },
870 .msg = "tx_buf_underrun",
871 .reset_level = HNS3_GLOBAL_RESET },
873 .msg = "rx_stp_buf_overflow",
874 .reset_level = HNS3_GLOBAL_RESET },
877 .reset_level = HNS3_NONE_RESET}
880 static const struct hns3_hw_error ssu_port_based_err_int[] = {
882 .msg = "roc_pkt_without_key_port",
883 .reset_level = HNS3_FUNC_RESET },
885 .msg = "tpu_pkt_without_key_port",
886 .reset_level = HNS3_GLOBAL_RESET },
888 .msg = "igu_pkt_without_key_port",
889 .reset_level = HNS3_GLOBAL_RESET },
891 .msg = "roc_eof_mis_match_port",
892 .reset_level = HNS3_GLOBAL_RESET },
894 .msg = "tpu_eof_mis_match_port",
895 .reset_level = HNS3_GLOBAL_RESET },
897 .msg = "igu_eof_mis_match_port",
898 .reset_level = HNS3_GLOBAL_RESET },
900 .msg = "roc_sof_mis_match_port",
901 .reset_level = HNS3_GLOBAL_RESET },
903 .msg = "tpu_sof_mis_match_port",
904 .reset_level = HNS3_GLOBAL_RESET },
906 .msg = "igu_sof_mis_match_port",
907 .reset_level = HNS3_GLOBAL_RESET },
908 { .int_msk = BIT(11),
909 .msg = "ets_rd_int_rx_port",
910 .reset_level = HNS3_GLOBAL_RESET },
911 { .int_msk = BIT(12),
912 .msg = "ets_wr_int_rx_port",
913 .reset_level = HNS3_GLOBAL_RESET },
914 { .int_msk = BIT(13),
915 .msg = "ets_rd_int_tx_port",
916 .reset_level = HNS3_GLOBAL_RESET },
917 { .int_msk = BIT(14),
918 .msg = "ets_wr_int_tx_port",
919 .reset_level = HNS3_GLOBAL_RESET },
922 .reset_level = HNS3_NONE_RESET}
925 static const struct hns3_hw_error_desc mpf_ras_err_tbl[] = {
928 .msg = "IMP_TCM_ECC_INT_STS",
929 .hw_err = imp_tcm_ecc_int },
932 .msg = "CMDQ_MEM_ECC_INT_STS",
933 .hw_err = cmdq_mem_ecc_int },
936 .msg = "IMP_RD_POISON_INT_STS",
937 .hw_err = imp_rd_poison_int },
940 .msg = "TQP_INT_ECC_INT_STS",
941 .hw_err = tqp_int_ecc_int },
944 .msg = "MSIX_ECC_INT_STS",
945 .hw_err = msix_ecc_int },
948 .msg = "SSU_ECC_MULTI_BIT_INT_0",
949 .hw_err = ssu_ecc_multi_bit_int_0 },
952 .msg = "SSU_ECC_MULTI_BIT_INT_1",
953 .hw_err = ssu_ecc_multi_bit_int_1 },
956 .msg = "SSU_COMMON_ERR_INT",
957 .hw_err = ssu_common_ecc_int },
960 .msg = "IGU_INT_STS",
964 .msg = "PPP_MPF_ABNORMAL_INT_ST1",
965 .hw_err = ppp_mpf_abnormal_int_st1 },
968 .msg = "PPP_MPF_ABNORMAL_INT_ST3",
969 .hw_err = ppp_mpf_abnormal_int_st3 },
972 .msg = "PPU_MPF_ABNORMAL_INT_ST1",
973 .hw_err = ppu_mpf_abnormal_int_st1 },
976 .msg = "PPU_MPF_ABNORMAL_INT_ST2_RAS",
977 .hw_err = ppu_mpf_abnormal_int_st2_ras },
980 .msg = "PPU_MPF_ABNORMAL_INT_ST3",
981 .hw_err = ppu_mpf_abnormal_int_st3 },
984 .msg = "TM_SCH_RINT",
985 .hw_err = tm_sch_int },
988 .msg = "QCN_FIFO_RINT",
989 .hw_err = qcn_fifo_int },
992 .msg = "QCN_ECC_RINT",
993 .hw_err = qcn_ecc_int },
996 .msg = "NCSI_ECC_INT_RPT",
997 .hw_err = ncsi_ecc_int },
1004 static const struct hns3_hw_error_desc pf_ras_err_tbl[] = {
1007 .msg = "SSU_PORT_BASED_ERR_INT_RAS",
1008 .hw_err = ssu_port_based_err_int },
1011 .msg = "SSU_FIFO_OVERFLOW_INT",
1012 .hw_err = ssu_fifo_overflow_int },
1015 .msg = "SSU_ETS_TCG_INT",
1016 .hw_err = ssu_ets_tcg_int },
1019 .msg = "IGU_EGU_TNL_INT_STS",
1020 .hw_err = igu_egu_tnl_int },
1023 .msg = "PPU_PF_ABNORMAL_INT_ST_RAS",
1024 .hw_err = ppu_pf_abnormal_int_ras },
1031 static const struct hns3_hw_error_desc mpf_msix_err_tbl[] = {
1034 .msg = "MAC_AFIFO_TNL_INT_R",
1035 .hw_err = mac_afifo_tnl_int },
1038 .msg = "PPU_MPF_ABNORMAL_INT_ST2_MSIX",
1039 .hw_err = ppu_mpf_abnormal_int_st2_msix },
1046 static const struct hns3_hw_error_desc pf_msix_err_tbl[] = {
1049 .msg = "SSU_PORT_BASED_ERR_INT_MSIX",
1050 .hw_err = ssu_port_based_pf_int },
1053 .msg = "PPP_PF_ABNORMAL_INT_ST0",
1054 .hw_err = ppp_pf_abnormal_int },
1057 .msg = "PPU_PF_ABNORMAL_INT_ST_MSIX",
1058 .hw_err = ppu_pf_abnormal_int_msix },
1065 enum hns3_hw_err_type {
1073 hns3_config_ncsi_hw_err_int(struct hns3_adapter *hns, bool en)
1075 struct hns3_hw *hw = &hns->hw;
1076 struct hns3_cmd_desc desc;
1079 /* configure NCSI error interrupts */
1080 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_NCSI_INT_EN, false);
1082 desc.data[0] = rte_cpu_to_le_32(HNS3_NCSI_ERR_INT_EN);
1084 ret = hns3_cmd_send(hw, &desc, 1);
1086 hns3_err(hw, "fail to %s NCSI error interrupts, ret = %d",
1087 en ? "enable" : "disable", ret);
1093 enable_igu_egu_err_intr(struct hns3_adapter *hns, bool en)
1095 struct hns3_hw *hw = &hns->hw;
1096 struct hns3_cmd_desc desc;
1099 /* configure IGU,EGU error interrupts */
1100 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_IGU_COMMON_INT_EN, false);
1102 desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_ENABLE);
1104 desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_DISABLE);
1106 desc.data[1] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_EN_MASK);
1108 ret = hns3_cmd_send(hw, &desc, 1);
1110 hns3_err(hw, "fail to %s IGU common interrupts, ret = %d",
1111 en ? "enable" : "disable", ret);
1115 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_IGU_EGU_TNL_INT_EN, false);
1117 desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_TNL_ERR_INT_EN);
1119 desc.data[1] = rte_cpu_to_le_32(HNS3_IGU_TNL_ERR_INT_EN_MASK);
1121 ret = hns3_cmd_send(hw, &desc, 1);
1123 hns3_err(hw, "fail to %s IGU-EGU TNL interrupts, ret = %d",
1124 en ? "enable" : "disable", ret);
1128 return hns3_config_ncsi_hw_err_int(hns, en);
1132 config_ppp_err_intr(struct hns3_adapter *hns, uint32_t cmd, bool en)
1134 struct hns3_hw *hw = &hns->hw;
1135 struct hns3_cmd_desc desc[2];
1138 /* configure PPP error interrupts */
1139 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
1140 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1141 hns3_cmd_setup_basic_desc(&desc[1], cmd, false);
1143 if (cmd == HNS3_OPC_PPP_CMD0_INT_CMD) {
1146 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN);
1148 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN);
1150 rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN);
1154 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN_MASK);
1156 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN_MASK);
1158 rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN_MASK);
1159 } else if (cmd == HNS3_OPC_PPP_CMD1_INT_CMD) {
1162 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN);
1164 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN);
1168 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN_MASK);
1170 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN_MASK);
1173 ret = hns3_cmd_send(hw, &desc[0], 2);
1175 hns3_err(hw, "fail to %s PPP error int, ret = %d",
1176 en ? "enable" : "disable", ret);
1182 enable_ppp_err_intr(struct hns3_adapter *hns, bool en)
1186 ret = config_ppp_err_intr(hns, HNS3_OPC_PPP_CMD0_INT_CMD, en);
1190 return config_ppp_err_intr(hns, HNS3_OPC_PPP_CMD1_INT_CMD, en);
1194 enable_ssu_err_intr(struct hns3_adapter *hns, bool en)
1196 struct hns3_hw *hw = &hns->hw;
1197 struct hns3_cmd_desc desc[2];
1200 /* configure SSU ecc error interrupts */
1201 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_SSU_ECC_INT_CMD, false);
1202 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1203 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_SSU_ECC_INT_CMD, false);
1206 rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN);
1208 rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN);
1210 rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN);
1213 desc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN_MASK);
1215 rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK);
1216 desc[1].data[2] = rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN_MASK);
1218 ret = hns3_cmd_send(hw, &desc[0], 2);
1220 hns3_err(hw, "fail to %s SSU ECC error interrupt, ret = %d",
1221 en ? "enable" : "disable", ret);
1225 /* configure SSU common error interrupts */
1226 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_SSU_COMMON_INT_CMD, false);
1227 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1228 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_SSU_COMMON_INT_CMD, false);
1231 desc[0].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN);
1233 rte_cpu_to_le_32(HNS3_SSU_PORT_BASED_ERR_INT_EN);
1235 rte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN);
1238 desc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN_MASK |
1239 HNS3_SSU_PORT_BASED_ERR_INT_EN_MASK);
1241 rte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK);
1243 ret = hns3_cmd_send(hw, &desc[0], 2);
1245 hns3_err(hw, "fail to %s SSU COMMON error intr, ret = %d",
1246 en ? "enable" : "disable", ret);
1252 hns3_config_mac_tnl_int(struct hns3_hw *hw, bool en)
1254 struct hns3_cmd_desc desc;
1257 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_TNL_INT_EN, false);
1259 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_EN);
1263 desc.data[1] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_EN_MASK);
1265 ret = hns3_cmd_send(hw, &desc, 1);
1267 hns3_err(hw, "fail to %s mac tnl intr, ret = %d",
1268 en ? "enable" : "disable", ret);
1272 config_ppu_err_intrs(struct hns3_adapter *hns, uint32_t cmd, bool en)
1274 struct hns3_hw *hw = &hns->hw;
1275 struct hns3_cmd_desc desc[2];
1278 /* configure PPU error interrupts */
1280 case HNS3_OPC_PPU_MPF_ECC_INT_CMD:
1281 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
1282 desc[0].flag |= HNS3_CMD_FLAG_NEXT;
1283 hns3_cmd_setup_basic_desc(&desc[1], cmd, false);
1285 desc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN;
1286 desc[0].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN;
1287 desc[1].data[3] = HNS3_PPU_MPF_ABNORMAL_INT3_EN;
1288 desc[1].data[4] = HNS3_PPU_MPF_ABNORMAL_INT2_EN;
1291 desc[1].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN_MASK;
1292 desc[1].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN_MASK;
1293 desc[1].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN_MASK;
1294 desc[1].data[3] |= HNS3_PPU_MPF_ABNORMAL_INT3_EN_MASK;
1297 case HNS3_OPC_PPU_MPF_OTHER_INT_CMD:
1298 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
1300 desc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2;
1302 desc[0].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2_MASK;
1304 case HNS3_OPC_PPU_PF_OTHER_INT_CMD:
1305 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
1307 desc[0].data[0] = HNS3_PPU_PF_ABNORMAL_INT_EN;
1309 desc[0].data[2] = HNS3_PPU_PF_ABNORMAL_INT_EN_MASK;
1313 "Invalid cmd(%u) to configure PPU error interrupts.",
1318 return hns3_cmd_send(hw, &desc[0], num);
1322 enable_ppu_err_intr(struct hns3_adapter *hns, bool en)
1324 struct hns3_hw *hw = &hns->hw;
1327 ret = config_ppu_err_intrs(hns, HNS3_OPC_PPU_MPF_ECC_INT_CMD, en);
1329 hns3_err(hw, "fail to %s PPU MPF ECC error intr, ret = %d",
1330 en ? "enable" : "disable", ret);
1334 ret = config_ppu_err_intrs(hns, HNS3_OPC_PPU_MPF_OTHER_INT_CMD, en);
1336 hns3_err(hw, "fail to %s PPU MPF other intr, ret = %d",
1337 en ? "enable" : "disable", ret);
1341 ret = config_ppu_err_intrs(hns, HNS3_OPC_PPU_PF_OTHER_INT_CMD, en);
1343 hns3_err(hw, "fail to %s PPU PF error interrupts, ret = %d",
1344 en ? "enable" : "disable", ret);
1349 enable_tm_err_intr(struct hns3_adapter *hns, bool en)
1351 struct hns3_hw *hw = &hns->hw;
1352 struct hns3_cmd_desc desc;
1355 /* configure TM SCH error interrupts */
1356 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_SCH_ECC_INT_EN, false);
1358 desc.data[0] = rte_cpu_to_le_32(HNS3_TM_SCH_ECC_ERR_INT_EN);
1360 ret = hns3_cmd_send(hw, &desc, 1);
1362 hns3_err(hw, "fail to %s TM SCH interrupts, ret = %d",
1363 en ? "enable" : "disable", ret);
1367 /* configure TM QCN hw errors */
1368 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QCN_MEM_INT_CFG, true);
1369 ret = hns3_cmd_send(hw, &desc, 1);
1371 hns3_err(hw, "fail to read TM QCN CFG status, ret = %d\n", ret);
1375 hns3_cmd_reuse_desc(&desc, false);
1377 desc.data[1] = rte_cpu_to_le_32(HNS3_TM_QCN_MEM_ERR_INT_EN);
1379 ret = hns3_cmd_send(hw, &desc, 1);
1381 hns3_err(hw, "fail to %s TM QCN mem errors, ret = %d\n",
1382 en ? "enable" : "disable", ret);
1388 enable_common_err_intr(struct hns3_adapter *hns, bool en)
1390 struct hns3_hw *hw = &hns->hw;
1391 struct hns3_cmd_desc desc[2];
1394 /* configure common error interrupts */
1395 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_COMMON_ECC_INT_CFG, false);
1396 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1397 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_COMMON_ECC_INT_CFG, false);
1401 rte_cpu_to_le_32(HNS3_IMP_TCM_ECC_ERR_INT_EN);
1403 rte_cpu_to_le_32(HNS3_CMDQ_NIC_ECC_ERR_INT_EN);
1405 rte_cpu_to_le_32(HNS3_IMP_RD_POISON_ERR_INT_EN);
1407 rte_cpu_to_le_32(HNS3_TQP_ECC_ERR_INT_EN |
1408 HNS3_MSIX_SRAM_ECC_ERR_INT_EN);
1410 rte_cpu_to_le_32(HNS3_IMP_ITCM4_ECC_ERR_INT_EN);
1413 desc[1].data[0] = rte_cpu_to_le_32(HNS3_IMP_TCM_ECC_ERR_INT_EN_MASK);
1414 desc[1].data[2] = rte_cpu_to_le_32(HNS3_CMDQ_NIC_ECC_ERR_INT_EN_MASK);
1415 desc[1].data[3] = rte_cpu_to_le_32(HNS3_IMP_RD_POISON_ERR_INT_EN_MASK);
1416 desc[1].data[4] = rte_cpu_to_le_32(HNS3_TQP_ECC_ERR_INT_EN_MASK |
1417 HNS3_MSIX_SRAM_ECC_ERR_INT_EN_MASK);
1418 desc[1].data[5] = rte_cpu_to_le_32(HNS3_IMP_ITCM4_ECC_ERR_INT_EN_MASK);
1420 ret = hns3_cmd_send(hw, &desc[0], RTE_DIM(desc));
1422 hns3_err(hw, "fail to %s common err interrupts, ret = %d\n",
1423 en ? "enable" : "disable", ret);
1429 enable_mac_err_intr(struct hns3_adapter *hns, bool en)
1431 struct hns3_hw *hw = &hns->hw;
1432 struct hns3_cmd_desc desc;
1435 /* configure MAC common error interrupts */
1436 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_COMMON_INT_EN, false);
1438 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN);
1440 desc.data[1] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN_MASK);
1442 ret = hns3_cmd_send(hw, &desc, 1);
1444 hns3_err(hw, "fail to %s MAC COMMON error intr: %d",
1445 en ? "enable" : "disable", ret);
1450 static const struct hns3_hw_blk hw_blk[] = {
1453 .enable_err_intr = enable_igu_egu_err_intr,
1457 .enable_err_intr = enable_ppp_err_intr,
1461 .enable_err_intr = enable_ssu_err_intr,
1465 .enable_err_intr = enable_ppu_err_intr,
1469 .enable_err_intr = enable_tm_err_intr,
1473 .enable_err_intr = enable_common_err_intr,
1477 .enable_err_intr = enable_mac_err_intr,
1481 .enable_err_intr = NULL,
1486 hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool en)
1488 const struct hns3_hw_blk *module = hw_blk;
1491 while (module->enable_err_intr) {
1492 ret = module->enable_err_intr(hns, en);
1502 static enum hns3_reset_level
1503 hns3_find_highest_level(struct hns3_adapter *hns, const char *reg,
1504 const struct hns3_hw_error *err, uint32_t err_sts)
1506 enum hns3_reset_level reset_level = HNS3_FUNC_RESET;
1507 struct hns3_hw *hw = &hns->hw;
1508 bool need_reset = false;
1511 if (err->int_msk & err_sts) {
1512 hns3_warn(hw, "%s %s found [error status=0x%x]",
1513 reg, err->msg, err_sts);
1514 if (err->reset_level != HNS3_NONE_RESET &&
1515 err->reset_level >= reset_level) {
1516 reset_level = err->reset_level;
1519 hns3_error_int_stats_add(hns, reg);
1526 return HNS3_NONE_RESET;
1530 query_num_bds(struct hns3_hw *hw, bool is_ras, uint32_t *mpf_bd_num,
1531 uint32_t *pf_bd_num)
1533 uint32_t mpf_min_bd_num, pf_min_bd_num;
1534 uint32_t mpf_bd_num_val, pf_bd_num_val;
1535 enum hns3_opcode_type opcode;
1536 struct hns3_cmd_desc desc;
1540 opcode = HNS3_OPC_QUERY_RAS_INT_STS_BD_NUM;
1541 mpf_min_bd_num = HNS3_MPF_RAS_INT_MIN_BD_NUM;
1542 pf_min_bd_num = HNS3_PF_RAS_INT_MIN_BD_NUM;
1544 opcode = HNS3_OPC_QUERY_MSIX_INT_STS_BD_NUM;
1545 mpf_min_bd_num = HNS3_MPF_MSIX_INT_MIN_BD_NUM;
1546 pf_min_bd_num = HNS3_PF_MSIX_INT_MIN_BD_NUM;
1549 hns3_cmd_setup_basic_desc(&desc, opcode, true);
1550 ret = hns3_cmd_send(hw, &desc, 1);
1552 hns3_err(hw, "query num bds in msix failed, ret = %d", ret);
1556 mpf_bd_num_val = rte_le_to_cpu_32(desc.data[0]);
1557 pf_bd_num_val = rte_le_to_cpu_32(desc.data[1]);
1558 if (mpf_bd_num_val < mpf_min_bd_num || pf_bd_num_val < pf_min_bd_num) {
1559 hns3_err(hw, "error bd num: mpf(%u), min_mpf(%u), "
1560 "pf(%u), min_pf(%u)\n", mpf_bd_num_val, mpf_min_bd_num,
1561 pf_bd_num_val, pf_min_bd_num);
1565 *mpf_bd_num = mpf_bd_num_val;
1566 *pf_bd_num = pf_bd_num_val;
1572 hns3_intr_unregister(const struct rte_intr_handle *hdl,
1573 rte_intr_callback_fn cb_fn, void *cb_arg)
1579 ret = rte_intr_callback_unregister(hdl, cb_fn, cb_arg);
1582 } else if (ret != -EAGAIN) {
1583 PMD_INIT_LOG(ERR, "Failed to unregister intr: %d", ret);
1586 rte_delay_ms(HNS3_INTR_UNREG_FAIL_DELAY_MS);
1587 } while (retry_cnt++ < HNS3_INTR_UNREG_FAIL_RETRY_CNT);
1591 hns3_get_hw_error_status(struct hns3_cmd_desc *desc, uint8_t desc_offset,
1592 uint8_t data_offset)
1595 uint32_t *desc_data;
1597 if (desc_offset == 0)
1598 status = rte_le_to_cpu_32(desc[desc_offset].data[data_offset]);
1600 desc_data = (uint32_t *)&desc[desc_offset];
1601 status = rte_le_to_cpu_32(*(desc_data + data_offset));
1608 hns3_handle_hw_error(struct hns3_adapter *hns, struct hns3_cmd_desc *desc,
1609 int num, uint64_t *levels, enum hns3_hw_err_type err_type)
1611 const struct hns3_hw_error_desc *err = pf_ras_err_tbl;
1612 enum hns3_opcode_type opcode;
1613 enum hns3_reset_level req_level;
1614 struct hns3_hw *hw = &hns->hw;
1620 err = mpf_msix_err_tbl;
1621 opcode = HNS3_OPC_QUERY_CLEAR_ALL_MPF_MSIX_INT;
1624 err = pf_msix_err_tbl;
1625 opcode = HNS3_OPC_QUERY_CLEAR_ALL_PF_MSIX_INT;
1628 err = mpf_ras_err_tbl;
1629 opcode = HNS3_OPC_QUERY_CLEAR_MPF_RAS_INT;
1632 err = pf_ras_err_tbl;
1633 opcode = HNS3_OPC_QUERY_CLEAR_PF_RAS_INT;
1636 hns3_err(hw, "error hardware err_type = %d\n", err_type);
1640 /* query all hardware errors */
1641 hns3_cmd_setup_basic_desc(&desc[0], opcode, true);
1642 ret = hns3_cmd_send(hw, &desc[0], num);
1644 hns3_err(hw, "query hw err int 0x%x cmd failed, ret = %d\n",
1649 /* traverses the error table and process based on the error type */
1651 status = hns3_get_hw_error_status(desc, err->desc_offset,
1655 * set the reset_level or non_reset flag based on
1656 * the error type and add error statistics. here just
1657 * set the flag, the actual reset action is in
1658 * hns3_msix_process.
1660 req_level = hns3_find_highest_level(hns, err->msg,
1663 hns3_atomic_set_bit(req_level, levels);
1668 /* clear all hardware errors */
1669 hns3_cmd_reuse_desc(&desc[0], false);
1670 ret = hns3_cmd_send(hw, &desc[0], num);
1672 hns3_err(hw, "clear all hw err int cmd failed, ret = %d\n",
1679 hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels)
1681 uint32_t mpf_bd_num, pf_bd_num, bd_num;
1682 struct hns3_hw *hw = &hns->hw;
1683 struct hns3_cmd_desc *desc;
1686 /* query the number of bds for the MSIx int status */
1687 ret = query_num_bds(hw, false, &mpf_bd_num, &pf_bd_num);
1689 hns3_err(hw, "fail to query msix int status bd num: ret = %d",
1694 bd_num = RTE_MAX(mpf_bd_num, pf_bd_num);
1695 desc = rte_zmalloc(NULL, bd_num * sizeof(struct hns3_cmd_desc), 0);
1698 "fail to zmalloc desc for handling msix error, size = %zu",
1699 bd_num * sizeof(struct hns3_cmd_desc));
1703 /* handle all main PF MSIx errors */
1704 ret = hns3_handle_hw_error(hns, desc, mpf_bd_num, levels, MPF_MSIX_ERR);
1706 hns3_err(hw, "fail to handle all main pf msix errors, ret = %d",
1711 memset(desc, 0, bd_num * sizeof(struct hns3_cmd_desc));
1713 /* handle all PF MSIx errors */
1714 ret = hns3_handle_hw_error(hns, desc, pf_bd_num, levels, PF_MSIX_ERR);
1716 hns3_err(hw, "fail to handle all pf msix errors, ret = %d",
1726 hns3_handle_ras_error(struct hns3_adapter *hns, uint64_t *levels)
1728 uint32_t mpf_bd_num, pf_bd_num, bd_num;
1729 struct hns3_hw *hw = &hns->hw;
1730 struct hns3_cmd_desc *desc;
1734 status = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
1735 if ((status & HNS3_RAS_REG_NFE_MASK) == 0)
1738 /* query the number of bds for the RAS int status */
1739 ret = query_num_bds(hw, true, &mpf_bd_num, &pf_bd_num);
1741 hns3_err(hw, "fail to query ras int status bd num: ret = %d",
1746 bd_num = RTE_MAX(mpf_bd_num, pf_bd_num);
1747 desc = rte_zmalloc(NULL, bd_num * sizeof(struct hns3_cmd_desc), 0);
1750 "fail to zmalloc desc for handing ras error, size = %zu",
1751 bd_num * sizeof(struct hns3_cmd_desc));
1755 /* handle all main PF RAS errors */
1756 ret = hns3_handle_hw_error(hns, desc, mpf_bd_num, levels, MPF_RAS_ERR);
1758 hns3_err(hw, "fail to handle all main pf ras errors, ret = %d",
1763 memset(desc, 0, bd_num * sizeof(struct hns3_cmd_desc));
1765 /* handle all PF RAS errors */
1766 ret = hns3_handle_hw_error(hns, desc, pf_bd_num, levels, PF_RAS_ERR);
1768 hns3_err(hw, "fail to handle all pf ras errors, ret = %d", ret);
1777 hns3_reset_init(struct hns3_hw *hw)
1779 rte_spinlock_init(&hw->lock);
1780 hw->reset.level = HNS3_NONE_RESET;
1781 hw->reset.stage = RESET_STAGE_NONE;
1782 hw->reset.request = 0;
1783 hw->reset.pending = 0;
1784 hw->reset.resetting = 0;
1785 __atomic_store_n(&hw->reset.disable_cmd, 0, __ATOMIC_RELAXED);
1786 hw->reset.wait_data = rte_zmalloc("wait_data",
1787 sizeof(struct hns3_wait_data), 0);
1788 if (!hw->reset.wait_data) {
1789 PMD_INIT_LOG(ERR, "Failed to allocate memory for wait_data");
1796 hns3_schedule_reset(struct hns3_adapter *hns)
1798 struct hns3_hw *hw = &hns->hw;
1800 /* Reschedule the reset process after successful initialization */
1801 if (hw->adapter_state == HNS3_NIC_UNINITIALIZED) {
1802 __atomic_store_n(&hw->reset.schedule, SCHEDULE_PENDING,
1807 if (hw->adapter_state >= HNS3_NIC_CLOSED)
1810 /* Schedule restart alarm if it is not scheduled yet */
1811 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
1814 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
1816 rte_eal_alarm_cancel(hw->reset.ops->reset_service, hns);
1817 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
1820 rte_eal_alarm_set(SWITCH_CONTEXT_US, hw->reset.ops->reset_service, hns);
1824 hns3_schedule_delayed_reset(struct hns3_adapter *hns)
1826 #define DEFERRED_SCHED_US (3 * MSEC_PER_SEC * USEC_PER_MSEC)
1827 struct hns3_hw *hw = &hns->hw;
1829 /* Do nothing if it is uninited or closed */
1830 if (hw->adapter_state == HNS3_NIC_UNINITIALIZED ||
1831 hw->adapter_state >= HNS3_NIC_CLOSED) {
1835 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) !=
1838 __atomic_store_n(&hw->reset.schedule, SCHEDULE_DEFERRED,
1840 rte_eal_alarm_set(DEFERRED_SCHED_US, hw->reset.ops->reset_service, hns);
1844 hns3_wait_callback(void *param)
1846 struct hns3_wait_data *data = (struct hns3_wait_data *)param;
1847 struct hns3_adapter *hns = data->hns;
1848 struct hns3_hw *hw = &hns->hw;
1853 if (data->check_completion) {
1855 * Check if the current time exceeds the deadline
1856 * or a pending reset coming, or reset during close.
1858 msec = get_timeofday_ms();
1859 if (msec > data->end_ms || is_reset_pending(hns) ||
1860 hw->adapter_state == HNS3_NIC_CLOSING) {
1864 done = data->check_completion(hw);
1868 if (!done && data->count > 0) {
1869 rte_eal_alarm_set(data->interval, hns3_wait_callback, data);
1873 data->result = HNS3_WAIT_SUCCESS;
1875 hns3_err(hw, "%s wait timeout at stage %d",
1876 reset_string[hw->reset.level], hw->reset.stage);
1877 data->result = HNS3_WAIT_TIMEOUT;
1879 hns3_schedule_reset(hns);
1883 hns3_notify_reset_ready(struct hns3_hw *hw, bool enable)
1887 reg_val = hns3_read_dev(hw, HNS3_CMDQ_TX_DEPTH_REG);
1889 reg_val |= HNS3_NIC_SW_RST_RDY;
1891 reg_val &= ~HNS3_NIC_SW_RST_RDY;
1893 hns3_write_dev(hw, HNS3_CMDQ_TX_DEPTH_REG, reg_val);
1897 hns3_reset_req_hw_reset(struct hns3_adapter *hns)
1899 struct hns3_hw *hw = &hns->hw;
1901 if (hw->reset.wait_data->result == HNS3_WAIT_UNKNOWN) {
1902 hw->reset.wait_data->hns = hns;
1903 hw->reset.wait_data->check_completion = NULL;
1904 hw->reset.wait_data->interval = HNS3_RESET_SYNC_US;
1905 hw->reset.wait_data->count = 1;
1906 hw->reset.wait_data->result = HNS3_WAIT_REQUEST;
1907 rte_eal_alarm_set(hw->reset.wait_data->interval,
1908 hns3_wait_callback, hw->reset.wait_data);
1910 } else if (hw->reset.wait_data->result == HNS3_WAIT_REQUEST)
1913 /* inform hardware that preparatory work is done */
1914 hns3_notify_reset_ready(hw, true);
1919 hns3_clear_reset_level(struct hns3_hw *hw, uint64_t *levels)
1921 uint64_t merge_cnt = hw->reset.stats.merge_cnt;
1924 switch (hw->reset.level) {
1925 case HNS3_IMP_RESET:
1926 hns3_atomic_clear_bit(HNS3_IMP_RESET, levels);
1927 tmp = hns3_test_and_clear_bit(HNS3_GLOBAL_RESET, levels);
1928 HNS3_CHECK_MERGE_CNT(tmp);
1929 tmp = hns3_test_and_clear_bit(HNS3_FUNC_RESET, levels);
1930 HNS3_CHECK_MERGE_CNT(tmp);
1932 case HNS3_GLOBAL_RESET:
1933 hns3_atomic_clear_bit(HNS3_GLOBAL_RESET, levels);
1934 tmp = hns3_test_and_clear_bit(HNS3_FUNC_RESET, levels);
1935 HNS3_CHECK_MERGE_CNT(tmp);
1937 case HNS3_FUNC_RESET:
1938 hns3_atomic_clear_bit(HNS3_FUNC_RESET, levels);
1941 hns3_atomic_clear_bit(HNS3_VF_RESET, levels);
1942 tmp = hns3_test_and_clear_bit(HNS3_VF_PF_FUNC_RESET, levels);
1943 HNS3_CHECK_MERGE_CNT(tmp);
1944 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);
1945 HNS3_CHECK_MERGE_CNT(tmp);
1947 case HNS3_VF_FULL_RESET:
1948 hns3_atomic_clear_bit(HNS3_VF_FULL_RESET, levels);
1949 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);
1950 HNS3_CHECK_MERGE_CNT(tmp);
1952 case HNS3_VF_PF_FUNC_RESET:
1953 hns3_atomic_clear_bit(HNS3_VF_PF_FUNC_RESET, levels);
1954 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);
1955 HNS3_CHECK_MERGE_CNT(tmp);
1957 case HNS3_VF_FUNC_RESET:
1958 hns3_atomic_clear_bit(HNS3_VF_FUNC_RESET, levels);
1960 case HNS3_FLR_RESET:
1961 hns3_atomic_clear_bit(HNS3_FLR_RESET, levels);
1963 case HNS3_NONE_RESET:
1967 if (merge_cnt != hw->reset.stats.merge_cnt)
1969 "No need to do low-level reset after %s reset. "
1970 "merge cnt: %" PRIx64 " total merge cnt: %" PRIx64,
1971 reset_string[hw->reset.level],
1972 hw->reset.stats.merge_cnt - merge_cnt,
1973 hw->reset.stats.merge_cnt);
1977 hns3_reset_err_handle(struct hns3_adapter *hns)
1979 #define MAX_RESET_FAIL_CNT 5
1981 struct hns3_hw *hw = &hns->hw;
1983 if (hw->adapter_state == HNS3_NIC_CLOSING)
1986 if (is_reset_pending(hns)) {
1987 hw->reset.attempts = 0;
1988 hw->reset.stats.fail_cnt++;
1989 hns3_warn(hw, "%s reset fail because new Reset is pending "
1990 "attempts:%" PRIx64,
1991 reset_string[hw->reset.level],
1992 hw->reset.stats.fail_cnt);
1993 hw->reset.level = HNS3_NONE_RESET;
1997 hw->reset.attempts++;
1998 if (hw->reset.attempts < MAX_RESET_FAIL_CNT) {
1999 hns3_atomic_set_bit(hw->reset.level, &hw->reset.pending);
2000 hns3_warn(hw, "%s retry to reset attempts: %d",
2001 reset_string[hw->reset.level],
2002 hw->reset.attempts);
2007 * Failure to reset does not mean that the network port is
2008 * completely unavailable, so cmd still needs to be initialized.
2009 * Regardless of whether the execution is successful or not, the
2010 * flow after execution must be continued.
2012 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED))
2013 (void)hns3_cmd_init(hw);
2015 hw->reset.attempts = 0;
2016 hw->reset.stats.fail_cnt++;
2017 hns3_warn(hw, "%s reset fail fail_cnt:%" PRIx64 " success_cnt:%" PRIx64
2018 " global_cnt:%" PRIx64 " imp_cnt:%" PRIx64
2019 " request_cnt:%" PRIx64 " exec_cnt:%" PRIx64
2020 " merge_cnt:%" PRIx64 "adapter_state:%d",
2021 reset_string[hw->reset.level], hw->reset.stats.fail_cnt,
2022 hw->reset.stats.success_cnt, hw->reset.stats.global_cnt,
2023 hw->reset.stats.imp_cnt, hw->reset.stats.request_cnt,
2024 hw->reset.stats.exec_cnt, hw->reset.stats.merge_cnt,
2027 /* IMP no longer waiting the ready flag */
2028 hns3_notify_reset_ready(hw, true);
2033 hns3_reset_pre(struct hns3_adapter *hns)
2035 struct hns3_hw *hw = &hns->hw;
2039 if (hw->reset.stage == RESET_STAGE_NONE) {
2040 __atomic_store_n(&hns->hw.reset.resetting, 1, __ATOMIC_RELAXED);
2041 hw->reset.stage = RESET_STAGE_DOWN;
2042 ret = hw->reset.ops->stop_service(hns);
2043 gettimeofday(&tv, NULL);
2045 hns3_warn(hw, "Reset step1 down fail=%d time=%ld.%.6ld",
2046 ret, tv.tv_sec, tv.tv_usec);
2049 hns3_warn(hw, "Reset step1 down success time=%ld.%.6ld",
2050 tv.tv_sec, tv.tv_usec);
2051 hw->reset.stage = RESET_STAGE_PREWAIT;
2053 if (hw->reset.stage == RESET_STAGE_PREWAIT) {
2054 ret = hw->reset.ops->prepare_reset(hns);
2055 gettimeofday(&tv, NULL);
2058 "Reset step2 prepare wait fail=%d time=%ld.%.6ld",
2059 ret, tv.tv_sec, tv.tv_usec);
2062 hns3_warn(hw, "Reset step2 prepare wait success time=%ld.%.6ld",
2063 tv.tv_sec, tv.tv_usec);
2064 hw->reset.stage = RESET_STAGE_REQ_HW_RESET;
2065 hw->reset.wait_data->result = HNS3_WAIT_UNKNOWN;
2071 hns3_reset_post(struct hns3_adapter *hns)
2073 #define TIMEOUT_RETRIES_CNT 5
2074 struct hns3_hw *hw = &hns->hw;
2075 struct timeval tv_delta;
2079 if (hw->adapter_state == HNS3_NIC_CLOSING) {
2080 hns3_warn(hw, "Don't do reset_post during closing, just uninit cmd");
2081 hns3_cmd_uninit(hw);
2085 if (hw->reset.stage == RESET_STAGE_DEV_INIT) {
2086 rte_spinlock_lock(&hw->lock);
2087 if (hw->reset.mbuf_deferred_free) {
2088 hns3_dev_release_mbufs(hns);
2089 hw->reset.mbuf_deferred_free = false;
2091 ret = hw->reset.ops->reinit_dev(hns);
2092 rte_spinlock_unlock(&hw->lock);
2093 gettimeofday(&tv, NULL);
2095 hns3_warn(hw, "Reset step5 devinit fail=%d retries=%d",
2096 ret, hw->reset.retries);
2099 hns3_warn(hw, "Reset step5 devinit success time=%ld.%.6ld",
2100 tv.tv_sec, tv.tv_usec);
2101 hw->reset.retries = 0;
2102 hw->reset.stage = RESET_STAGE_RESTORE;
2103 rte_eal_alarm_set(SWITCH_CONTEXT_US,
2104 hw->reset.ops->reset_service, hns);
2107 if (hw->reset.stage == RESET_STAGE_RESTORE) {
2108 rte_spinlock_lock(&hw->lock);
2109 ret = hw->reset.ops->restore_conf(hns);
2110 rte_spinlock_unlock(&hw->lock);
2111 gettimeofday(&tv, NULL);
2114 "Reset step6 restore fail=%d retries=%d",
2115 ret, hw->reset.retries);
2118 hns3_warn(hw, "Reset step6 restore success time=%ld.%.6ld",
2119 tv.tv_sec, tv.tv_usec);
2120 hw->reset.retries = 0;
2121 hw->reset.stage = RESET_STAGE_DONE;
2123 if (hw->reset.stage == RESET_STAGE_DONE) {
2124 /* IMP will wait ready flag before reset */
2125 hns3_notify_reset_ready(hw, false);
2126 hns3_clear_reset_level(hw, &hw->reset.pending);
2127 __atomic_store_n(&hns->hw.reset.resetting, 0, __ATOMIC_RELAXED);
2128 hw->reset.attempts = 0;
2129 hw->reset.stats.success_cnt++;
2130 hw->reset.stage = RESET_STAGE_NONE;
2131 rte_spinlock_lock(&hw->lock);
2132 hw->reset.ops->start_service(hns);
2133 rte_spinlock_unlock(&hw->lock);
2134 gettimeofday(&tv, NULL);
2135 timersub(&tv, &hw->reset.start_time, &tv_delta);
2136 hns3_warn(hw, "%s reset done fail_cnt:%" PRIx64
2137 " success_cnt:%" PRIx64 " global_cnt:%" PRIx64
2138 " imp_cnt:%" PRIx64 " request_cnt:%" PRIx64
2139 " exec_cnt:%" PRIx64 " merge_cnt:%" PRIx64,
2140 reset_string[hw->reset.level],
2141 hw->reset.stats.fail_cnt, hw->reset.stats.success_cnt,
2142 hw->reset.stats.global_cnt, hw->reset.stats.imp_cnt,
2143 hw->reset.stats.request_cnt, hw->reset.stats.exec_cnt,
2144 hw->reset.stats.merge_cnt);
2146 "%s reset done delta %ld ms time=%ld.%.6ld",
2147 reset_string[hw->reset.level],
2148 tv_delta.tv_sec * MSEC_PER_SEC +
2149 tv_delta.tv_usec / USEC_PER_MSEC,
2150 tv.tv_sec, tv.tv_usec);
2151 hw->reset.level = HNS3_NONE_RESET;
2156 if (ret == -ETIME) {
2157 hw->reset.retries++;
2158 if (hw->reset.retries < TIMEOUT_RETRIES_CNT) {
2159 rte_eal_alarm_set(HNS3_RESET_SYNC_US,
2160 hw->reset.ops->reset_service, hns);
2164 hw->reset.retries = 0;
2169 * There are three scenarios as follows:
2170 * When the reset is not in progress, the reset process starts.
2171 * During the reset process, if the reset level has not changed,
2172 * the reset process continues; otherwise, the reset process is aborted.
2173 * hw->reset.level new_level action
2174 * HNS3_NONE_RESET HNS3_XXXX_RESET start reset
2175 * HNS3_XXXX_RESET HNS3_XXXX_RESET continue reset
2176 * HNS3_LOW_RESET HNS3_HIGH_RESET abort
2179 hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level)
2181 struct hns3_hw *hw = &hns->hw;
2182 struct timeval tv_delta;
2186 if (hw->reset.level == HNS3_NONE_RESET) {
2187 hw->reset.level = new_level;
2188 hw->reset.stats.exec_cnt++;
2189 gettimeofday(&hw->reset.start_time, NULL);
2190 hns3_warn(hw, "Start %s reset time=%ld.%.6ld",
2191 reset_string[hw->reset.level],
2192 hw->reset.start_time.tv_sec,
2193 hw->reset.start_time.tv_usec);
2196 if (is_reset_pending(hns)) {
2197 gettimeofday(&tv, NULL);
2199 "%s reset is aborted by high level time=%ld.%.6ld",
2200 reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec);
2201 if (hw->reset.wait_data->result == HNS3_WAIT_REQUEST)
2202 rte_eal_alarm_cancel(hns3_wait_callback,
2203 hw->reset.wait_data);
2207 ret = hns3_reset_pre(hns);
2211 if (hw->reset.stage == RESET_STAGE_REQ_HW_RESET) {
2212 ret = hns3_reset_req_hw_reset(hns);
2215 gettimeofday(&tv, NULL);
2217 "Reset step3 request IMP reset success time=%ld.%.6ld",
2218 tv.tv_sec, tv.tv_usec);
2219 hw->reset.stage = RESET_STAGE_WAIT;
2220 hw->reset.wait_data->result = HNS3_WAIT_UNKNOWN;
2222 if (hw->reset.stage == RESET_STAGE_WAIT) {
2223 ret = hw->reset.ops->wait_hardware_ready(hns);
2226 gettimeofday(&tv, NULL);
2227 hns3_warn(hw, "Reset step4 reset wait success time=%ld.%.6ld",
2228 tv.tv_sec, tv.tv_usec);
2229 hw->reset.stage = RESET_STAGE_DEV_INIT;
2232 ret = hns3_reset_post(hns);
2241 hns3_clear_reset_level(hw, &hw->reset.pending);
2242 if (hns3_reset_err_handle(hns)) {
2243 hw->reset.stage = RESET_STAGE_PREWAIT;
2244 hns3_schedule_reset(hns);
2246 rte_spinlock_lock(&hw->lock);
2247 if (hw->reset.mbuf_deferred_free) {
2248 hns3_dev_release_mbufs(hns);
2249 hw->reset.mbuf_deferred_free = false;
2251 rte_spinlock_unlock(&hw->lock);
2252 __atomic_store_n(&hns->hw.reset.resetting, 0, __ATOMIC_RELAXED);
2253 hw->reset.stage = RESET_STAGE_NONE;
2254 gettimeofday(&tv, NULL);
2255 timersub(&tv, &hw->reset.start_time, &tv_delta);
2256 hns3_warn(hw, "%s reset fail delta %ld ms time=%ld.%.6ld",
2257 reset_string[hw->reset.level],
2258 tv_delta.tv_sec * MSEC_PER_SEC +
2259 tv_delta.tv_usec / USEC_PER_MSEC,
2260 tv.tv_sec, tv.tv_usec);
2261 hw->reset.level = HNS3_NONE_RESET;
2268 * The reset process can only be terminated after handshake with IMP(step3),
2269 * so that IMP can complete the reset process normally.
2272 hns3_reset_abort(struct hns3_adapter *hns)
2274 struct hns3_hw *hw = &hns->hw;
2278 for (i = 0; i < HNS3_QUIT_RESET_CNT; i++) {
2279 if (hw->reset.level == HNS3_NONE_RESET)
2281 rte_delay_ms(HNS3_QUIT_RESET_DELAY_MS);
2284 /* IMP no longer waiting the ready flag */
2285 hns3_notify_reset_ready(hw, true);
2287 rte_eal_alarm_cancel(hw->reset.ops->reset_service, hns);
2288 rte_eal_alarm_cancel(hns3_wait_callback, hw->reset.wait_data);
2290 if (hw->reset.level != HNS3_NONE_RESET) {
2291 gettimeofday(&tv, NULL);
2292 hns3_err(hw, "Failed to terminate reset: %s time=%ld.%.6ld",
2293 reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec);