1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
5 #include <rte_ethdev.h>
7 #include <rte_malloc.h>
9 #include "hns3_ethdev.h"
10 #include "hns3_rxtx.h"
11 #include "hns3_logs.h"
12 #include "hns3_regs.h"
14 /* The statistics of the per-rxq basic stats */
15 static const struct hns3_xstats_name_offset hns3_rxq_basic_stats_strings[] = {
17 HNS3_RXQ_BASIC_STATS_FIELD_OFFSET(packets)},
19 HNS3_RXQ_BASIC_STATS_FIELD_OFFSET(bytes)},
21 HNS3_RXQ_BASIC_STATS_FIELD_OFFSET(errors)}
24 /* The statistics of the per-txq basic stats */
25 static const struct hns3_xstats_name_offset hns3_txq_basic_stats_strings[] = {
27 HNS3_TXQ_BASIC_STATS_FIELD_OFFSET(packets)},
29 HNS3_TXQ_BASIC_STATS_FIELD_OFFSET(bytes)}
33 static const struct hns3_xstats_name_offset hns3_mac_strings[] = {
34 {"mac_tx_mac_pause_num",
35 HNS3_MAC_STATS_OFFSET(mac_tx_mac_pause_num)},
36 {"mac_rx_mac_pause_num",
37 HNS3_MAC_STATS_OFFSET(mac_rx_mac_pause_num)},
38 {"mac_tx_control_pkt_num",
39 HNS3_MAC_STATS_OFFSET(mac_tx_ctrl_pkt_num)},
40 {"mac_rx_control_pkt_num",
41 HNS3_MAC_STATS_OFFSET(mac_rx_ctrl_pkt_num)},
42 {"mac_tx_pfc_pkt_num",
43 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pause_pkt_num)},
44 {"mac_tx_pfc_pri0_pkt_num",
45 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri0_pkt_num)},
46 {"mac_tx_pfc_pri1_pkt_num",
47 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri1_pkt_num)},
48 {"mac_tx_pfc_pri2_pkt_num",
49 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri2_pkt_num)},
50 {"mac_tx_pfc_pri3_pkt_num",
51 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri3_pkt_num)},
52 {"mac_tx_pfc_pri4_pkt_num",
53 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri4_pkt_num)},
54 {"mac_tx_pfc_pri5_pkt_num",
55 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri5_pkt_num)},
56 {"mac_tx_pfc_pri6_pkt_num",
57 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri6_pkt_num)},
58 {"mac_tx_pfc_pri7_pkt_num",
59 HNS3_MAC_STATS_OFFSET(mac_tx_pfc_pri7_pkt_num)},
60 {"mac_rx_pfc_pkt_num",
61 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pause_pkt_num)},
62 {"mac_rx_pfc_pri0_pkt_num",
63 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri0_pkt_num)},
64 {"mac_rx_pfc_pri1_pkt_num",
65 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri1_pkt_num)},
66 {"mac_rx_pfc_pri2_pkt_num",
67 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri2_pkt_num)},
68 {"mac_rx_pfc_pri3_pkt_num",
69 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri3_pkt_num)},
70 {"mac_rx_pfc_pri4_pkt_num",
71 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri4_pkt_num)},
72 {"mac_rx_pfc_pri5_pkt_num",
73 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri5_pkt_num)},
74 {"mac_rx_pfc_pri6_pkt_num",
75 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri6_pkt_num)},
76 {"mac_rx_pfc_pri7_pkt_num",
77 HNS3_MAC_STATS_OFFSET(mac_rx_pfc_pri7_pkt_num)},
78 {"mac_tx_total_pkt_num",
79 HNS3_MAC_STATS_OFFSET(mac_tx_total_pkt_num)},
80 {"mac_tx_total_oct_num",
81 HNS3_MAC_STATS_OFFSET(mac_tx_total_oct_num)},
82 {"mac_tx_good_pkt_num",
83 HNS3_MAC_STATS_OFFSET(mac_tx_good_pkt_num)},
84 {"mac_tx_bad_pkt_num",
85 HNS3_MAC_STATS_OFFSET(mac_tx_bad_pkt_num)},
86 {"mac_tx_good_oct_num",
87 HNS3_MAC_STATS_OFFSET(mac_tx_good_oct_num)},
88 {"mac_tx_bad_oct_num",
89 HNS3_MAC_STATS_OFFSET(mac_tx_bad_oct_num)},
90 {"mac_tx_uni_pkt_num",
91 HNS3_MAC_STATS_OFFSET(mac_tx_uni_pkt_num)},
92 {"mac_tx_multi_pkt_num",
93 HNS3_MAC_STATS_OFFSET(mac_tx_multi_pkt_num)},
94 {"mac_tx_broad_pkt_num",
95 HNS3_MAC_STATS_OFFSET(mac_tx_broad_pkt_num)},
96 {"mac_tx_undersize_pkt_num",
97 HNS3_MAC_STATS_OFFSET(mac_tx_undersize_pkt_num)},
98 {"mac_tx_oversize_pkt_num",
99 HNS3_MAC_STATS_OFFSET(mac_tx_oversize_pkt_num)},
100 {"mac_tx_64_oct_pkt_num",
101 HNS3_MAC_STATS_OFFSET(mac_tx_64_oct_pkt_num)},
102 {"mac_tx_65_127_oct_pkt_num",
103 HNS3_MAC_STATS_OFFSET(mac_tx_65_127_oct_pkt_num)},
104 {"mac_tx_128_255_oct_pkt_num",
105 HNS3_MAC_STATS_OFFSET(mac_tx_128_255_oct_pkt_num)},
106 {"mac_tx_256_511_oct_pkt_num",
107 HNS3_MAC_STATS_OFFSET(mac_tx_256_511_oct_pkt_num)},
108 {"mac_tx_512_1023_oct_pkt_num",
109 HNS3_MAC_STATS_OFFSET(mac_tx_512_1023_oct_pkt_num)},
110 {"mac_tx_1024_1518_oct_pkt_num",
111 HNS3_MAC_STATS_OFFSET(mac_tx_1024_1518_oct_pkt_num)},
112 {"mac_tx_1519_2047_oct_pkt_num",
113 HNS3_MAC_STATS_OFFSET(mac_tx_1519_2047_oct_pkt_num)},
114 {"mac_tx_2048_4095_oct_pkt_num",
115 HNS3_MAC_STATS_OFFSET(mac_tx_2048_4095_oct_pkt_num)},
116 {"mac_tx_4096_8191_oct_pkt_num",
117 HNS3_MAC_STATS_OFFSET(mac_tx_4096_8191_oct_pkt_num)},
118 {"mac_tx_8192_9216_oct_pkt_num",
119 HNS3_MAC_STATS_OFFSET(mac_tx_8192_9216_oct_pkt_num)},
120 {"mac_tx_9217_12287_oct_pkt_num",
121 HNS3_MAC_STATS_OFFSET(mac_tx_9217_12287_oct_pkt_num)},
122 {"mac_tx_12288_16383_oct_pkt_num",
123 HNS3_MAC_STATS_OFFSET(mac_tx_12288_16383_oct_pkt_num)},
124 {"mac_tx_1519_max_good_pkt_num",
125 HNS3_MAC_STATS_OFFSET(mac_tx_1519_max_good_oct_pkt_num)},
126 {"mac_tx_1519_max_bad_pkt_num",
127 HNS3_MAC_STATS_OFFSET(mac_tx_1519_max_bad_oct_pkt_num)},
128 {"mac_rx_total_pkt_num",
129 HNS3_MAC_STATS_OFFSET(mac_rx_total_pkt_num)},
130 {"mac_rx_total_oct_num",
131 HNS3_MAC_STATS_OFFSET(mac_rx_total_oct_num)},
132 {"mac_rx_good_pkt_num",
133 HNS3_MAC_STATS_OFFSET(mac_rx_good_pkt_num)},
134 {"mac_rx_bad_pkt_num",
135 HNS3_MAC_STATS_OFFSET(mac_rx_bad_pkt_num)},
136 {"mac_rx_good_oct_num",
137 HNS3_MAC_STATS_OFFSET(mac_rx_good_oct_num)},
138 {"mac_rx_bad_oct_num",
139 HNS3_MAC_STATS_OFFSET(mac_rx_bad_oct_num)},
140 {"mac_rx_uni_pkt_num",
141 HNS3_MAC_STATS_OFFSET(mac_rx_uni_pkt_num)},
142 {"mac_rx_multi_pkt_num",
143 HNS3_MAC_STATS_OFFSET(mac_rx_multi_pkt_num)},
144 {"mac_rx_broad_pkt_num",
145 HNS3_MAC_STATS_OFFSET(mac_rx_broad_pkt_num)},
146 {"mac_rx_undersize_pkt_num",
147 HNS3_MAC_STATS_OFFSET(mac_rx_undersize_pkt_num)},
148 {"mac_rx_oversize_pkt_num",
149 HNS3_MAC_STATS_OFFSET(mac_rx_oversize_pkt_num)},
150 {"mac_rx_64_oct_pkt_num",
151 HNS3_MAC_STATS_OFFSET(mac_rx_64_oct_pkt_num)},
152 {"mac_rx_65_127_oct_pkt_num",
153 HNS3_MAC_STATS_OFFSET(mac_rx_65_127_oct_pkt_num)},
154 {"mac_rx_128_255_oct_pkt_num",
155 HNS3_MAC_STATS_OFFSET(mac_rx_128_255_oct_pkt_num)},
156 {"mac_rx_256_511_oct_pkt_num",
157 HNS3_MAC_STATS_OFFSET(mac_rx_256_511_oct_pkt_num)},
158 {"mac_rx_512_1023_oct_pkt_num",
159 HNS3_MAC_STATS_OFFSET(mac_rx_512_1023_oct_pkt_num)},
160 {"mac_rx_1024_1518_oct_pkt_num",
161 HNS3_MAC_STATS_OFFSET(mac_rx_1024_1518_oct_pkt_num)},
162 {"mac_rx_1519_2047_oct_pkt_num",
163 HNS3_MAC_STATS_OFFSET(mac_rx_1519_2047_oct_pkt_num)},
164 {"mac_rx_2048_4095_oct_pkt_num",
165 HNS3_MAC_STATS_OFFSET(mac_rx_2048_4095_oct_pkt_num)},
166 {"mac_rx_4096_8191_oct_pkt_num",
167 HNS3_MAC_STATS_OFFSET(mac_rx_4096_8191_oct_pkt_num)},
168 {"mac_rx_8192_9216_oct_pkt_num",
169 HNS3_MAC_STATS_OFFSET(mac_rx_8192_9216_oct_pkt_num)},
170 {"mac_rx_9217_12287_oct_pkt_num",
171 HNS3_MAC_STATS_OFFSET(mac_rx_9217_12287_oct_pkt_num)},
172 {"mac_rx_12288_16383_oct_pkt_num",
173 HNS3_MAC_STATS_OFFSET(mac_rx_12288_16383_oct_pkt_num)},
174 {"mac_rx_1519_max_good_pkt_num",
175 HNS3_MAC_STATS_OFFSET(mac_rx_1519_max_good_oct_pkt_num)},
176 {"mac_rx_1519_max_bad_pkt_num",
177 HNS3_MAC_STATS_OFFSET(mac_rx_1519_max_bad_oct_pkt_num)},
178 {"mac_tx_fragment_pkt_num",
179 HNS3_MAC_STATS_OFFSET(mac_tx_fragment_pkt_num)},
180 {"mac_tx_undermin_pkt_num",
181 HNS3_MAC_STATS_OFFSET(mac_tx_undermin_pkt_num)},
182 {"mac_tx_jabber_pkt_num",
183 HNS3_MAC_STATS_OFFSET(mac_tx_jabber_pkt_num)},
184 {"mac_tx_err_all_pkt_num",
185 HNS3_MAC_STATS_OFFSET(mac_tx_err_all_pkt_num)},
186 {"mac_tx_from_app_good_pkt_num",
187 HNS3_MAC_STATS_OFFSET(mac_tx_from_app_good_pkt_num)},
188 {"mac_tx_from_app_bad_pkt_num",
189 HNS3_MAC_STATS_OFFSET(mac_tx_from_app_bad_pkt_num)},
190 {"mac_rx_fragment_pkt_num",
191 HNS3_MAC_STATS_OFFSET(mac_rx_fragment_pkt_num)},
192 {"mac_rx_undermin_pkt_num",
193 HNS3_MAC_STATS_OFFSET(mac_rx_undermin_pkt_num)},
194 {"mac_rx_jabber_pkt_num",
195 HNS3_MAC_STATS_OFFSET(mac_rx_jabber_pkt_num)},
196 {"mac_rx_fcs_err_pkt_num",
197 HNS3_MAC_STATS_OFFSET(mac_rx_fcs_err_pkt_num)},
198 {"mac_rx_send_app_good_pkt_num",
199 HNS3_MAC_STATS_OFFSET(mac_rx_send_app_good_pkt_num)},
200 {"mac_rx_send_app_bad_pkt_num",
201 HNS3_MAC_STATS_OFFSET(mac_rx_send_app_bad_pkt_num)}
204 static const struct hns3_xstats_name_offset hns3_error_int_stats_strings[] = {
205 {"MAC_AFIFO_TNL_INT_R",
206 HNS3_ERR_INT_STATS_FIELD_OFFSET(mac_afifo_tnl_int_cnt)},
207 {"PPU_MPF_ABNORMAL_INT_ST2_MSIX",
208 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abn_int_st2_msix_cnt)},
209 {"SSU_PORT_BASED_ERR_INT_MSIX",
210 HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_port_based_pf_int_cnt)},
211 {"PPP_PF_ABNORMAL_INT_ST0",
212 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_pf_abnormal_int_cnt)},
213 {"PPU_PF_ABNORMAL_INT_ST_MSIX",
214 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_pf_abnormal_int_msix_cnt)},
215 {"IMP_TCM_ECC_INT_STS",
216 HNS3_ERR_INT_STATS_FIELD_OFFSET(imp_tcm_ecc_int_cnt)},
217 {"CMDQ_MEM_ECC_INT_STS",
218 HNS3_ERR_INT_STATS_FIELD_OFFSET(cmdq_mem_ecc_int_cnt)},
219 {"IMP_RD_POISON_INT_STS",
220 HNS3_ERR_INT_STATS_FIELD_OFFSET(imp_rd_poison_int_cnt)},
221 {"TQP_INT_ECC_INT_STS",
222 HNS3_ERR_INT_STATS_FIELD_OFFSET(tqp_int_ecc_int_cnt)},
224 HNS3_ERR_INT_STATS_FIELD_OFFSET(msix_ecc_int_cnt)},
225 {"SSU_ECC_MULTI_BIT_INT_0",
226 HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ecc_multi_bit_int_0_cnt)},
227 {"SSU_ECC_MULTI_BIT_INT_1",
228 HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ecc_multi_bit_int_1_cnt)},
229 {"SSU_COMMON_ERR_INT",
230 HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_common_ecc_int_cnt)},
232 HNS3_ERR_INT_STATS_FIELD_OFFSET(igu_int_cnt)},
233 {"PPP_MPF_ABNORMAL_INT_ST1",
234 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_mpf_abnormal_int_st1_cnt)},
235 {"PPP_MPF_ABNORMAL_INT_ST3",
236 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_mpf_abnormal_int_st3_cnt)},
237 {"PPU_MPF_ABNORMAL_INT_ST1",
238 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abnormal_int_st1_cnt)},
239 {"PPU_MPF_ABNORMAL_INT_ST2_RAS",
240 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abn_int_st2_ras_cnt)},
241 {"PPU_MPF_ABNORMAL_INT_ST3",
242 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abnormal_int_st3_cnt)},
244 HNS3_ERR_INT_STATS_FIELD_OFFSET(tm_sch_int_cnt)},
246 HNS3_ERR_INT_STATS_FIELD_OFFSET(qcn_fifo_int_cnt)},
248 HNS3_ERR_INT_STATS_FIELD_OFFSET(qcn_ecc_int_cnt)},
250 HNS3_ERR_INT_STATS_FIELD_OFFSET(ncsi_ecc_int_cnt)},
251 {"SSU_PORT_BASED_ERR_INT_RAS",
252 HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_port_based_err_int_cnt)},
253 {"SSU_FIFO_OVERFLOW_INT",
254 HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_fifo_overflow_int_cnt)},
256 HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ets_tcg_int_cnt)},
257 {"IGU_EGU_TNL_INT_STS",
258 HNS3_ERR_INT_STATS_FIELD_OFFSET(igu_egu_tnl_int_cnt)},
259 {"PPU_PF_ABNORMAL_INT_ST_RAS",
260 HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_pf_abnormal_int_ras_cnt)},
263 /* The statistic of reset */
264 static const struct hns3_xstats_name_offset hns3_reset_stats_strings[] = {
266 HNS3_RESET_STATS_FIELD_OFFSET(request_cnt)},
268 HNS3_RESET_STATS_FIELD_OFFSET(global_cnt)},
270 HNS3_RESET_STATS_FIELD_OFFSET(imp_cnt)},
272 HNS3_RESET_STATS_FIELD_OFFSET(exec_cnt)},
273 {"RESET_SUCCESS_CNT",
274 HNS3_RESET_STATS_FIELD_OFFSET(success_cnt)},
276 HNS3_RESET_STATS_FIELD_OFFSET(fail_cnt)},
278 HNS3_RESET_STATS_FIELD_OFFSET(merge_cnt)}
281 /* The statistic of errors in Rx BD */
282 static const struct hns3_xstats_name_offset hns3_rx_bd_error_strings[] = {
284 HNS3_RX_BD_ERROR_STATS_FIELD_OFFSET(pkt_len_errors)},
286 HNS3_RX_BD_ERROR_STATS_FIELD_OFFSET(l2_errors)}
289 /* The dfx statistic in Rx datapath */
290 static const struct hns3_xstats_name_offset hns3_rxq_dfx_stats_strings[] = {
291 {"L3_CHECKSUM_ERRORS",
292 HNS3_RXQ_DFX_STATS_FIELD_OFFSET(l3_csum_errors)},
293 {"L4_CHECKSUM_ERRORS",
294 HNS3_RXQ_DFX_STATS_FIELD_OFFSET(l4_csum_errors)},
295 {"OL3_CHECKSUM_ERRORS",
296 HNS3_RXQ_DFX_STATS_FIELD_OFFSET(ol3_csum_errors)},
297 {"OL4_CHECKSUM_ERRORS",
298 HNS3_RXQ_DFX_STATS_FIELD_OFFSET(ol4_csum_errors)}
301 /* The dfx statistic in Tx datapath */
302 static const struct hns3_xstats_name_offset hns3_txq_dfx_stats_strings[] = {
303 {"OVER_LENGTH_PKT_CNT",
304 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(over_length_pkt_cnt)},
305 {"EXCEED_LIMITED_BD_PKT_CNT",
306 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(exceed_limit_bd_pkt_cnt)},
307 {"EXCEED_LIMITED_BD_PKT_REASSEMBLE_FAIL_CNT",
308 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(exceed_limit_bd_reassem_fail)},
309 {"UNSUPPORTED_TUNNEL_PKT_CNT",
310 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(unsupported_tunnel_pkt_cnt)},
312 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(queue_full_cnt)},
313 {"SHORT_PKT_PAD_FAIL_CNT",
314 HNS3_TXQ_DFX_STATS_FIELD_OFFSET(pkt_padding_fail_cnt)}
317 /* The statistic of rx queue */
318 static const struct hns3_xstats_name_offset hns3_rx_queue_strings[] = {
319 {"RX_QUEUE_FBD", HNS3_RING_RX_FBDNUM_REG}
322 /* The statistic of tx queue */
323 static const struct hns3_xstats_name_offset hns3_tx_queue_strings[] = {
324 {"TX_QUEUE_FBD", HNS3_RING_TX_FBDNUM_REG}
327 /* The statistic of imissed packet */
328 static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = {
330 HNS3_IMISSED_STATS_FIELD_OFFSET(rpu_rx_drop_cnt)},
333 #define HNS3_NUM_MAC_STATS (sizeof(hns3_mac_strings) / \
334 sizeof(hns3_mac_strings[0]))
336 #define HNS3_NUM_ERROR_INT_XSTATS (sizeof(hns3_error_int_stats_strings) / \
337 sizeof(hns3_error_int_stats_strings[0]))
339 #define HNS3_NUM_RESET_XSTATS (sizeof(hns3_reset_stats_strings) / \
340 sizeof(hns3_reset_stats_strings[0]))
342 #define HNS3_NUM_RX_BD_ERROR_XSTATS (sizeof(hns3_rx_bd_error_strings) / \
343 sizeof(hns3_rx_bd_error_strings[0]))
345 #define HNS3_NUM_RXQ_DFX_XSTATS (sizeof(hns3_rxq_dfx_stats_strings) / \
346 sizeof(hns3_rxq_dfx_stats_strings[0]))
348 #define HNS3_NUM_TXQ_DFX_XSTATS (sizeof(hns3_txq_dfx_stats_strings) / \
349 sizeof(hns3_txq_dfx_stats_strings[0]))
351 #define HNS3_NUM_RX_QUEUE_STATS (sizeof(hns3_rx_queue_strings) / \
352 sizeof(hns3_rx_queue_strings[0]))
354 #define HNS3_NUM_TX_QUEUE_STATS (sizeof(hns3_tx_queue_strings) / \
355 sizeof(hns3_tx_queue_strings[0]))
357 #define HNS3_NUM_RXQ_BASIC_STATS (sizeof(hns3_rxq_basic_stats_strings) / \
358 sizeof(hns3_rxq_basic_stats_strings[0]))
360 #define HNS3_NUM_TXQ_BASIC_STATS (sizeof(hns3_txq_basic_stats_strings) / \
361 sizeof(hns3_txq_basic_stats_strings[0]))
363 #define HNS3_NUM_IMISSED_XSTATS (sizeof(hns3_imissed_stats_strings) / \
364 sizeof(hns3_imissed_stats_strings[0]))
366 #define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + HNS3_NUM_ERROR_INT_XSTATS + \
367 HNS3_NUM_RESET_XSTATS + HNS3_NUM_IMISSED_XSTATS)
369 static void hns3_tqp_stats_clear(struct hns3_hw *hw);
372 * Query all the MAC statistics data of Network ICL command ,opcode id: 0x0034.
373 * This command is used before send 'query_mac_stat command', the descriptor
374 * number of 'query_mac_stat command' must match with reg_num in this command.
376 * Pointer to structure hns3_hw.
381 hns3_update_mac_stats(struct hns3_hw *hw, const uint32_t desc_num)
383 uint64_t *data = (uint64_t *)(&hw->mac_stats);
384 struct hns3_cmd_desc *desc;
389 desc = rte_malloc("hns3_mac_desc",
390 desc_num * sizeof(struct hns3_cmd_desc), 0);
392 hns3_err(hw, "Mac_update_stats alloced desc malloc fail");
396 hns3_cmd_setup_basic_desc(desc, HNS3_OPC_STATS_MAC_ALL, true);
397 ret = hns3_cmd_send(hw, desc, desc_num);
399 hns3_err(hw, "Update complete MAC pkt stats fail : %d", ret);
404 for (i = 0; i < desc_num; i++) {
405 /* For special opcode 0034, only the first desc has the head */
407 desc_data = (uint64_t *)(&desc[i].data[0]);
408 n = HNS3_RD_FIRST_STATS_NUM;
410 desc_data = (uint64_t *)(&desc[i]);
411 n = HNS3_RD_OTHER_STATS_NUM;
414 for (k = 0; k < n; k++) {
415 *data += rte_le_to_cpu_64(*desc_data);
426 * Query Mac stat reg num command ,opcode id: 0x0033.
427 * This command is used before send 'query_mac_stat command', the descriptor
428 * number of 'query_mac_stat command' must match with reg_num in this command.
430 * Pointer to structure rte_eth_stats.
435 hns3_mac_query_reg_num(struct rte_eth_dev *dev, uint32_t *desc_num)
437 struct hns3_adapter *hns = dev->data->dev_private;
438 struct hns3_hw *hw = &hns->hw;
439 struct hns3_cmd_desc desc;
444 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_REG_NUM, true);
445 ret = hns3_cmd_send(hw, &desc, 1);
450 * The num of MAC statistics registers that are provided by IMP in this
453 desc_data = (uint32_t *)(&desc.data[0]);
454 reg_num = rte_le_to_cpu_32(*desc_data);
457 * The descriptor number of 'query_additional_mac_stat command' is
458 * '1 + (reg_num-3)/4 + ((reg_num-3)%4 !=0)';
459 * This value is 83 in this version
461 *desc_num = 1 + ((reg_num - 3) >> 2) +
462 (uint32_t)(((reg_num - 3) & 0x3) ? 1 : 0);
468 hns3_query_update_mac_stats(struct rte_eth_dev *dev)
470 struct hns3_adapter *hns = dev->data->dev_private;
471 struct hns3_hw *hw = &hns->hw;
475 ret = hns3_mac_query_reg_num(dev, &desc_num);
477 ret = hns3_update_mac_stats(hw, desc_num);
479 hns3_err(hw, "Query mac reg num fail : %d", ret);
484 hns3_update_rpu_drop_stats(struct hns3_hw *hw)
486 struct hns3_rx_missed_stats *stats = &hw->imissed_stats;
487 struct hns3_query_rpu_cmd *req;
488 struct hns3_cmd_desc desc;
493 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_DFX_RPU_REG_0, true);
494 req = (struct hns3_query_rpu_cmd *)desc.data;
497 * tc_num is 0, means rpu stats of all TC channels will be
501 req->tc_queue_num = rte_cpu_to_le_32(tc_num);
502 ret = hns3_cmd_send(hw, &desc, 1);
504 hns3_err(hw, "failed to query RPU stats: %d", ret);
508 cnt = rte_le_to_cpu_32(req->rpu_rx_pkt_drop_cnt);
509 stats->rpu_rx_drop_cnt += cnt;
515 hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear)
519 ret = hns3_update_rpu_drop_stats(hw);
524 memset(&hw->imissed_stats, 0, sizeof(hw->imissed_stats));
530 * Query tqp tx queue statistics ,opcode id: 0x0B03.
531 * Query tqp rx queue statistics ,opcode id: 0x0B13.
532 * Get all statistics of a port.
534 * Pointer to Ethernet device.
536 * Pointer to structure rte_eth_stats.
541 hns3_stats_get(struct rte_eth_dev *eth_dev, struct rte_eth_stats *rte_stats)
543 struct hns3_adapter *hns = eth_dev->data->dev_private;
544 struct hns3_hw *hw = &hns->hw;
545 struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats;
546 struct hns3_tqp_stats *stats = &hw->tqp_stats;
547 struct hns3_rx_queue *rxq;
548 struct hns3_tx_queue *txq;
554 /* Update imissed stats */
555 ret = hns3_update_imissed_stats(hw, false);
557 hns3_err(hw, "update imissed stats failed, ret = %d",
562 rte_stats->imissed = imissed_stats->rpu_rx_drop_cnt;
565 /* Reads all the stats of a rxq in a loop to keep them synchronized */
566 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
567 rxq = eth_dev->data->rx_queues[i];
571 cnt = hns3_read_dev(rxq, HNS3_RING_RX_PKTNUM_RECORD_REG);
573 * Read hardware and software in adjacent positions to minumize
574 * the timing variance.
576 rte_stats->ierrors += rxq->err_stats.l2_errors +
577 rxq->err_stats.pkt_len_errors;
578 stats->rcb_rx_ring_pktnum_rcd += cnt;
579 stats->rcb_rx_ring_pktnum[i] += cnt;
580 rte_stats->ibytes += rxq->basic_stats.bytes;
583 /* Reads all the stats of a txq in a loop to keep them synchronized */
584 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
585 txq = eth_dev->data->tx_queues[i];
589 cnt = hns3_read_dev(txq, HNS3_RING_TX_PKTNUM_RECORD_REG);
590 stats->rcb_tx_ring_pktnum_rcd += cnt;
591 stats->rcb_tx_ring_pktnum[i] += cnt;
592 rte_stats->obytes += txq->basic_stats.bytes;
595 rte_stats->oerrors = 0;
597 * If HW statistics are reset by stats_reset, but a lot of residual
598 * packets exist in the hardware queue and these packets are error
599 * packets, flip overflow may occurred. So return 0 in this case.
601 rte_stats->ipackets =
602 stats->rcb_rx_ring_pktnum_rcd > rte_stats->ierrors ?
603 stats->rcb_rx_ring_pktnum_rcd - rte_stats->ierrors : 0;
604 rte_stats->opackets = stats->rcb_tx_ring_pktnum_rcd -
606 rte_stats->rx_nombuf = eth_dev->data->rx_mbuf_alloc_failed;
612 hns3_stats_reset(struct rte_eth_dev *eth_dev)
614 struct hns3_adapter *hns = eth_dev->data->dev_private;
615 struct hns3_hw *hw = &hns->hw;
616 struct hns3_rx_queue *rxq;
617 struct hns3_tx_queue *txq;
623 * Note: Reading hardware statistics of imissed registers will
626 ret = hns3_update_imissed_stats(hw, true);
628 hns3_err(hw, "clear imissed stats failed, ret = %d",
634 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
635 rxq = eth_dev->data->rx_queues[i];
639 rxq->err_stats.pkt_len_errors = 0;
640 rxq->err_stats.l2_errors = 0;
643 /* Clear all the stats of a rxq in a loop to keep them synchronized */
644 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
645 rxq = eth_dev->data->rx_queues[i];
649 memset(&rxq->basic_stats, 0,
650 sizeof(struct hns3_rx_basic_stats));
652 /* This register is read-clear */
653 (void)hns3_read_dev(rxq, HNS3_RING_RX_PKTNUM_RECORD_REG);
654 rxq->err_stats.pkt_len_errors = 0;
655 rxq->err_stats.l2_errors = 0;
658 /* Clear all the stats of a txq in a loop to keep them synchronized */
659 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
660 txq = eth_dev->data->tx_queues[i];
664 memset(&txq->basic_stats, 0,
665 sizeof(struct hns3_tx_basic_stats));
667 /* This register is read-clear */
668 (void)hns3_read_dev(txq, HNS3_RING_TX_PKTNUM_RECORD_REG);
671 hns3_tqp_stats_clear(hw);
677 hns3_mac_stats_reset(__rte_unused struct rte_eth_dev *dev)
679 struct hns3_adapter *hns = dev->data->dev_private;
680 struct hns3_hw *hw = &hns->hw;
681 struct hns3_mac_stats *mac_stats = &hw->mac_stats;
684 ret = hns3_query_update_mac_stats(dev);
686 hns3_err(hw, "Clear Mac stats fail : %d", ret);
690 memset(mac_stats, 0, sizeof(struct hns3_mac_stats));
695 /* This function calculates the number of xstats based on the current config */
697 hns3_xstats_calc_num(struct rte_eth_dev *dev)
699 #define HNS3_PF_VF_RX_COMM_STATS_NUM (HNS3_NUM_RX_BD_ERROR_XSTATS + \
700 HNS3_NUM_RXQ_DFX_XSTATS + \
701 HNS3_NUM_RX_QUEUE_STATS + \
702 HNS3_NUM_RXQ_BASIC_STATS)
703 #define HNS3_PF_VF_TX_COMM_STATS_NUM (HNS3_NUM_TXQ_DFX_XSTATS + \
704 HNS3_NUM_TX_QUEUE_STATS + \
705 HNS3_NUM_TXQ_BASIC_STATS)
707 struct hns3_adapter *hns = dev->data->dev_private;
708 uint16_t nb_rx_q = dev->data->nb_rx_queues;
709 uint16_t nb_tx_q = dev->data->nb_tx_queues;
710 int rx_comm_stats_num = nb_rx_q * HNS3_PF_VF_RX_COMM_STATS_NUM;
711 int tx_comm_stats_num = nb_tx_q * HNS3_PF_VF_TX_COMM_STATS_NUM;
714 return rx_comm_stats_num + tx_comm_stats_num +
715 HNS3_NUM_RESET_XSTATS;
717 return rx_comm_stats_num + tx_comm_stats_num +
722 hns3_queue_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
725 struct hns3_adapter *hns = dev->data->dev_private;
726 struct hns3_hw *hw = &hns->hw;
730 /* Get rx queue stats */
731 for (j = 0; j < dev->data->nb_rx_queues; j++) {
732 for (i = 0; i < HNS3_NUM_RX_QUEUE_STATS; i++) {
733 reg_offset = hns3_get_tqp_reg_offset(j);
734 xstats[*count].value = hns3_read_dev(hw,
735 reg_offset + hns3_rx_queue_strings[i].offset);
736 xstats[*count].id = *count;
741 /* Get tx queue stats */
742 for (j = 0; j < dev->data->nb_tx_queues; j++) {
743 for (i = 0; i < HNS3_NUM_TX_QUEUE_STATS; i++) {
744 reg_offset = hns3_get_tqp_reg_offset(j);
745 xstats[*count].value = hns3_read_dev(hw,
746 reg_offset + hns3_tx_queue_strings[i].offset);
747 xstats[*count].id = *count;
754 hns3_error_int_stats_add(struct hns3_adapter *hns, const char *err)
756 struct hns3_pf *pf = &hns->pf;
760 for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) {
761 if (strcmp(hns3_error_int_stats_strings[i].name, err) == 0) {
762 addr = (char *)&pf->abn_int_stats +
763 hns3_error_int_stats_strings[i].offset;
764 *(uint64_t *)addr += 1;
771 hns3_rxq_dfx_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
774 struct hns3_rx_dfx_stats *dfx_stats;
775 struct hns3_rx_queue *rxq;
779 for (i = 0; i < dev->data->nb_rx_queues; i++) {
780 rxq = (struct hns3_rx_queue *)dev->data->rx_queues[i];
784 dfx_stats = &rxq->dfx_stats;
785 for (j = 0; j < HNS3_NUM_RXQ_DFX_XSTATS; j++) {
786 val = (char *)dfx_stats +
787 hns3_rxq_dfx_stats_strings[j].offset;
788 xstats[*count].value = *(uint64_t *)val;
789 xstats[*count].id = *count;
796 hns3_txq_dfx_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
799 struct hns3_tx_dfx_stats *dfx_stats;
800 struct hns3_tx_queue *txq;
804 for (i = 0; i < dev->data->nb_tx_queues; i++) {
805 txq = (struct hns3_tx_queue *)dev->data->tx_queues[i];
809 dfx_stats = &txq->dfx_stats;
810 for (j = 0; j < HNS3_NUM_TXQ_DFX_XSTATS; j++) {
811 val = (char *)dfx_stats +
812 hns3_txq_dfx_stats_strings[j].offset;
813 xstats[*count].value = *(uint64_t *)val;
814 xstats[*count].id = *count;
821 hns3_tqp_dfx_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
824 hns3_rxq_dfx_stats_get(dev, xstats, count);
825 hns3_txq_dfx_stats_get(dev, xstats, count);
829 hns3_rxq_basic_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
832 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
833 struct hns3_tqp_stats *stats = &hw->tqp_stats;
834 struct hns3_rx_basic_stats *rxq_stats;
835 struct hns3_rx_queue *rxq;
840 for (i = 0; i < dev->data->nb_rx_queues; i++) {
841 rxq = dev->data->rx_queues[i];
845 cnt = hns3_read_dev(rxq, HNS3_RING_RX_PKTNUM_RECORD_REG);
847 * Read hardware and software in adjacent positions to minimize
848 * the time difference.
850 rxq_stats = &rxq->basic_stats;
851 rxq_stats->errors = rxq->err_stats.l2_errors +
852 rxq->err_stats.pkt_len_errors;
853 stats->rcb_rx_ring_pktnum_rcd += cnt;
854 stats->rcb_rx_ring_pktnum[i] += cnt;
857 * If HW statistics are reset by stats_reset, but a lot of
858 * residual packets exist in the hardware queue and these
859 * packets are error packets, flip overflow may occurred.
860 * So return 0 in this case.
863 stats->rcb_rx_ring_pktnum[i] > rxq_stats->errors ?
864 stats->rcb_rx_ring_pktnum[i] - rxq_stats->errors : 0;
865 for (j = 0; j < HNS3_NUM_RXQ_BASIC_STATS; j++) {
866 val = (char *)rxq_stats +
867 hns3_rxq_basic_stats_strings[j].offset;
868 xstats[*count].value = *(uint64_t *)val;
869 xstats[*count].id = *count;
876 hns3_txq_basic_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
879 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
880 struct hns3_tqp_stats *stats = &hw->tqp_stats;
881 struct hns3_tx_basic_stats *txq_stats;
882 struct hns3_tx_queue *txq;
887 for (i = 0; i < dev->data->nb_tx_queues; i++) {
888 txq = dev->data->tx_queues[i];
892 cnt = hns3_read_dev(txq, HNS3_RING_TX_PKTNUM_RECORD_REG);
893 stats->rcb_tx_ring_pktnum_rcd += cnt;
894 stats->rcb_tx_ring_pktnum[i] += cnt;
896 txq_stats = &txq->basic_stats;
897 txq_stats->packets = stats->rcb_tx_ring_pktnum[i];
899 for (j = 0; j < HNS3_NUM_TXQ_BASIC_STATS; j++) {
900 val = (char *)txq_stats +
901 hns3_txq_basic_stats_strings[j].offset;
902 xstats[*count].value = *(uint64_t *)val;
903 xstats[*count].id = *count;
910 hns3_tqp_basic_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
913 hns3_rxq_basic_stats_get(dev, xstats, count);
914 hns3_txq_basic_stats_get(dev, xstats, count);
918 * Retrieve extended(tqp | Mac) statistics of an Ethernet device.
920 * Pointer to Ethernet device.
922 * A pointer to a table of structure of type *rte_eth_xstat*
923 * to be filled with device statistics ids and values.
924 * This parameter can be set to NULL if n is 0.
926 * The size of the xstats array (number of elements).
928 * 0 on fail, count(The size of the statistics elements) on success.
931 hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
934 struct hns3_adapter *hns = dev->data->dev_private;
935 struct hns3_pf *pf = &hns->pf;
936 struct hns3_hw *hw = &hns->hw;
937 struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats;
938 struct hns3_mac_stats *mac_stats = &hw->mac_stats;
939 struct hns3_reset_stats *reset_stats = &hw->reset.stats;
940 struct hns3_rx_bd_errors_stats *rx_err_stats;
941 struct hns3_rx_queue *rxq;
950 count = hns3_xstats_calc_num(dev);
956 hns3_tqp_basic_stats_get(dev, xstats, &count);
959 /* Update Mac stats */
960 ret = hns3_query_update_mac_stats(dev);
962 hns3_err(hw, "Update Mac stats fail : %d", ret);
966 /* Get MAC stats from hw->hw_xstats.mac_stats struct */
967 for (i = 0; i < HNS3_NUM_MAC_STATS; i++) {
968 addr = (char *)mac_stats + hns3_mac_strings[i].offset;
969 xstats[count].value = *(uint64_t *)addr;
970 xstats[count].id = count;
974 ret = hns3_update_imissed_stats(hw, false);
976 hns3_err(hw, "update imissed stats failed, ret = %d",
981 for (i = 0; i < HNS3_NUM_IMISSED_XSTATS; i++) {
982 addr = (char *)imissed_stats +
983 hns3_imissed_stats_strings[i].offset;
984 xstats[count].value = *(uint64_t *)addr;
985 xstats[count].id = count;
989 for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) {
990 addr = (char *)&pf->abn_int_stats +
991 hns3_error_int_stats_strings[i].offset;
992 xstats[count].value = *(uint64_t *)addr;
993 xstats[count].id = count;
998 /* Get the reset stat */
999 for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) {
1000 addr = (char *)reset_stats + hns3_reset_stats_strings[i].offset;
1001 xstats[count].value = *(uint64_t *)addr;
1002 xstats[count].id = count;
1006 /* Get the Rx BD errors stats */
1007 for (j = 0; j < dev->data->nb_rx_queues; j++) {
1008 for (i = 0; i < HNS3_NUM_RX_BD_ERROR_XSTATS; i++) {
1009 rxq = dev->data->rx_queues[j];
1011 rx_err_stats = &rxq->err_stats;
1012 addr = (char *)rx_err_stats +
1013 hns3_rx_bd_error_strings[i].offset;
1014 xstats[count].value = *(uint64_t *)addr;
1015 xstats[count].id = count;
1021 hns3_tqp_dfx_stats_get(dev, xstats, &count);
1022 hns3_queue_stats_get(dev, xstats, &count);
1028 hns3_tqp_basic_stats_name_get(struct rte_eth_dev *dev,
1029 struct rte_eth_xstat_name *xstats_names,
1034 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1035 for (j = 0; j < HNS3_NUM_RXQ_BASIC_STATS; j++) {
1036 snprintf(xstats_names[*count].name,
1037 sizeof(xstats_names[*count].name),
1039 hns3_rxq_basic_stats_strings[j].name);
1043 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1044 for (j = 0; j < HNS3_NUM_TXQ_BASIC_STATS; j++) {
1045 snprintf(xstats_names[*count].name,
1046 sizeof(xstats_names[*count].name),
1048 hns3_txq_basic_stats_strings[j].name);
1055 hns3_tqp_dfx_stats_name_get(struct rte_eth_dev *dev,
1056 struct rte_eth_xstat_name *xstats_names,
1061 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1062 for (j = 0; j < HNS3_NUM_RXQ_DFX_XSTATS; j++) {
1063 snprintf(xstats_names[*count].name,
1064 sizeof(xstats_names[*count].name),
1066 hns3_rxq_dfx_stats_strings[j].name);
1071 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1072 for (j = 0; j < HNS3_NUM_TXQ_DFX_XSTATS; j++) {
1073 snprintf(xstats_names[*count].name,
1074 sizeof(xstats_names[*count].name),
1076 hns3_txq_dfx_stats_strings[j].name);
1083 * Retrieve names of extended statistics of an Ethernet device.
1085 * There is an assumption that 'xstat_names' and 'xstats' arrays are matched
1087 * xstats_names[i].name => xstats[i].value
1089 * And the array index is same with id field of 'struct rte_eth_xstat':
1092 * This assumption makes key-value pair matching less flexible but simpler.
1095 * Pointer to Ethernet device.
1096 * @param xstats_names
1097 * An rte_eth_xstat_name array of at least *size* elements to
1098 * be filled. If set to NULL, the function returns the required number
1101 * The size of the xstats_names array (number of elements).
1103 * - A positive value lower or equal to size: success. The return value
1104 * is the number of entries filled in the stats table.
1107 hns3_dev_xstats_get_names(struct rte_eth_dev *dev,
1108 struct rte_eth_xstat_name *xstats_names,
1109 __rte_unused unsigned int size)
1111 struct hns3_adapter *hns = dev->data->dev_private;
1112 int cnt_stats = hns3_xstats_calc_num(dev);
1116 if (xstats_names == NULL)
1119 hns3_tqp_basic_stats_name_get(dev, xstats_names, &count);
1121 /* Note: size limited checked in rte_eth_xstats_get_names() */
1123 /* Get MAC name from hw->hw_xstats.mac_stats struct */
1124 for (i = 0; i < HNS3_NUM_MAC_STATS; i++) {
1125 snprintf(xstats_names[count].name,
1126 sizeof(xstats_names[count].name),
1127 "%s", hns3_mac_strings[i].name);
1131 for (i = 0; i < HNS3_NUM_IMISSED_XSTATS; i++) {
1132 snprintf(xstats_names[count].name,
1133 sizeof(xstats_names[count].name),
1134 "%s", hns3_imissed_stats_strings[i].name);
1138 for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) {
1139 snprintf(xstats_names[count].name,
1140 sizeof(xstats_names[count].name),
1141 "%s", hns3_error_int_stats_strings[i].name);
1145 for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) {
1146 snprintf(xstats_names[count].name,
1147 sizeof(xstats_names[count].name),
1148 "%s", hns3_reset_stats_strings[i].name);
1152 for (j = 0; j < dev->data->nb_rx_queues; j++) {
1153 for (i = 0; i < HNS3_NUM_RX_BD_ERROR_XSTATS; i++) {
1154 snprintf(xstats_names[count].name,
1155 sizeof(xstats_names[count].name),
1157 hns3_rx_bd_error_strings[i].name);
1162 hns3_tqp_dfx_stats_name_get(dev, xstats_names, &count);
1164 for (j = 0; j < dev->data->nb_rx_queues; j++) {
1165 for (i = 0; i < HNS3_NUM_RX_QUEUE_STATS; i++) {
1166 snprintf(xstats_names[count].name,
1167 sizeof(xstats_names[count].name),
1168 "rx_q%u_%s", j, hns3_rx_queue_strings[i].name);
1173 for (j = 0; j < dev->data->nb_tx_queues; j++) {
1174 for (i = 0; i < HNS3_NUM_TX_QUEUE_STATS; i++) {
1175 snprintf(xstats_names[count].name,
1176 sizeof(xstats_names[count].name),
1177 "tx_q%u_%s", j, hns3_tx_queue_strings[i].name);
1186 * Retrieve extended statistics of an Ethernet device.
1189 * Pointer to Ethernet device.
1191 * A pointer to an ids array passed by application. This tells which
1192 * statistics values function should retrieve. This parameter
1193 * can be set to NULL if size is 0. In this case function will retrieve
1194 * all avalible statistics.
1196 * A pointer to a table to be filled with device statistics values.
1198 * The size of the ids array (number of elements).
1200 * - A positive value lower or equal to size: success. The return value
1201 * is the number of entries filled in the stats table.
1202 * - A positive value higher than size: error, the given statistics table
1203 * is too small. The return value corresponds to the size that should
1204 * be given to succeed. The entries in the table are not valid and
1205 * shall not be used by the caller.
1209 hns3_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1210 uint64_t *values, uint32_t size)
1212 const uint32_t cnt_stats = hns3_xstats_calc_num(dev);
1213 struct hns3_adapter *hns = dev->data->dev_private;
1214 struct rte_eth_xstat *values_copy;
1215 struct hns3_hw *hw = &hns->hw;
1216 uint32_t count_value;
1220 if (ids == NULL && values == NULL)
1224 if (size < cnt_stats)
1227 len = cnt_stats * sizeof(struct rte_eth_xstat);
1228 values_copy = rte_zmalloc("hns3_xstats_values", len, 0);
1229 if (values_copy == NULL) {
1230 hns3_err(hw, "Failed to allocate %" PRIx64 " bytes needed "
1231 "to store statistics values", len);
1235 count_value = hns3_dev_xstats_get(dev, values_copy, cnt_stats);
1236 if (count_value != cnt_stats) {
1237 rte_free(values_copy);
1241 if (ids == NULL && values != NULL) {
1242 for (i = 0; i < cnt_stats; i++)
1243 memcpy(&values[i], &values_copy[i].value,
1246 rte_free(values_copy);
1250 for (i = 0; i < size; i++) {
1251 if (ids[i] >= cnt_stats) {
1252 hns3_err(hw, "ids[%u] (%" PRIx64 ") is invalid, "
1253 "should < %u", i, ids[i], cnt_stats);
1254 rte_free(values_copy);
1257 memcpy(&values[i], &values_copy[ids[i]].value,
1261 rte_free(values_copy);
1266 * Retrieve names of extended statistics of an Ethernet device.
1269 * Pointer to Ethernet device.
1270 * @param xstats_names
1271 * An rte_eth_xstat_name array of at least *size* elements to
1272 * be filled. If set to NULL, the function returns the required number
1275 * IDs array given by app to retrieve specific statistics
1277 * The size of the xstats_names array (number of elements).
1279 * - A positive value lower or equal to size: success. The return value
1280 * is the number of entries filled in the stats table.
1281 * - A positive value higher than size: error, the given statistics table
1282 * is too small. The return value corresponds to the size that should
1283 * be given to succeed. The entries in the table are not valid and
1284 * shall not be used by the caller.
1287 hns3_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
1288 struct rte_eth_xstat_name *xstats_names,
1289 const uint64_t *ids, uint32_t size)
1291 const uint32_t cnt_stats = hns3_xstats_calc_num(dev);
1292 struct hns3_adapter *hns = dev->data->dev_private;
1293 struct rte_eth_xstat_name *names_copy;
1294 struct hns3_hw *hw = &hns->hw;
1298 if (xstats_names == NULL)
1302 if (size < cnt_stats)
1305 return hns3_dev_xstats_get_names(dev, xstats_names, cnt_stats);
1308 len = cnt_stats * sizeof(struct rte_eth_xstat_name);
1309 names_copy = rte_zmalloc("hns3_xstats_names", len, 0);
1310 if (names_copy == NULL) {
1311 hns3_err(hw, "Failed to allocate %" PRIx64 " bytes needed "
1312 "to store statistics names", len);
1316 (void)hns3_dev_xstats_get_names(dev, names_copy, cnt_stats);
1318 for (i = 0; i < size; i++) {
1319 if (ids[i] >= cnt_stats) {
1320 hns3_err(hw, "ids[%u] (%" PRIx64 ") is invalid, "
1321 "should < %u", i, ids[i], cnt_stats);
1322 rte_free(names_copy);
1325 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1326 "%s", names_copy[ids[i]].name);
1329 rte_free(names_copy);
1334 hns3_tqp_dfx_stats_clear(struct rte_eth_dev *dev)
1336 struct hns3_rx_queue *rxq;
1337 struct hns3_tx_queue *txq;
1340 /* Clear Rx dfx stats */
1341 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1342 rxq = dev->data->rx_queues[i];
1344 memset(&rxq->dfx_stats, 0,
1345 sizeof(struct hns3_rx_dfx_stats));
1348 /* Clear Tx dfx stats */
1349 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1350 txq = dev->data->tx_queues[i];
1352 memset(&txq->dfx_stats, 0,
1353 sizeof(struct hns3_tx_dfx_stats));
1358 hns3_dev_xstats_reset(struct rte_eth_dev *dev)
1360 struct hns3_adapter *hns = dev->data->dev_private;
1361 struct hns3_pf *pf = &hns->pf;
1364 /* Clear tqp stats */
1365 ret = hns3_stats_reset(dev);
1369 hns3_tqp_dfx_stats_clear(dev);
1371 /* Clear reset stats */
1372 memset(&hns->hw.reset.stats, 0, sizeof(struct hns3_reset_stats));
1377 /* HW registers are cleared on read */
1378 ret = hns3_mac_stats_reset(dev);
1382 /* Clear error stats */
1383 memset(&pf->abn_int_stats, 0, sizeof(struct hns3_err_msix_intr_stats));
1389 hns3_tqp_stats_init(struct hns3_hw *hw)
1391 struct hns3_tqp_stats *tqp_stats = &hw->tqp_stats;
1393 tqp_stats->rcb_rx_ring_pktnum = rte_zmalloc("hns3_rx_ring_pkt_num",
1394 sizeof(uint64_t) * hw->tqps_num, 0);
1395 if (tqp_stats->rcb_rx_ring_pktnum == NULL) {
1396 hns3_err(hw, "failed to allocate rx_ring pkt_num.");
1400 tqp_stats->rcb_tx_ring_pktnum = rte_zmalloc("hns3_tx_ring_pkt_num",
1401 sizeof(uint64_t) * hw->tqps_num, 0);
1402 if (tqp_stats->rcb_tx_ring_pktnum == NULL) {
1403 hns3_err(hw, "failed to allocate tx_ring pkt_num.");
1404 rte_free(tqp_stats->rcb_rx_ring_pktnum);
1405 tqp_stats->rcb_rx_ring_pktnum = NULL;
1413 hns3_tqp_stats_uninit(struct hns3_hw *hw)
1415 struct hns3_tqp_stats *tqp_stats = &hw->tqp_stats;
1417 rte_free(tqp_stats->rcb_rx_ring_pktnum);
1418 tqp_stats->rcb_rx_ring_pktnum = NULL;
1419 rte_free(tqp_stats->rcb_tx_ring_pktnum);
1420 tqp_stats->rcb_tx_ring_pktnum = NULL;
1424 hns3_tqp_stats_clear(struct hns3_hw *hw)
1426 struct hns3_tqp_stats *stats = &hw->tqp_stats;
1428 stats->rcb_rx_ring_pktnum_rcd = 0;
1429 stats->rcb_tx_ring_pktnum_rcd = 0;
1430 memset(stats->rcb_rx_ring_pktnum, 0, sizeof(uint64_t) * hw->tqps_num);
1431 memset(stats->rcb_tx_ring_pktnum, 0, sizeof(uint64_t) * hw->tqps_num);