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34 #ifndef _I40E_ETHDEV_H_
35 #define _I40E_ETHDEV_H_
37 #include <rte_eth_ctrl.h>
40 #define I40E_VLAN_TAG_SIZE 4
42 #define I40E_AQ_LEN 32
43 #define I40E_AQ_BUF_SZ 4096
44 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
45 #define I40E_MAX_Q_PER_TC 64
46 #define I40E_NUM_DESC_DEFAULT 512
47 #define I40E_NUM_DESC_ALIGN 32
48 #define I40E_BUF_SIZE_MIN 1024
49 #define I40E_FRAME_SIZE_MAX 9728
50 #define I40E_QUEUE_BASE_ADDR_UNIT 128
51 /* number of VSIs and queue default setting */
52 #define I40E_MAX_QP_NUM_PER_VF 16
53 #define I40E_DEFAULT_QP_NUM_FDIR 1
54 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
55 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
57 * vlan_id is a 12 bit number.
58 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
59 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
60 * The higher 7 bit val specifies VFTA array index.
62 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
63 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
65 /* Default TC traffic in case DCB is not enabled */
66 #define I40E_DEFAULT_TCMAP 0x1
67 #define I40E_FDIR_QUEUE_ID 0
69 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
70 #define I40E_VMDQ_POOL_BASE 1
72 #define I40E_DEFAULT_RX_FREE_THRESH 32
73 #define I40E_DEFAULT_RX_PTHRESH 8
74 #define I40E_DEFAULT_RX_HTHRESH 8
75 #define I40E_DEFAULT_RX_WTHRESH 0
77 #define I40E_DEFAULT_TX_FREE_THRESH 32
78 #define I40E_DEFAULT_TX_PTHRESH 32
79 #define I40E_DEFAULT_TX_HTHRESH 0
80 #define I40E_DEFAULT_TX_WTHRESH 0
81 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
83 /* Bit shift and mask */
84 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
85 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
86 #define I40E_8_BIT_WIDTH CHAR_BIT
87 #define I40E_8_BIT_MASK UINT8_MAX
88 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
89 #define I40E_16_BIT_MASK UINT16_MAX
90 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
91 #define I40E_32_BIT_MASK UINT32_MAX
92 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
93 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
95 /* Linux PF host with virtchnl version 1.1 */
96 #define PF_IS_V11(vf) \
97 (((vf)->version_major == I40E_VIRTCHNL_VERSION_MAJOR) && \
98 ((vf)->version_minor == 1))
100 /* index flex payload per layer */
101 enum i40e_flxpld_layer_idx {
102 I40E_FLXPLD_L2_IDX = 0,
103 I40E_FLXPLD_L3_IDX = 1,
104 I40E_FLXPLD_L4_IDX = 2,
105 I40E_MAX_FLXPLD_LAYER = 3,
107 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
108 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
109 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
110 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
111 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */
114 #define I40E_FLAG_RSS (1ULL << 0)
115 #define I40E_FLAG_DCB (1ULL << 1)
116 #define I40E_FLAG_VMDQ (1ULL << 2)
117 #define I40E_FLAG_SRIOV (1ULL << 3)
118 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
119 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
120 #define I40E_FLAG_FDIR (1ULL << 6)
121 #define I40E_FLAG_VXLAN (1ULL << 7)
122 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
123 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
127 I40E_FLAG_HEADER_SPLIT_DISABLED | \
128 I40E_FLAG_HEADER_SPLIT_ENABLED | \
131 I40E_FLAG_RSS_AQ_CAPABLE)
133 #define I40E_RSS_OFFLOAD_ALL ( \
134 ETH_RSS_FRAG_IPV4 | \
135 ETH_RSS_NONFRAG_IPV4_TCP | \
136 ETH_RSS_NONFRAG_IPV4_UDP | \
137 ETH_RSS_NONFRAG_IPV4_SCTP | \
138 ETH_RSS_NONFRAG_IPV4_OTHER | \
139 ETH_RSS_FRAG_IPV6 | \
140 ETH_RSS_NONFRAG_IPV6_TCP | \
141 ETH_RSS_NONFRAG_IPV6_UDP | \
142 ETH_RSS_NONFRAG_IPV6_SCTP | \
143 ETH_RSS_NONFRAG_IPV6_OTHER | \
146 /* All bits of RSS hash enable */
147 #define I40E_RSS_HENA_ALL ( \
148 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
149 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
150 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
151 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
152 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
153 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
154 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
155 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
156 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
157 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
158 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
159 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
160 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
161 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
163 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
164 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
166 /* Default queue interrupt throttling time in microseconds */
167 #define I40E_ITR_INDEX_DEFAULT 0
168 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
169 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
174 * MAC filter structure
176 struct i40e_mac_filter_info {
177 enum rte_mac_filter_type filter_type;
178 struct ether_addr mac_addr;
181 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
183 /* MAC filter list structure */
184 struct i40e_mac_filter {
185 TAILQ_ENTRY(i40e_mac_filter) next;
186 struct i40e_mac_filter_info mac_info;
189 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
193 /* VSI list structure */
194 struct i40e_vsi_list {
195 TAILQ_ENTRY(i40e_vsi_list) list;
196 struct i40e_vsi *vsi;
199 struct i40e_rx_queue;
200 struct i40e_tx_queue;
202 /* Structure that defines a VEB */
204 struct i40e_vsi_list_head head;
205 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
206 uint16_t seid; /* The seid of VEB itself */
207 uint16_t uplink_seid; /* The uplink seid of this VEB */
209 struct i40e_eth_stats stats;
212 /* i40e MACVLAN filter structure */
213 struct i40e_macvlan_filter {
214 struct ether_addr macaddr;
215 enum rte_mac_filter_type filter_type;
219 /* Bandwidth limit information */
220 struct i40e_bw_info {
221 uint16_t bw_limit; /* BW Limit (0 = disabled) */
222 uint8_t bw_max_quanta; /* Max Quanta when BW limit is enabled */
224 /* Relative TC credits across VSIs */
225 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
226 /* TC BW limit credits within VSI */
227 uint8_t bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
228 /* TC BW limit max quanta within VSI */
229 uint8_t bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
233 * Structure that defines a VSI, associated with a adapter.
236 struct i40e_adapter *adapter; /* Backreference to associated adapter */
237 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
239 struct i40e_eth_stats eth_stats_offset;
240 struct i40e_eth_stats eth_stats;
242 * When drivers loaded, only a default main VSI exists. In case new VSI
243 * needs to add, HW needs to know the layout that VSIs are organized.
244 * Besides that, VSI isan element and can't switch packets, which needs
245 * to add new component VEB to perform switching. So, a new VSI needs
246 * to specify the the uplink VSI (Parent VSI) before created. The
247 * uplink VSI will check whether it had a VEB to switch packets. If no,
248 * it will try to create one. Then, uplink VSI will move the new VSI
249 * into its' sib_vsi_list to manage all the downlink VSI.
250 * sib_vsi_list: the VSI list that shared the same uplink VSI.
251 * parent_vsi : the uplink VSI. It's NULL for main VSI.
252 * veb : the VEB associates with the VSI.
254 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
255 struct i40e_vsi *parent_vsi;
256 struct i40e_veb *veb; /* Associated veb, could be null */
258 enum i40e_vsi_type type; /* VSI types */
259 uint16_t vlan_num; /* Total VLAN number */
260 uint16_t mac_num; /* Total mac number */
261 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
262 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
263 /* specific VSI-defined parameters, SRIOV stored the vf_id */
265 uint16_t seid; /* The seid of VSI itself */
266 uint16_t uplink_seid; /* The uplink seid of this VSI */
267 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
268 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
269 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
270 uint16_t base_queue; /* The first queue index of this VSI */
272 * The offset to visit VSI related register, assigned by HW when
276 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
277 uint16_t nb_msix; /* The max number of msix vector */
278 uint8_t enabled_tc; /* The traffic class enabled */
279 struct i40e_bw_info bw_info; /* VSI bandwidth information */
283 LIST_ENTRY(pool_entry) next;
288 LIST_HEAD(res_list, pool_entry);
290 struct i40e_res_pool_info {
291 uint32_t base; /* Resource start index */
292 uint32_t num_alloc; /* Allocated resource number */
293 uint32_t num_free; /* Total available resource number */
294 struct res_list alloc_list; /* Allocated resource list */
295 struct res_list free_list; /* Available resource list */
299 I40E_VF_INACTIVE = 0,
306 * Structure to store private data for PF host.
310 struct i40e_vsi *vsi;
311 enum I40E_VF_STATE state; /* The number of queue pairs availiable */
312 uint16_t vf_idx; /* VF index in pf->vfs */
313 uint16_t lan_nb_qps; /* Actual queues allocated */
314 uint16_t reset_cnt; /* Total vf reset times */
318 * Structure to store private data for flow control.
320 struct i40e_fc_conf {
321 uint16_t pause_time; /* Flow control pause timer */
322 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
323 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
324 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */
325 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
329 * Structure to store private data for VMDQ instance
331 struct i40e_vmdq_info {
333 struct i40e_vsi *vsi;
337 * Structure to store flex pit for flow diretor.
339 struct i40e_fdir_flex_pit {
340 uint8_t src_offset; /* offset in words from the beginning of payload */
341 uint8_t size; /* size in words */
342 uint8_t dst_offset; /* offset in words of flexible payload */
345 struct i40e_fdir_flex_mask {
346 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
350 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
353 #define I40E_FILTER_PCTYPE_MAX 64
355 * A structure used to define fields of a FDIR related info.
357 struct i40e_fdir_info {
358 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
359 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
360 struct i40e_tx_queue *txq;
361 struct i40e_rx_queue *rxq;
362 void *prg_pkt; /* memory for fdir program packet */
363 uint64_t dma_addr; /* physic address of packet memory*/
365 * the rule how bytes stream is extracted as flexible payload
366 * for each payload layer, the setting can up to three elements
368 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
369 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
372 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
373 #define I40E_MAX_MIRROR_RULES 64
375 * Mirror rule structure
377 struct i40e_mirror_rule {
378 TAILQ_ENTRY(i40e_mirror_rule) rules;
380 uint16_t index; /* the sw index of mirror rule */
381 uint16_t id; /* the rule id assigned by firmware */
382 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
383 uint16_t num_entries;
384 /* the info stores depend on the rule type.
385 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
386 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
388 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
391 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
394 * Structure to store private data specific for PF instance.
397 struct i40e_adapter *adapter; /* The adapter this PF associate to */
398 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
399 uint16_t mac_seid; /* The seid of the MAC of this PF */
400 uint16_t main_vsi_seid; /* The seid of the main VSI */
401 uint16_t max_num_vsi;
402 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
403 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
405 struct i40e_hw_port_stats stats_offset;
406 struct i40e_hw_port_stats stats;
409 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
410 struct ether_addr dev_addr; /* PF device mac address */
411 uint64_t flags; /* PF featuer flags */
412 /* All kinds of queue pair setting for different VSIs */
413 struct i40e_pf_vf *vfs;
415 /* Each of below queue pairs should be power of 2 since it's the
416 precondition after TC configuration applied */
417 uint16_t lan_nb_qp_max;
418 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
419 uint16_t lan_qp_offset;
420 uint16_t vmdq_nb_qp_max;
421 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
422 uint16_t vmdq_qp_offset;
423 uint16_t vf_nb_qp_max;
424 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
425 uint16_t vf_qp_offset;
426 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
427 uint16_t fdir_qp_offset;
429 uint16_t hash_lut_size; /* The size of hash lookup table */
430 /* store VXLAN UDP ports */
431 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
432 uint16_t vxlan_bitmap; /* Vxlan bit mask */
434 /* VMDQ related info */
435 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
436 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
437 struct i40e_vmdq_info *vmdq;
439 struct i40e_fdir_info fdir; /* flow director info */
440 struct i40e_fc_conf fc_conf; /* Flow control conf */
441 struct i40e_mirror_rule_list mirror_list;
442 uint16_t nb_mirror_rule; /* The number of mirror rules */
446 PFMSG_LINK_CHANGE = 0x1,
447 PFMSG_RESET_IMPENDING = 0x2,
448 PFMSG_DRIVER_CLOSE = 0x4,
451 struct i40e_vsi_vlan_pvid_info {
452 uint16_t on; /* Enable or disable pvid */
454 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
456 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
457 * while 'untagged' will reject untagged packets.
465 struct i40e_vf_rx_queues {
466 uint64_t rx_dma_addr;
467 uint32_t rx_ring_len;
471 struct i40e_vf_tx_queues {
472 uint64_t tx_dma_addr;
473 uint32_t tx_ring_len;
477 * Structure to store private data specific for VF instance.
480 struct i40e_adapter *adapter; /* The adapter this VF associate to */
481 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
482 uint16_t num_queue_pairs;
483 uint16_t max_pkt_len; /* Maximum packet length */
484 bool promisc_unicast_enabled;
485 bool promisc_multicast_enabled;
487 uint32_t version_major; /* Major version number */
488 uint32_t version_minor; /* Minor version number */
489 uint16_t promisc_flags; /* Promiscuous setting */
490 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
496 volatile uint32_t pend_cmd; /* pending command not finished yet */
497 u16 pend_msg; /* flags indicates events from pf not handled yet */
500 struct i40e_virtchnl_vf_resource *vf_res; /* All VSIs */
501 struct i40e_virtchnl_vsi_resource *vsi_res; /* LAN VSI */
507 * Structure to store private data for each PF/VF instance.
509 struct i40e_adapter {
510 /* Common for both PF and VF */
512 struct rte_eth_dev *eth_dev;
514 /* Specific for PF or VF */
521 bool rx_bulk_alloc_allowed;
523 bool tx_simple_allowed;
527 struct rte_timecounter systime_tc;
528 struct rte_timecounter rx_tstamp_tc;
529 struct rte_timecounter tx_tstamp_tc;
532 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
533 int i40e_vsi_release(struct i40e_vsi *vsi);
534 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
535 enum i40e_vsi_type type,
536 struct i40e_vsi *uplink_vsi,
537 uint16_t user_param);
538 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
539 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
540 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
541 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
542 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
543 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);
544 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
545 void i40e_pf_disable_irq0(struct i40e_hw *hw);
546 void i40e_pf_enable_irq0(struct i40e_hw *hw);
547 int i40e_dev_link_update(struct rte_eth_dev *dev,
548 __rte_unused int wait_to_complete);
549 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi);
550 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
551 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
552 struct i40e_vsi_vlan_pvid_info *info);
553 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
554 uint64_t i40e_config_hena(uint64_t flags);
555 uint64_t i40e_parse_hena(uint64_t flags);
556 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
557 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
558 int i40e_fdir_setup(struct i40e_pf *pf);
559 const struct rte_memzone *i40e_memzone_reserve(const char *name,
562 int i40e_fdir_configure(struct rte_eth_dev *dev);
563 void i40e_fdir_teardown(struct i40e_pf *pf);
564 enum i40e_filter_pctype i40e_flowtype_to_pctype(uint16_t flow_type);
565 uint16_t i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype);
566 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
567 enum rte_filter_op filter_op,
569 int i40e_select_filter_input_set(struct i40e_hw *hw,
570 struct rte_eth_input_set_conf *conf,
571 enum rte_filter_type filter);
572 int i40e_filter_inset_select(struct i40e_hw *hw,
573 struct rte_eth_input_set_conf *conf,
574 enum rte_filter_type filter);
576 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
577 struct rte_eth_rxq_info *qinfo);
578 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
579 struct rte_eth_txq_info *qinfo);
581 /* I40E_DEV_PRIVATE_TO */
582 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
583 (&((struct i40e_adapter *)adapter)->pf)
584 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
585 (&((struct i40e_adapter *)adapter)->hw)
586 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
587 ((struct i40e_adapter *)adapter)
589 /* I40EVF_DEV_PRIVATE_TO */
590 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
591 (&((struct i40e_adapter *)adapter)->vf)
593 static inline struct i40e_vsi *
594 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
601 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
602 if (hw->mac.type == I40E_MAC_VF) {
603 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
606 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
610 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
611 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
614 #define I40E_VSI_TO_HW(vsi) \
615 (&(((struct i40e_vsi *)vsi)->adapter->hw))
616 #define I40E_VSI_TO_PF(vsi) \
617 (&(((struct i40e_vsi *)vsi)->adapter->pf))
618 #define I40E_VSI_TO_VF(vsi) \
619 (&(((struct i40e_vsi *)vsi)->adapter->vf))
620 #define I40E_VSI_TO_DEV_DATA(vsi) \
621 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
622 #define I40E_VSI_TO_ETH_DEV(vsi) \
623 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
626 #define I40E_PF_TO_HW(pf) \
627 (&(((struct i40e_pf *)pf)->adapter->hw))
628 #define I40E_PF_TO_ADAPTER(pf) \
629 ((struct i40e_adapter *)pf->adapter)
632 #define I40E_VF_TO_HW(vf) \
633 (&(((struct i40e_vf *)vf)->adapter->hw))
636 i40e_init_adminq_parameter(struct i40e_hw *hw)
638 hw->aq.num_arq_entries = I40E_AQ_LEN;
639 hw->aq.num_asq_entries = I40E_AQ_LEN;
640 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
641 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
645 i40e_align_floor(int n)
649 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
652 static inline uint16_t
653 i40e_calc_itr_interval(int16_t interval)
655 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
656 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
658 /* Convert to hardware count, as writing each 1 represents 2 us */
659 return (interval / 2);
662 #define I40E_VALID_FLOW(flow_type) \
663 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
664 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
665 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
666 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
667 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
668 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
669 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
670 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
671 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
672 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
673 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
675 #define I40E_VALID_PCTYPE(pctype) \
676 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
677 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
678 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
679 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
680 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
681 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
682 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
683 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
684 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
685 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
686 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
688 #endif /* _I40E_ETHDEV_H_ */