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34 #ifndef _I40E_ETHDEV_H_
35 #define _I40E_ETHDEV_H_
37 #include <rte_eth_ctrl.h>
39 #include <rte_kvargs.h>
41 #include <rte_flow_driver.h>
42 #include <rte_tm_driver.h>
44 #define I40E_VLAN_TAG_SIZE 4
46 #define I40E_AQ_LEN 32
47 #define I40E_AQ_BUF_SZ 4096
48 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
49 #define I40E_MAX_Q_PER_TC 64
50 #define I40E_NUM_DESC_DEFAULT 512
51 #define I40E_NUM_DESC_ALIGN 32
52 #define I40E_BUF_SIZE_MIN 1024
53 #define I40E_FRAME_SIZE_MAX 9728
54 #define I40E_QUEUE_BASE_ADDR_UNIT 128
55 /* number of VSIs and queue default setting */
56 #define I40E_MAX_QP_NUM_PER_VF 16
57 #define I40E_DEFAULT_QP_NUM_FDIR 1
58 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
59 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
60 /* Maximun number of MAC addresses */
61 #define I40E_NUM_MACADDR_MAX 64
62 /* Maximum number of VFs */
63 #define I40E_MAX_VF 128
66 * vlan_id is a 12 bit number.
67 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
68 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
69 * The higher 7 bit val specifies VFTA array index.
71 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
72 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
74 /* Default TC traffic in case DCB is not enabled */
75 #define I40E_DEFAULT_TCMAP 0x1
76 #define I40E_FDIR_QUEUE_ID 0
78 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
79 #define I40E_VMDQ_POOL_BASE 1
81 #define I40E_DEFAULT_RX_FREE_THRESH 32
82 #define I40E_DEFAULT_RX_PTHRESH 8
83 #define I40E_DEFAULT_RX_HTHRESH 8
84 #define I40E_DEFAULT_RX_WTHRESH 0
86 #define I40E_DEFAULT_TX_FREE_THRESH 32
87 #define I40E_DEFAULT_TX_PTHRESH 32
88 #define I40E_DEFAULT_TX_HTHRESH 0
89 #define I40E_DEFAULT_TX_WTHRESH 0
90 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
92 /* Bit shift and mask */
93 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
94 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
95 #define I40E_8_BIT_WIDTH CHAR_BIT
96 #define I40E_8_BIT_MASK UINT8_MAX
97 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
98 #define I40E_16_BIT_MASK UINT16_MAX
99 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
100 #define I40E_32_BIT_MASK UINT32_MAX
101 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
102 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
104 /* Linux PF host with virtchnl version 1.1 */
105 #define PF_IS_V11(vf) \
106 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \
107 ((vf)->version_minor == 1))
109 /* index flex payload per layer */
110 enum i40e_flxpld_layer_idx {
111 I40E_FLXPLD_L2_IDX = 0,
112 I40E_FLXPLD_L3_IDX = 1,
113 I40E_FLXPLD_L4_IDX = 2,
114 I40E_MAX_FLXPLD_LAYER = 3,
116 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
117 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
118 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
119 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
120 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */
123 #define I40E_FLAG_RSS (1ULL << 0)
124 #define I40E_FLAG_DCB (1ULL << 1)
125 #define I40E_FLAG_VMDQ (1ULL << 2)
126 #define I40E_FLAG_SRIOV (1ULL << 3)
127 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
128 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
129 #define I40E_FLAG_FDIR (1ULL << 6)
130 #define I40E_FLAG_VXLAN (1ULL << 7)
131 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
132 #define I40E_FLAG_VF_MAC_BY_PF (1ULL << 9)
133 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
137 I40E_FLAG_HEADER_SPLIT_DISABLED | \
138 I40E_FLAG_HEADER_SPLIT_ENABLED | \
141 I40E_FLAG_RSS_AQ_CAPABLE | \
142 I40E_FLAG_VF_MAC_BY_PF)
144 #define I40E_RSS_OFFLOAD_ALL ( \
145 ETH_RSS_FRAG_IPV4 | \
146 ETH_RSS_NONFRAG_IPV4_TCP | \
147 ETH_RSS_NONFRAG_IPV4_UDP | \
148 ETH_RSS_NONFRAG_IPV4_SCTP | \
149 ETH_RSS_NONFRAG_IPV4_OTHER | \
150 ETH_RSS_FRAG_IPV6 | \
151 ETH_RSS_NONFRAG_IPV6_TCP | \
152 ETH_RSS_NONFRAG_IPV6_UDP | \
153 ETH_RSS_NONFRAG_IPV6_SCTP | \
154 ETH_RSS_NONFRAG_IPV6_OTHER | \
157 /* All bits of RSS hash enable for X722*/
158 #define I40E_RSS_HENA_ALL_X722 ( \
159 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
160 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
161 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
162 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
163 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
164 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
167 /* All bits of RSS hash enable */
168 #define I40E_RSS_HENA_ALL ( \
169 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
170 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
171 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
172 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
173 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
174 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
175 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
176 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
177 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
178 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
179 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
180 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
181 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
182 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
184 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
185 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
187 /* Default queue interrupt throttling time in microseconds */
188 #define I40E_ITR_INDEX_DEFAULT 0
189 #define I40E_ITR_INDEX_NONE 3
190 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
191 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
192 /* Special FW support this floating VEB feature */
193 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5
194 #define FLOATING_VEB_SUPPORTED_FW_MIN 0
196 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
197 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
198 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
199 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
201 #define I40E_INSET_NONE 0x00000000000000000ULL
204 #define I40E_INSET_DMAC 0x0000000000000001ULL
205 #define I40E_INSET_SMAC 0x0000000000000002ULL
206 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
207 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
208 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
211 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
212 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
213 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
214 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
215 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
216 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
217 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
219 /* bit 16 ~ bit 31 */
220 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
221 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
222 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
223 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
224 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
225 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
226 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
227 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
229 /* bit 32 ~ bit 47, tunnel fields */
230 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
231 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
232 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
233 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
234 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
235 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
237 /* bit 48 ~ bit 55 */
238 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
240 /* bit 56 ~ bit 63, Flex Payload */
241 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
242 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
243 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
244 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
245 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
246 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
247 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
248 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
249 #define I40E_INSET_FLEX_PAYLOAD \
250 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
251 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
252 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
253 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
255 /* The max bandwidth of i40e is 40Gbps. */
256 #define I40E_QOS_BW_MAX 40000
257 /* The bandwidth should be the multiple of 50Mbps. */
258 #define I40E_QOS_BW_GRANULARITY 50
259 /* The min bandwidth weight is 1. */
260 #define I40E_QOS_BW_WEIGHT_MIN 1
261 /* The max bandwidth weight is 127. */
262 #define I40E_QOS_BW_WEIGHT_MAX 127
263 /* The max queue region index is 7. */
264 #define I40E_REGION_MAX_INDEX 7
266 #define I40E_MAX_PERCENT 100
267 #define I40E_DEFAULT_DCB_APP_NUM 1
268 #define I40E_DEFAULT_DCB_APP_PRIO 3
271 * The overhead from MTU to max frame size.
272 * Considering QinQ packet, the VLAN tag needs to be counted twice.
274 #define I40E_ETH_OVERHEAD \
275 (ETHER_HDR_LEN + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2)
280 * MAC filter structure
282 struct i40e_mac_filter_info {
283 enum rte_mac_filter_type filter_type;
284 struct ether_addr mac_addr;
287 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
289 /* MAC filter list structure */
290 struct i40e_mac_filter {
291 TAILQ_ENTRY(i40e_mac_filter) next;
292 struct i40e_mac_filter_info mac_info;
295 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
299 /* VSI list structure */
300 struct i40e_vsi_list {
301 TAILQ_ENTRY(i40e_vsi_list) list;
302 struct i40e_vsi *vsi;
305 struct i40e_rx_queue;
306 struct i40e_tx_queue;
308 /* Bandwidth limit information */
309 struct i40e_bw_info {
310 uint16_t bw_limit; /* BW Limit (0 = disabled) */
311 uint8_t bw_max; /* Max BW limit if enabled */
313 /* Relative credits within same TC with respect to other VSIs or Comps */
314 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
315 /* Bandwidth limit per TC */
316 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
317 /* Max bandwidth limit per TC */
318 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS];
321 /* Structure that defines a VEB */
323 struct i40e_vsi_list_head head;
324 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
325 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */
326 uint16_t seid; /* The seid of VEB itself */
327 uint16_t uplink_seid; /* The uplink seid of this VEB */
329 struct i40e_eth_stats stats;
330 uint8_t enabled_tc; /* The traffic class enabled */
331 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */
332 struct i40e_bw_info bw_info; /* VEB bandwidth information */
335 /* i40e MACVLAN filter structure */
336 struct i40e_macvlan_filter {
337 struct ether_addr macaddr;
338 enum rte_mac_filter_type filter_type;
343 * Structure that defines a VSI, associated with a adapter.
346 struct i40e_adapter *adapter; /* Backreference to associated adapter */
347 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
349 struct i40e_eth_stats eth_stats_offset;
350 struct i40e_eth_stats eth_stats;
352 * When drivers loaded, only a default main VSI exists. In case new VSI
353 * needs to add, HW needs to know the layout that VSIs are organized.
354 * Besides that, VSI isan element and can't switch packets, which needs
355 * to add new component VEB to perform switching. So, a new VSI needs
356 * to specify the the uplink VSI (Parent VSI) before created. The
357 * uplink VSI will check whether it had a VEB to switch packets. If no,
358 * it will try to create one. Then, uplink VSI will move the new VSI
359 * into its' sib_vsi_list to manage all the downlink VSI.
360 * sib_vsi_list: the VSI list that shared the same uplink VSI.
361 * parent_vsi : the uplink VSI. It's NULL for main VSI.
362 * veb : the VEB associates with the VSI.
364 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
365 struct i40e_vsi *parent_vsi;
366 struct i40e_veb *veb; /* Associated veb, could be null */
367 struct i40e_veb *floating_veb; /* Associated floating veb */
369 enum i40e_vsi_type type; /* VSI types */
370 uint16_t vlan_num; /* Total VLAN number */
371 uint16_t mac_num; /* Total mac number */
372 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
373 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
374 /* specific VSI-defined parameters, SRIOV stored the vf_id */
376 uint16_t seid; /* The seid of VSI itself */
377 uint16_t uplink_seid; /* The uplink seid of this VSI */
378 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
379 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
380 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
381 uint16_t base_queue; /* The first queue index of this VSI */
383 * The offset to visit VSI related register, assigned by HW when
387 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
388 uint16_t nb_msix; /* The max number of msix vector */
389 uint8_t enabled_tc; /* The traffic class enabled */
390 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
391 uint8_t vlan_filter_on; /* The VLAN filter enabled */
392 struct i40e_bw_info bw_info; /* VSI bandwidth information */
396 LIST_ENTRY(pool_entry) next;
401 LIST_HEAD(res_list, pool_entry);
403 struct i40e_res_pool_info {
404 uint32_t base; /* Resource start index */
405 uint32_t num_alloc; /* Allocated resource number */
406 uint32_t num_free; /* Total available resource number */
407 struct res_list alloc_list; /* Allocated resource list */
408 struct res_list free_list; /* Available resource list */
412 I40E_VF_INACTIVE = 0,
419 * Structure to store private data for PF host.
423 struct i40e_vsi *vsi;
424 enum I40E_VF_STATE state; /* The number of queue pairs available */
425 uint16_t vf_idx; /* VF index in pf->vfs */
426 uint16_t lan_nb_qps; /* Actual queues allocated */
427 uint16_t reset_cnt; /* Total vf reset times */
428 struct ether_addr mac_addr; /* Default MAC address */
432 * Structure to store private data for flow control.
434 struct i40e_fc_conf {
435 uint16_t pause_time; /* Flow control pause timer */
436 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
437 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
438 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */
439 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
443 * Structure to store private data for VMDQ instance
445 struct i40e_vmdq_info {
447 struct i40e_vsi *vsi;
450 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */
451 #define I40E_MAX_FLX_SOURCE_OFF 480
452 #define NONUSE_FLX_PIT_DEST_OFF 63
453 #define NONUSE_FLX_PIT_FSIZE 1
454 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50
455 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
456 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
457 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
458 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
459 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
460 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
461 NONUSE_FLX_PIT_DEST_OFF : \
462 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
463 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
464 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
465 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
466 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
467 #define I40E_FDIR_IPv6_TC_OFFSET 20
469 /* A structure used to define the input for GTP flow */
470 struct i40e_gtp_flow {
471 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */
472 uint8_t msg_type; /* Message type. */
473 uint32_t teid; /* TEID in big endian. */
476 /* A structure used to define the input for GTP IPV4 flow */
477 struct i40e_gtp_ipv4_flow {
478 struct i40e_gtp_flow gtp;
479 struct rte_eth_ipv4_flow ip4;
482 /* A structure used to define the input for GTP IPV6 flow */
483 struct i40e_gtp_ipv6_flow {
484 struct i40e_gtp_flow gtp;
485 struct rte_eth_ipv6_flow ip6;
488 /* A structure used to define the input for raw type flow */
489 struct i40e_raw_flow {
496 * A union contains the inputs for all types of flow
497 * items in flows need to be in big endian
499 union i40e_fdir_flow {
500 struct rte_eth_l2_flow l2_flow;
501 struct rte_eth_udpv4_flow udp4_flow;
502 struct rte_eth_tcpv4_flow tcp4_flow;
503 struct rte_eth_sctpv4_flow sctp4_flow;
504 struct rte_eth_ipv4_flow ip4_flow;
505 struct rte_eth_udpv6_flow udp6_flow;
506 struct rte_eth_tcpv6_flow tcp6_flow;
507 struct rte_eth_sctpv6_flow sctp6_flow;
508 struct rte_eth_ipv6_flow ipv6_flow;
509 struct i40e_gtp_flow gtp_flow;
510 struct i40e_gtp_ipv4_flow gtp_ipv4_flow;
511 struct i40e_gtp_ipv6_flow gtp_ipv6_flow;
512 struct i40e_raw_flow raw_flow;
515 enum i40e_fdir_ip_type {
516 I40E_FDIR_IPTYPE_IPV4,
517 I40E_FDIR_IPTYPE_IPV6,
520 /* A structure used to contain extend input of flow */
521 struct i40e_fdir_flow_ext {
523 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];
524 /* It is filled by the flexible payload to match. */
525 uint8_t is_vf; /* 1 for VF, 0 for port dev */
526 uint16_t dst_id; /* VF ID, available when is_vf is 1*/
527 bool inner_ip; /* If there is inner ip */
528 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */
529 bool customized_pctype; /* If customized pctype is used */
530 bool pkt_template; /* If raw packet template is used */
533 /* A structure used to define the input for a flow director filter entry */
534 struct i40e_fdir_input {
535 enum i40e_filter_pctype pctype;
536 union i40e_fdir_flow flow;
537 /* Flow fields to match, dependent on flow_type */
538 struct i40e_fdir_flow_ext flow_ext;
539 /* Additional fields to match */
542 /* Behavior will be taken if FDIR match */
543 enum i40e_fdir_behavior {
544 I40E_FDIR_ACCEPT = 0,
549 /* Flow director report status
550 * It defines what will be reported if FDIR entry is matched.
552 enum i40e_fdir_status {
553 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */
554 I40E_FDIR_REPORT_ID, /* Only report FD ID. */
555 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */
556 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */
559 /* A structure used to define an action when match FDIR packet filter. */
560 struct i40e_fdir_action {
561 uint16_t rx_queue; /* Queue assigned to if FDIR match. */
562 enum i40e_fdir_behavior behavior; /* Behavior will be taken */
563 enum i40e_fdir_status report_status; /* Status report option */
564 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or
565 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported
566 * flex bytes start from in flexible payload.
571 /* A structure used to define the flow director filter entry by filter_ctrl API
572 * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_ADD and
573 * RTE_ETH_FILTER_DELETE operations.
575 struct i40e_fdir_filter_conf {
577 /* ID, an unique value is required when deal with FDIR entry */
578 struct i40e_fdir_input input; /* Input set */
579 struct i40e_fdir_action action; /* Action taken when match */
583 * Structure to store flex pit for flow diretor.
585 struct i40e_fdir_flex_pit {
586 uint8_t src_offset; /* offset in words from the beginning of payload */
587 uint8_t size; /* size in words */
588 uint8_t dst_offset; /* offset in words of flexible payload */
591 struct i40e_fdir_flex_mask {
592 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
597 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
600 #define I40E_FILTER_PCTYPE_INVALID 0
601 #define I40E_FILTER_PCTYPE_MAX 64
602 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8)
604 struct i40e_fdir_filter {
605 TAILQ_ENTRY(i40e_fdir_filter) rules;
606 struct i40e_fdir_filter_conf fdir;
609 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter);
611 * A structure used to define fields of a FDIR related info.
613 struct i40e_fdir_info {
614 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
615 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
616 struct i40e_tx_queue *txq;
617 struct i40e_rx_queue *rxq;
618 void *prg_pkt; /* memory for fdir program packet */
619 uint64_t dma_addr; /* physic address of packet memory*/
620 /* input set bits for each pctype */
621 uint64_t input_set[I40E_FILTER_PCTYPE_MAX];
623 * the rule how bytes stream is extracted as flexible payload
624 * for each payload layer, the setting can up to three elements
626 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
627 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
629 struct i40e_fdir_filter_list fdir_list;
630 struct i40e_fdir_filter **hash_map;
631 struct rte_hash *hash_table;
633 /* Mark if flex pit and mask is set */
634 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER];
635 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX];
637 bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */
640 /* Ethertype filter number HW supports */
641 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768
643 /* Ethertype filter struct */
644 struct i40e_ethertype_filter_input {
645 struct ether_addr mac_addr; /* Mac address to match */
646 uint16_t ether_type; /* Ether type to match */
649 struct i40e_ethertype_filter {
650 TAILQ_ENTRY(i40e_ethertype_filter) rules;
651 struct i40e_ethertype_filter_input input;
652 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */
653 uint16_t queue; /* Queue assigned to when match */
656 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter);
658 struct i40e_ethertype_rule {
659 struct i40e_ethertype_filter_list ethertype_list;
660 struct i40e_ethertype_filter **hash_map;
661 struct rte_hash *hash_table;
664 /* queue region info */
665 struct i40e_queue_region_info {
666 /* the region id for this configuration */
668 /* the start queue index for this region */
669 uint8_t queue_start_index;
670 /* the total queue number of this queue region */
672 /* the total number of user priority for this region */
673 uint8_t user_priority_num;
674 /* the packet's user priority for this region */
675 uint8_t user_priority[I40E_MAX_USER_PRIORITY];
676 /* the total number of flowtype for this region */
677 uint8_t flowtype_num;
679 * the pctype or hardware flowtype of packet,
680 * the specific index for each type has been defined
681 * in file i40e_type.h as enum i40e_filter_pctype.
683 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX];
686 struct i40e_queue_regions {
687 /* the total number of queue region for this port */
688 uint16_t queue_region_number;
689 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1];
692 /* Tunnel filter number HW supports */
693 #define I40E_MAX_TUNNEL_FILTER_NUM 400
695 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44
696 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45
697 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8
698 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9
699 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10
700 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11
701 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12
702 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11
703 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12
704 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13
705 #define I40E_AQC_NEW_TR_21 21
706 #define I40E_AQC_NEW_TR_22 22
708 enum i40e_tunnel_iptype {
709 I40E_TUNNEL_IPTYPE_IPV4,
710 I40E_TUNNEL_IPTYPE_IPV6,
713 /* Tunnel filter struct */
714 struct i40e_tunnel_filter_input {
715 uint8_t outer_mac[6]; /* Outer mac address to match */
716 uint8_t inner_mac[6]; /* Inner mac address to match */
717 uint16_t inner_vlan; /* Inner vlan address to match */
718 enum i40e_tunnel_iptype ip_type;
719 uint16_t flags; /* Filter type flag */
720 uint32_t tenant_id; /* Tenant id to match */
721 uint16_t general_fields[32]; /* Big buffer */
724 struct i40e_tunnel_filter {
725 TAILQ_ENTRY(i40e_tunnel_filter) rules;
726 struct i40e_tunnel_filter_input input;
727 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */
728 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */
729 uint16_t queue; /* Queue assigned to when match */
732 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter);
734 struct i40e_tunnel_rule {
735 struct i40e_tunnel_filter_list tunnel_list;
736 struct i40e_tunnel_filter **hash_map;
737 struct rte_hash *hash_table;
743 enum i40e_tunnel_type {
744 I40E_TUNNEL_TYPE_NONE = 0,
745 I40E_TUNNEL_TYPE_VXLAN,
746 I40E_TUNNEL_TYPE_GENEVE,
747 I40E_TUNNEL_TYPE_TEREDO,
748 I40E_TUNNEL_TYPE_NVGRE,
749 I40E_TUNNEL_TYPE_IP_IN_GRE,
750 I40E_L2_TUNNEL_TYPE_E_TAG,
751 I40E_TUNNEL_TYPE_MPLSoUDP,
752 I40E_TUNNEL_TYPE_MPLSoGRE,
753 I40E_TUNNEL_TYPE_QINQ,
754 I40E_TUNNEL_TYPE_GTPC,
755 I40E_TUNNEL_TYPE_GTPU,
756 I40E_TUNNEL_TYPE_MAX,
760 * Tunneling Packet filter configuration.
762 struct i40e_tunnel_filter_conf {
763 struct ether_addr outer_mac; /**< Outer MAC address to match. */
764 struct ether_addr inner_mac; /**< Inner MAC address to match. */
765 uint16_t inner_vlan; /**< Inner VLAN to match. */
766 uint32_t outer_vlan; /**< Outer VLAN to match */
767 enum i40e_tunnel_iptype ip_type; /**< IP address type. */
769 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP
770 * is set in filter_type, or inner destination IP address to match
771 * if ETH_TUNNEL_FILTER_IIP is set in filter_type.
774 uint32_t ipv4_addr; /**< IPv4 address in big endian. */
775 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */
777 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */
778 uint16_t filter_type;
779 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */
780 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */
781 uint16_t queue_id; /**< Queue assigned to if match. */
782 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */
783 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */
786 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
787 #define I40E_MAX_MIRROR_RULES 64
789 * Mirror rule structure
791 struct i40e_mirror_rule {
792 TAILQ_ENTRY(i40e_mirror_rule) rules;
794 uint16_t index; /* the sw index of mirror rule */
795 uint16_t id; /* the rule id assigned by firmware */
796 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
797 uint16_t num_entries;
798 /* the info stores depend on the rule type.
799 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
800 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
802 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
805 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
808 * Struct to store flow created.
811 TAILQ_ENTRY(rte_flow) node;
812 enum rte_filter_type filter_type;
816 TAILQ_HEAD(i40e_flow_list, rte_flow);
818 /* Struct to store Traffic Manager shaper profile. */
819 struct i40e_tm_shaper_profile {
820 TAILQ_ENTRY(i40e_tm_shaper_profile) node;
821 uint32_t shaper_profile_id;
822 uint32_t reference_count;
823 struct rte_tm_shaper_params profile;
826 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile);
828 /* node type of Traffic Manager */
829 enum i40e_tm_node_type {
830 I40E_TM_NODE_TYPE_PORT,
831 I40E_TM_NODE_TYPE_TC,
832 I40E_TM_NODE_TYPE_QUEUE,
833 I40E_TM_NODE_TYPE_MAX,
836 /* Struct to store Traffic Manager node configuration. */
837 struct i40e_tm_node {
838 TAILQ_ENTRY(i40e_tm_node) node;
842 uint32_t reference_count;
843 struct i40e_tm_node *parent;
844 struct i40e_tm_shaper_profile *shaper_profile;
845 struct rte_tm_node_params params;
848 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node);
850 /* Struct to store all the Traffic Manager configuration. */
851 struct i40e_tm_conf {
852 struct i40e_shaper_profile_list shaper_profile_list;
853 struct i40e_tm_node *root; /* root node - port */
854 struct i40e_tm_node_list tc_list; /* node list for all the TCs */
855 struct i40e_tm_node_list queue_list; /* node list for all the queues */
857 * The number of added TC nodes.
858 * It should be no more than the TC number of this port.
862 * The number of added queue nodes.
863 * It should be no more than the queue number of this port.
865 uint32_t nb_queue_node;
867 * This flag is used to check if APP can change the TM node
869 * When it's true, means the configuration is applied to HW,
870 * APP should not change the configuration.
871 * As we don't support on-the-fly configuration, when starting
872 * the port, APP should call the hierarchy_commit API to set this
873 * flag to true. When stopping the port, this flag should be set
879 enum i40e_new_pctype {
880 I40E_CUSTOMIZED_GTPC = 0,
881 I40E_CUSTOMIZED_GTPU_IPV4,
882 I40E_CUSTOMIZED_GTPU_IPV6,
883 I40E_CUSTOMIZED_GTPU,
887 #define I40E_FILTER_PCTYPE_INVALID 0
888 struct i40e_customized_pctype {
889 enum i40e_new_pctype index; /* Indicate which customized pctype */
890 uint8_t pctype; /* New pctype value */
891 bool valid; /* Check if it's valid */
895 * Structure to store private data specific for PF instance.
898 struct i40e_adapter *adapter; /* The adapter this PF associate to */
899 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
900 uint16_t mac_seid; /* The seid of the MAC of this PF */
901 uint16_t main_vsi_seid; /* The seid of the main VSI */
902 uint16_t max_num_vsi;
903 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
904 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
906 struct i40e_hw_port_stats stats_offset;
907 struct i40e_hw_port_stats stats;
908 /* internal packet statistics, it should be excluded from the total */
909 struct i40e_eth_stats internal_stats_offset;
910 struct i40e_eth_stats internal_stats;
913 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
914 struct ether_addr dev_addr; /* PF device mac address */
915 uint64_t flags; /* PF feature flags */
916 /* All kinds of queue pair setting for different VSIs */
917 struct i40e_pf_vf *vfs;
919 /* Each of below queue pairs should be power of 2 since it's the
920 precondition after TC configuration applied */
921 uint16_t lan_nb_qp_max;
922 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
923 uint16_t lan_qp_offset;
924 uint16_t vmdq_nb_qp_max;
925 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
926 uint16_t vmdq_qp_offset;
927 uint16_t vf_nb_qp_max;
928 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
929 uint16_t vf_qp_offset;
930 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
931 uint16_t fdir_qp_offset;
933 uint16_t hash_lut_size; /* The size of hash lookup table */
934 /* input set bits for each pctype */
935 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX];
936 /* store VXLAN UDP ports */
937 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
938 uint16_t vxlan_bitmap; /* Vxlan bit mask */
940 /* VMDQ related info */
941 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
942 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
943 struct i40e_vmdq_info *vmdq;
945 struct i40e_fdir_info fdir; /* flow director info */
946 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */
947 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */
948 struct i40e_queue_regions queue_region; /* queue region info */
949 struct i40e_fc_conf fc_conf; /* Flow control conf */
950 struct i40e_mirror_rule_list mirror_list;
951 uint16_t nb_mirror_rule; /* The number of mirror rules */
952 bool floating_veb; /* The flag to use the floating VEB */
953 /* The floating enable flag for the specific VF */
954 bool floating_veb_list[I40E_MAX_VF];
955 struct i40e_flow_list flow_list;
956 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */
957 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */
958 bool qinq_replace_flag; /* QINQ filter replace is done */
959 struct i40e_tm_conf tm_conf;
961 /* Dynamic Device Personalization */
962 bool gtp_support; /* 1 - support GTP-C and GTP-U */
963 /* customer customized pctype */
964 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX];
968 PFMSG_LINK_CHANGE = 0x1,
969 PFMSG_RESET_IMPENDING = 0x2,
970 PFMSG_DRIVER_CLOSE = 0x4,
973 struct i40e_vsi_vlan_pvid_info {
974 uint16_t on; /* Enable or disable pvid */
976 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
978 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
979 * while 'untagged' will reject untagged packets.
987 struct i40e_vf_rx_queues {
988 uint64_t rx_dma_addr;
989 uint32_t rx_ring_len;
993 struct i40e_vf_tx_queues {
994 uint64_t tx_dma_addr;
995 uint32_t tx_ring_len;
999 * Structure to store private data specific for VF instance.
1002 struct i40e_adapter *adapter; /* The adapter this VF associate to */
1003 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
1004 uint16_t num_queue_pairs;
1005 uint16_t max_pkt_len; /* Maximum packet length */
1006 bool promisc_unicast_enabled;
1007 bool promisc_multicast_enabled;
1009 uint32_t version_major; /* Major version number */
1010 uint32_t version_minor; /* Minor version number */
1011 uint16_t promisc_flags; /* Promiscuous setting */
1012 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
1017 enum virtchnl_link_speed link_speed;
1019 volatile uint32_t pend_cmd; /* pending command not finished yet */
1020 int32_t cmd_retval; /* return value of the cmd response from PF */
1021 u16 pend_msg; /* flags indicates events from pf not handled yet */
1022 uint8_t *aq_resp; /* buffer to store the adminq response from PF */
1025 struct virtchnl_vf_resource *vf_res; /* All VSIs */
1026 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */
1027 struct i40e_vsi vsi;
1031 #define I40E_MAX_PKT_TYPE 256
1032 #define I40E_FLOW_TYPE_MAX 64
1035 * Structure to store private data for each PF/VF instance.
1037 struct i40e_adapter {
1038 /* Common for both PF and VF */
1040 struct rte_eth_dev *eth_dev;
1042 /* Specific for PF or VF */
1048 /* For vector PMD */
1049 bool rx_bulk_alloc_allowed;
1050 bool rx_vec_allowed;
1051 bool tx_simple_allowed;
1052 bool tx_vec_allowed;
1055 struct rte_timecounter systime_tc;
1056 struct rte_timecounter rx_tstamp_tc;
1057 struct rte_timecounter tx_tstamp_tc;
1059 /* ptype mapping table */
1060 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned;
1061 /* flow type to pctype mapping table */
1062 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned;
1063 uint64_t flow_types_mask;
1064 uint64_t pctypes_mask;
1067 extern const struct rte_flow_ops i40e_flow_ops;
1069 union i40e_filter_t {
1070 struct rte_eth_ethertype_filter ethertype_filter;
1071 struct i40e_fdir_filter_conf fdir_filter;
1072 struct rte_eth_tunnel_filter_conf tunnel_filter;
1073 struct i40e_tunnel_filter_conf consistent_tunnel_filter;
1076 typedef int (*parse_filter_t)(struct rte_eth_dev *dev,
1077 const struct rte_flow_attr *attr,
1078 const struct rte_flow_item pattern[],
1079 const struct rte_flow_action actions[],
1080 struct rte_flow_error *error,
1081 union i40e_filter_t *filter);
1082 struct i40e_valid_pattern {
1083 enum rte_flow_item_type *items;
1084 parse_filter_t parse_filter;
1087 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
1088 int i40e_vsi_release(struct i40e_vsi *vsi);
1089 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
1090 enum i40e_vsi_type type,
1091 struct i40e_vsi *uplink_vsi,
1092 uint16_t user_param);
1093 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1094 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1095 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1096 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1097 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
1098 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);
1099 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
1100 void i40e_pf_disable_irq0(struct i40e_hw *hw);
1101 void i40e_pf_enable_irq0(struct i40e_hw *hw);
1102 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete);
1103 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx);
1104 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
1105 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
1106 struct i40e_vsi_vlan_pvid_info *info);
1107 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
1108 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on);
1109 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags);
1110 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags);
1111 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
1112 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
1113 int i40e_fdir_setup(struct i40e_pf *pf);
1114 const struct rte_memzone *i40e_memzone_reserve(const char *name,
1117 int i40e_fdir_configure(struct rte_eth_dev *dev);
1118 void i40e_fdir_teardown(struct i40e_pf *pf);
1119 enum i40e_filter_pctype
1120 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter,
1121 uint16_t flow_type);
1122 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
1123 enum i40e_filter_pctype pctype);
1124 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1125 enum rte_filter_op filter_op,
1127 int i40e_select_filter_input_set(struct i40e_hw *hw,
1128 struct rte_eth_input_set_conf *conf,
1129 enum rte_filter_type filter);
1130 void i40e_fdir_filter_restore(struct i40e_pf *pf);
1131 int i40e_hash_filter_inset_select(struct i40e_hw *hw,
1132 struct rte_eth_input_set_conf *conf);
1133 int i40e_fdir_filter_inset_select(struct i40e_pf *pf,
1134 struct rte_eth_input_set_conf *conf);
1135 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode,
1136 uint32_t retval, uint8_t *msg,
1138 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1139 struct rte_eth_rxq_info *qinfo);
1140 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1141 struct rte_eth_txq_info *qinfo);
1142 struct i40e_ethertype_filter *
1143 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
1144 const struct i40e_ethertype_filter_input *input);
1145 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
1146 struct i40e_ethertype_filter_input *input);
1147 int i40e_sw_fdir_filter_del(struct i40e_pf *pf,
1148 struct i40e_fdir_input *input);
1149 struct i40e_tunnel_filter *
1150 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
1151 const struct i40e_tunnel_filter_input *input);
1152 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
1153 struct i40e_tunnel_filter_input *input);
1154 uint64_t i40e_get_default_input_set(uint16_t pctype);
1155 int i40e_ethertype_filter_set(struct i40e_pf *pf,
1156 struct rte_eth_ethertype_filter *filter,
1158 int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1159 const struct rte_eth_fdir_filter *filter,
1161 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
1162 const struct i40e_fdir_filter_conf *filter,
1164 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
1165 struct rte_eth_tunnel_filter_conf *tunnel_filter,
1167 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
1168 struct i40e_tunnel_filter_conf *tunnel_filter,
1170 int i40e_fdir_flush(struct rte_eth_dev *dev);
1171 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
1172 struct i40e_macvlan_filter *mv_f,
1173 int num, struct ether_addr *addr);
1174 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
1175 struct i40e_macvlan_filter *filter,
1177 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on);
1178 int i40e_add_macvlan_filters(struct i40e_vsi *vsi,
1179 struct i40e_macvlan_filter *filter,
1181 bool is_i40e_supported(struct rte_eth_dev *dev);
1183 int i40e_validate_input_set(enum i40e_filter_pctype pctype,
1184 enum rte_filter_type filter, uint64_t inset);
1185 int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
1187 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
1188 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);
1190 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops);
1191 void i40e_tm_conf_init(struct rte_eth_dev *dev);
1192 void i40e_tm_conf_uninit(struct rte_eth_dev *dev);
1193 struct i40e_customized_pctype*
1194 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index);
1195 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
1197 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
1198 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev,
1199 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on);
1200 void i40e_init_queue_region_conf(struct rte_eth_dev *dev);
1202 #define I40E_DEV_TO_PCI(eth_dev) \
1203 RTE_DEV_TO_PCI((eth_dev)->device)
1205 /* I40E_DEV_PRIVATE_TO */
1206 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
1207 (&((struct i40e_adapter *)adapter)->pf)
1208 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
1209 (&((struct i40e_adapter *)adapter)->hw)
1210 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
1211 ((struct i40e_adapter *)adapter)
1213 /* I40EVF_DEV_PRIVATE_TO */
1214 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
1215 (&((struct i40e_adapter *)adapter)->vf)
1217 static inline struct i40e_vsi *
1218 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
1225 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
1226 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1227 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
1230 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
1231 return pf->main_vsi;
1234 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
1235 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
1238 #define I40E_VSI_TO_HW(vsi) \
1239 (&(((struct i40e_vsi *)vsi)->adapter->hw))
1240 #define I40E_VSI_TO_PF(vsi) \
1241 (&(((struct i40e_vsi *)vsi)->adapter->pf))
1242 #define I40E_VSI_TO_VF(vsi) \
1243 (&(((struct i40e_vsi *)vsi)->adapter->vf))
1244 #define I40E_VSI_TO_DEV_DATA(vsi) \
1245 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
1246 #define I40E_VSI_TO_ETH_DEV(vsi) \
1247 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
1250 #define I40E_PF_TO_HW(pf) \
1251 (&(((struct i40e_pf *)pf)->adapter->hw))
1252 #define I40E_PF_TO_ADAPTER(pf) \
1253 ((struct i40e_adapter *)pf->adapter)
1256 #define I40E_VF_TO_HW(vf) \
1257 (&(((struct i40e_vf *)vf)->adapter->hw))
1260 i40e_init_adminq_parameter(struct i40e_hw *hw)
1262 hw->aq.num_arq_entries = I40E_AQ_LEN;
1263 hw->aq.num_asq_entries = I40E_AQ_LEN;
1264 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
1265 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
1269 i40e_align_floor(int n)
1273 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
1276 static inline uint16_t
1277 i40e_calc_itr_interval(int16_t interval)
1279 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
1280 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
1282 /* Convert to hardware count, as writing each 1 represents 2 us */
1283 return interval / 2;
1286 #define I40E_VALID_FLOW(flow_type) \
1287 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
1288 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
1289 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
1290 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
1291 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
1292 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
1293 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
1294 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
1295 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
1296 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
1297 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
1299 #define I40E_VALID_PCTYPE_X722(pctype) \
1300 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1301 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1302 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \
1303 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1304 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \
1305 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \
1306 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1307 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1308 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1309 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1310 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \
1311 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \
1312 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1313 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \
1314 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1315 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1316 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1318 #define I40E_VALID_PCTYPE(pctype) \
1319 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1320 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1321 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1322 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1323 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1324 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1325 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1326 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1327 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1328 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1329 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1331 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
1332 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
1333 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \
1334 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \
1335 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \
1336 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
1337 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
1339 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
1340 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
1341 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
1342 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
1343 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR))
1345 #endif /* _I40E_ETHDEV_H_ */