4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
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22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
51 #include "i40e_logs.h"
52 #include "base/i40e_prototype.h"
53 #include "base/i40e_adminq_cmd.h"
54 #include "base/i40e_type.h"
55 #include "i40e_ethdev.h"
56 #include "i40e_rxtx.h"
59 #define I40E_CFG_CRCSTRIP_DEFAULT 1
62 i40e_pf_host_switch_queues(struct i40e_pf_vf *vf,
63 struct i40e_virtchnl_queue_select *qsel,
67 * Bind PF queues with VSI and VF.
70 i40e_pf_vf_queues_mapping(struct i40e_pf_vf *vf)
73 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
74 uint16_t vsi_id = vf->vsi->vsi_id;
75 uint16_t vf_id = vf->vf_idx;
76 uint16_t nb_qps = vf->vsi->nb_qps;
77 uint16_t qbase = vf->vsi->base_queue;
82 * VF should use scatter range queues. So, it needn't
83 * to set QBASE in this register.
85 I40E_WRITE_REG(hw, I40E_VSILAN_QBASE(vsi_id),
86 I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);
88 /* Set to enable VFLAN_QTABLE[] registers valid */
89 I40E_WRITE_REG(hw, I40E_VPLAN_MAPENA(vf_id),
90 I40E_VPLAN_MAPENA_TXRX_ENA_MASK);
92 /* map PF queues to VF */
93 for (i = 0; i < nb_qps; i++) {
94 val = ((qbase + i) & I40E_VPLAN_QTABLE_QINDEX_MASK);
95 I40E_WRITE_REG(hw, I40E_VPLAN_QTABLE(i, vf_id), val);
98 /* map PF queues to VSI */
99 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF / 2; i++) {
100 if (2 * i > nb_qps - 1)
101 q1 = I40E_VSILAN_QTABLE_QINDEX_0_MASK;
105 if (2 * i + 1 > nb_qps - 1)
106 q2 = I40E_VSILAN_QTABLE_QINDEX_0_MASK;
108 q2 = qbase + 2 * i + 1;
110 val = (q2 << I40E_VSILAN_QTABLE_QINDEX_1_SHIFT) + q1;
111 I40E_WRITE_REG(hw, I40E_VSILAN_QTABLE(i, vsi_id), val);
113 I40E_WRITE_FLUSH(hw);
120 * Proceed VF reset operation.
123 i40e_pf_host_vf_reset(struct i40e_pf_vf *vf, bool do_hw_reset)
126 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
127 uint16_t vf_id, abs_vf_id, vf_msix_num;
129 struct i40e_virtchnl_queue_select qsel;
135 abs_vf_id = vf_id + hw->func_caps.vf_base_id;
137 /* Notify VF that we are in VFR progress */
138 I40E_WRITE_REG(hw, I40E_VFGEN_RSTAT1(vf_id), I40E_PF_VFR_INPROGRESS);
141 * If require a SW VF reset, a VFLR interrupt will be generated,
142 * this function will be called again. To avoid it,
143 * disable interrupt first.
146 vf->state = I40E_VF_INRESET;
147 val = I40E_READ_REG(hw, I40E_VPGEN_VFRTRIG(vf_id));
148 val |= I40E_VPGEN_VFRTRIG_VFSWR_MASK;
149 I40E_WRITE_REG(hw, I40E_VPGEN_VFRTRIG(vf_id), val);
150 I40E_WRITE_FLUSH(hw);
153 #define VFRESET_MAX_WAIT_CNT 100
154 /* Wait until VF reset is done */
155 for (i = 0; i < VFRESET_MAX_WAIT_CNT; i++) {
157 val = I40E_READ_REG(hw, I40E_VPGEN_VFRSTAT(vf_id));
158 if (val & I40E_VPGEN_VFRSTAT_VFRD_MASK)
162 if (i >= VFRESET_MAX_WAIT_CNT) {
163 PMD_DRV_LOG(ERR, "VF reset timeout");
167 /* This is not first time to do reset, do cleanup job first */
170 memset(&qsel, 0, sizeof(qsel));
171 for (i = 0; i < vf->vsi->nb_qps; i++)
172 qsel.rx_queues |= 1 << i;
173 qsel.tx_queues = qsel.rx_queues;
174 ret = i40e_pf_host_switch_queues(vf, &qsel, false);
175 if (ret != I40E_SUCCESS) {
176 PMD_DRV_LOG(ERR, "Disable VF queues failed");
180 /* Disable VF interrupt setting */
181 vf_msix_num = hw->func_caps.num_msix_vectors_vf;
182 for (i = 0; i < vf_msix_num; i++) {
184 val = I40E_VFINT_DYN_CTL0(vf_id);
186 val = I40E_VFINT_DYN_CTLN(((vf_msix_num - 1) *
188 I40E_WRITE_REG(hw, val, I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
190 I40E_WRITE_FLUSH(hw);
193 ret = i40e_vsi_release(vf->vsi);
194 if (ret != I40E_SUCCESS) {
195 PMD_DRV_LOG(ERR, "Release VSI failed");
200 #define I40E_VF_PCI_ADDR 0xAA
201 #define I40E_VF_PEND_MASK 0x20
202 /* Check the pending transactions of this VF */
203 /* Use absolute VF id, refer to datasheet for details */
204 I40E_WRITE_REG(hw, I40E_PF_PCI_CIAA, I40E_VF_PCI_ADDR |
205 (abs_vf_id << I40E_PF_PCI_CIAA_VF_NUM_SHIFT));
206 for (i = 0; i < VFRESET_MAX_WAIT_CNT; i++) {
208 val = I40E_READ_REG(hw, I40E_PF_PCI_CIAD);
209 if ((val & I40E_VF_PEND_MASK) == 0)
213 if (i >= VFRESET_MAX_WAIT_CNT) {
214 PMD_DRV_LOG(ERR, "Wait VF PCI transaction end timeout");
218 /* Reset done, Set COMPLETE flag and clear reset bit */
219 I40E_WRITE_REG(hw, I40E_VFGEN_RSTAT1(vf_id), I40E_PF_VFR_COMPLETED);
220 val = I40E_READ_REG(hw, I40E_VPGEN_VFRTRIG(vf_id));
221 val &= ~I40E_VPGEN_VFRTRIG_VFSWR_MASK;
222 I40E_WRITE_REG(hw, I40E_VPGEN_VFRTRIG(vf_id), val);
224 I40E_WRITE_FLUSH(hw);
226 /* Allocate resource again */
227 vf->vsi = i40e_vsi_setup(vf->pf, I40E_VSI_SRIOV,
228 vf->pf->main_vsi, vf->vf_idx);
229 if (vf->vsi == NULL) {
230 PMD_DRV_LOG(ERR, "Add vsi failed");
234 ret = i40e_pf_vf_queues_mapping(vf);
235 if (ret != I40E_SUCCESS) {
236 PMD_DRV_LOG(ERR, "queue mapping error");
237 i40e_vsi_release(vf->vsi);
245 i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf,
251 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
252 uint16_t abs_vf_id = hw->func_caps.vf_base_id + vf->vf_idx;
255 ret = i40e_aq_send_msg_to_vf(hw, abs_vf_id, opcode, retval,
258 PMD_INIT_LOG(ERR, "Fail to send message to VF, err %u",
259 hw->aq.asq_last_status);
266 i40e_pf_host_process_cmd_version(struct i40e_pf_vf *vf)
268 struct i40e_virtchnl_version_info info;
270 info.major = I40E_DPDK_VERSION_MAJOR;
271 info.minor = I40E_DPDK_VERSION_MINOR;
272 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_VERSION,
273 I40E_SUCCESS, (uint8_t *)&info, sizeof(info));
277 i40e_pf_host_process_cmd_reset_vf(struct i40e_pf_vf *vf)
279 i40e_pf_host_vf_reset(vf, 1);
281 /* No feedback will be sent to VF for VFLR */
286 i40e_pf_host_process_cmd_get_vf_resource(struct i40e_pf_vf *vf)
288 struct i40e_virtchnl_vf_resource *vf_res = NULL;
289 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
291 int ret = I40E_SUCCESS;
293 /* only have 1 VSI by default */
294 len = sizeof(struct i40e_virtchnl_vf_resource) +
295 I40E_DEFAULT_VF_VSI_NUM *
296 sizeof(struct i40e_virtchnl_vsi_resource);
298 vf_res = rte_zmalloc("i40e_vf_res", len, 0);
299 if (vf_res == NULL) {
300 PMD_DRV_LOG(ERR, "failed to allocate mem");
301 ret = I40E_ERR_NO_MEMORY;
307 vf_res->vf_offload_flags = I40E_VIRTCHNL_VF_OFFLOAD_L2 |
308 I40E_VIRTCHNL_VF_OFFLOAD_VLAN;
309 vf_res->max_vectors = hw->func_caps.num_msix_vectors_vf;
310 vf_res->num_queue_pairs = vf->vsi->nb_qps;
311 vf_res->num_vsis = I40E_DEFAULT_VF_VSI_NUM;
313 /* Change below setting if PF host can support more VSIs for VF */
314 vf_res->vsi_res[0].vsi_type = I40E_VSI_SRIOV;
315 /* As assume Vf only has single VSI now, always return 0 */
316 vf_res->vsi_res[0].vsi_id = 0;
317 vf_res->vsi_res[0].num_queue_pairs = vf->vsi->nb_qps;
320 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_GET_VF_RESOURCES,
321 ret, (uint8_t *)vf_res, len);
328 i40e_pf_host_hmc_config_rxq(struct i40e_hw *hw,
329 struct i40e_pf_vf *vf,
330 struct i40e_virtchnl_rxq_info *rxq,
333 int err = I40E_SUCCESS;
334 struct i40e_hmc_obj_rxq rx_ctx;
335 uint16_t abs_queue_id = vf->vsi->base_queue + rxq->queue_id;
337 /* Clear the context structure first */
338 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
339 rx_ctx.dbuff = rxq->databuffer_size >> I40E_RXQ_CTX_DBUFF_SHIFT;
340 rx_ctx.hbuff = rxq->hdr_size >> I40E_RXQ_CTX_HBUFF_SHIFT;
341 rx_ctx.base = rxq->dma_ring_addr / I40E_QUEUE_BASE_ADDR_UNIT;
342 rx_ctx.qlen = rxq->ring_len;
343 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
347 if (rxq->splithdr_enabled) {
348 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
349 rx_ctx.dtype = i40e_header_split_enabled;
351 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
352 rx_ctx.dtype = i40e_header_split_none;
354 rx_ctx.rxmax = rxq->max_pkt_size;
355 rx_ctx.tphrdesc_ena = 1;
356 rx_ctx.tphwdesc_ena = 1;
357 rx_ctx.tphdata_ena = 1;
358 rx_ctx.tphhead_ena = 1;
359 rx_ctx.lrxqthresh = 2;
360 rx_ctx.crcstrip = crcstrip;
364 err = i40e_clear_lan_rx_queue_context(hw, abs_queue_id);
365 if (err != I40E_SUCCESS)
367 err = i40e_set_lan_rx_queue_context(hw, abs_queue_id, &rx_ctx);
373 i40e_pf_host_hmc_config_txq(struct i40e_hw *hw,
374 struct i40e_pf_vf *vf,
375 struct i40e_virtchnl_txq_info *txq)
377 int err = I40E_SUCCESS;
378 struct i40e_hmc_obj_txq tx_ctx;
380 uint16_t abs_queue_id = vf->vsi->base_queue + txq->queue_id;
383 /* clear the context structure first */
384 memset(&tx_ctx, 0, sizeof(tx_ctx));
385 tx_ctx.new_context = 1;
386 tx_ctx.base = txq->dma_ring_addr / I40E_QUEUE_BASE_ADDR_UNIT;
387 tx_ctx.qlen = txq->ring_len;
388 tx_ctx.rdylist = rte_le_to_cpu_16(vf->vsi->info.qs_handle[0]);
389 err = i40e_clear_lan_tx_queue_context(hw, abs_queue_id);
390 if (err != I40E_SUCCESS)
393 err = i40e_set_lan_tx_queue_context(hw, abs_queue_id, &tx_ctx);
394 if (err != I40E_SUCCESS)
397 /* bind queue with VF function, since TX/QX will appear in pair,
398 * so only has QTX_CTL to set.
400 qtx_ctl = (I40E_QTX_CTL_VF_QUEUE << I40E_QTX_CTL_PFVF_Q_SHIFT) |
401 ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
402 I40E_QTX_CTL_PF_INDX_MASK) |
403 (((vf->vf_idx + hw->func_caps.vf_base_id) <<
404 I40E_QTX_CTL_VFVM_INDX_SHIFT) &
405 I40E_QTX_CTL_VFVM_INDX_MASK);
406 I40E_WRITE_REG(hw, I40E_QTX_CTL(abs_queue_id), qtx_ctl);
407 I40E_WRITE_FLUSH(hw);
413 i40e_pf_host_process_cmd_config_vsi_queues(struct i40e_pf_vf *vf,
417 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
418 struct i40e_vsi *vsi = vf->vsi;
419 struct i40e_virtchnl_vsi_queue_config_info *vc_vqci =
420 (struct i40e_virtchnl_vsi_queue_config_info *)msg;
421 struct i40e_virtchnl_queue_pair_info *vc_qpi;
422 int i, ret = I40E_SUCCESS;
424 if (!msg || vc_vqci->num_queue_pairs > vsi->nb_qps ||
425 vc_vqci->num_queue_pairs > I40E_MAX_VSI_QP ||
426 msglen < I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci,
427 vc_vqci->num_queue_pairs)) {
428 PMD_DRV_LOG(ERR, "vsi_queue_config_info argument wrong\n");
429 ret = I40E_ERR_PARAM;
433 vc_qpi = vc_vqci->qpair;
434 for (i = 0; i < vc_vqci->num_queue_pairs; i++) {
435 if (vc_qpi[i].rxq.queue_id > vsi->nb_qps - 1 ||
436 vc_qpi[i].txq.queue_id > vsi->nb_qps - 1) {
437 ret = I40E_ERR_PARAM;
442 * Apply VF RX queue setting to HMC.
443 * If the opcode is I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,
444 * then the extra information of
445 * 'struct i40e_virtchnl_queue_pair_extra_info' is needed,
446 * otherwise set the last parameter to NULL.
448 if (i40e_pf_host_hmc_config_rxq(hw, vf, &vc_qpi[i].rxq,
449 I40E_CFG_CRCSTRIP_DEFAULT) != I40E_SUCCESS) {
450 PMD_DRV_LOG(ERR, "Configure RX queue HMC failed");
451 ret = I40E_ERR_PARAM;
455 /* Apply VF TX queue setting to HMC */
456 if (i40e_pf_host_hmc_config_txq(hw, vf,
457 &vc_qpi[i].txq) != I40E_SUCCESS) {
458 PMD_DRV_LOG(ERR, "Configure TX queue HMC failed");
459 ret = I40E_ERR_PARAM;
465 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES,
472 i40e_pf_host_process_cmd_config_vsi_queues_ext(struct i40e_pf_vf *vf,
476 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
477 struct i40e_vsi *vsi = vf->vsi;
478 struct i40e_virtchnl_vsi_queue_config_ext_info *vc_vqcei =
479 (struct i40e_virtchnl_vsi_queue_config_ext_info *)msg;
480 struct i40e_virtchnl_queue_pair_ext_info *vc_qpei;
481 int i, ret = I40E_SUCCESS;
483 if (!msg || vc_vqcei->num_queue_pairs > vsi->nb_qps ||
484 vc_vqcei->num_queue_pairs > I40E_MAX_VSI_QP ||
485 msglen < I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei,
486 vc_vqcei->num_queue_pairs)) {
487 PMD_DRV_LOG(ERR, "vsi_queue_config_ext_info argument wrong\n");
488 ret = I40E_ERR_PARAM;
492 vc_qpei = vc_vqcei->qpair;
493 for (i = 0; i < vc_vqcei->num_queue_pairs; i++) {
494 if (vc_qpei[i].rxq.queue_id > vsi->nb_qps - 1 ||
495 vc_qpei[i].txq.queue_id > vsi->nb_qps - 1) {
496 ret = I40E_ERR_PARAM;
500 * Apply VF RX queue setting to HMC.
501 * If the opcode is I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,
502 * then the extra information of
503 * 'struct i40e_virtchnl_queue_pair_ext_info' is needed,
504 * otherwise set the last parameter to NULL.
506 if (i40e_pf_host_hmc_config_rxq(hw, vf, &vc_qpei[i].rxq,
507 vc_qpei[i].rxq_ext.crcstrip) != I40E_SUCCESS) {
508 PMD_DRV_LOG(ERR, "Configure RX queue HMC failed");
509 ret = I40E_ERR_PARAM;
513 /* Apply VF TX queue setting to HMC */
514 if (i40e_pf_host_hmc_config_txq(hw, vf, &vc_qpei[i].txq) !=
516 PMD_DRV_LOG(ERR, "Configure TX queue HMC failed");
517 ret = I40E_ERR_PARAM;
523 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,
530 i40e_pf_host_process_cmd_config_irq_map(struct i40e_pf_vf *vf,
531 uint8_t *msg, uint16_t msglen)
533 int ret = I40E_SUCCESS;
534 struct i40e_virtchnl_irq_map_info *irqmap =
535 (struct i40e_virtchnl_irq_map_info *)msg;
537 if (msg == NULL || msglen < sizeof(struct i40e_virtchnl_irq_map_info)) {
538 PMD_DRV_LOG(ERR, "buffer too short");
539 ret = I40E_ERR_PARAM;
543 /* Assume VF only have 1 vector to bind all queues */
544 if (irqmap->num_vectors != 1) {
545 PMD_DRV_LOG(ERR, "DKDK host only support 1 vector");
546 ret = I40E_ERR_PARAM;
550 /* This MSIX intr store the intr in VF range */
551 vf->vsi->msix_intr = irqmap->vecmap[0].vector_id;
552 vf->vsi->nb_msix = irqmap->num_vectors;
553 vf->vsi->nb_used_qps = vf->vsi->nb_qps;
555 /* Don't care how the TX/RX queue mapping with this vector.
556 * Link all VF RX queues together. Only did mapping work.
557 * VF can disable/enable the intr by itself.
559 i40e_vsi_queues_bind_intr(vf->vsi);
561 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP,
568 i40e_pf_host_switch_queues(struct i40e_pf_vf *vf,
569 struct i40e_virtchnl_queue_select *qsel,
572 int ret = I40E_SUCCESS;
574 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
575 uint16_t baseq = vf->vsi->base_queue;
577 if (qsel->rx_queues + qsel->tx_queues == 0)
578 return I40E_ERR_PARAM;
580 /* always enable RX first and disable last */
581 /* Enable RX if it's enable */
583 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
584 if (qsel->rx_queues & (1 << i)) {
585 ret = i40e_switch_rx_queue(hw, baseq + i, on);
586 if (ret != I40E_SUCCESS)
591 /* Enable/Disable TX */
592 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
593 if (qsel->tx_queues & (1 << i)) {
594 ret = i40e_switch_tx_queue(hw, baseq + i, on);
595 if (ret != I40E_SUCCESS)
599 /* disable RX last if it's disable */
602 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
603 if (qsel->rx_queues & (1 << i)) {
604 ret = i40e_switch_rx_queue(hw, baseq + i, on);
605 if (ret != I40E_SUCCESS)
614 i40e_pf_host_process_cmd_enable_queues(struct i40e_pf_vf *vf,
618 int ret = I40E_SUCCESS;
619 struct i40e_virtchnl_queue_select *q_sel =
620 (struct i40e_virtchnl_queue_select *)msg;
622 if (msg == NULL || msglen != sizeof(*q_sel)) {
623 ret = I40E_ERR_PARAM;
626 ret = i40e_pf_host_switch_queues(vf, q_sel, true);
629 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_ENABLE_QUEUES,
636 i40e_pf_host_process_cmd_disable_queues(struct i40e_pf_vf *vf,
640 int ret = I40E_SUCCESS;
641 struct i40e_virtchnl_queue_select *q_sel =
642 (struct i40e_virtchnl_queue_select *)msg;
644 if (msg == NULL || msglen != sizeof(*q_sel)) {
645 ret = I40E_ERR_PARAM;
648 ret = i40e_pf_host_switch_queues(vf, q_sel, false);
651 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_DISABLE_QUEUES,
659 i40e_pf_host_process_cmd_add_ether_address(struct i40e_pf_vf *vf,
663 int ret = I40E_SUCCESS;
664 struct i40e_virtchnl_ether_addr_list *addr_list =
665 (struct i40e_virtchnl_ether_addr_list *)msg;
666 struct i40e_mac_filter_info filter;
668 struct ether_addr *mac;
670 memset(&filter, 0 , sizeof(struct i40e_mac_filter_info));
672 if (msg == NULL || msglen <= sizeof(*addr_list)) {
673 PMD_DRV_LOG(ERR, "add_ether_address argument too short");
674 ret = I40E_ERR_PARAM;
678 for (i = 0; i < addr_list->num_elements; i++) {
679 mac = (struct ether_addr *)(addr_list->list[i].addr);
680 (void)rte_memcpy(&filter.mac_addr, mac, ETHER_ADDR_LEN);
681 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
682 if(!is_valid_assigned_ether_addr(mac) ||
683 i40e_vsi_add_mac(vf->vsi, &filter)) {
684 ret = I40E_ERR_INVALID_MAC_ADDR;
690 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS,
697 i40e_pf_host_process_cmd_del_ether_address(struct i40e_pf_vf *vf,
701 int ret = I40E_SUCCESS;
702 struct i40e_virtchnl_ether_addr_list *addr_list =
703 (struct i40e_virtchnl_ether_addr_list *)msg;
705 struct ether_addr *mac;
707 if (msg == NULL || msglen <= sizeof(*addr_list)) {
708 PMD_DRV_LOG(ERR, "delete_ether_address argument too short");
709 ret = I40E_ERR_PARAM;
713 for (i = 0; i < addr_list->num_elements; i++) {
714 mac = (struct ether_addr *)(addr_list->list[i].addr);
715 if(!is_valid_assigned_ether_addr(mac) ||
716 i40e_vsi_delete_mac(vf->vsi, mac)) {
717 ret = I40E_ERR_INVALID_MAC_ADDR;
723 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS,
730 i40e_pf_host_process_cmd_add_vlan(struct i40e_pf_vf *vf,
731 uint8_t *msg, uint16_t msglen)
733 int ret = I40E_SUCCESS;
734 struct i40e_virtchnl_vlan_filter_list *vlan_filter_list =
735 (struct i40e_virtchnl_vlan_filter_list *)msg;
739 if (msg == NULL || msglen <= sizeof(*vlan_filter_list)) {
740 PMD_DRV_LOG(ERR, "add_vlan argument too short");
741 ret = I40E_ERR_PARAM;
745 vid = vlan_filter_list->vlan_id;
747 for (i = 0; i < vlan_filter_list->num_elements; i++) {
748 ret = i40e_vsi_add_vlan(vf->vsi, vid[i]);
749 if(ret != I40E_SUCCESS)
754 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_ADD_VLAN,
761 i40e_pf_host_process_cmd_del_vlan(struct i40e_pf_vf *vf,
765 int ret = I40E_SUCCESS;
766 struct i40e_virtchnl_vlan_filter_list *vlan_filter_list =
767 (struct i40e_virtchnl_vlan_filter_list *)msg;
771 if (msg == NULL || msglen <= sizeof(*vlan_filter_list)) {
772 PMD_DRV_LOG(ERR, "delete_vlan argument too short");
773 ret = I40E_ERR_PARAM;
777 vid = vlan_filter_list->vlan_id;
778 for (i = 0; i < vlan_filter_list->num_elements; i++) {
779 ret = i40e_vsi_delete_vlan(vf->vsi, vid[i]);
780 if(ret != I40E_SUCCESS)
785 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_DEL_VLAN,
792 i40e_pf_host_process_cmd_config_promisc_mode(
793 struct i40e_pf_vf *vf,
797 int ret = I40E_SUCCESS;
798 struct i40e_virtchnl_promisc_info *promisc =
799 (struct i40e_virtchnl_promisc_info *)msg;
800 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
801 bool unicast = FALSE, multicast = FALSE;
803 if (msg == NULL || msglen != sizeof(*promisc)) {
804 ret = I40E_ERR_PARAM;
808 if (promisc->flags & I40E_FLAG_VF_UNICAST_PROMISC)
810 ret = i40e_aq_set_vsi_unicast_promiscuous(hw,
811 vf->vsi->seid, unicast, NULL);
812 if (ret != I40E_SUCCESS)
815 if (promisc->flags & I40E_FLAG_VF_MULTICAST_PROMISC)
817 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vf->vsi->seid,
821 i40e_pf_host_send_msg_to_vf(vf,
822 I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE, ret, NULL, 0);
828 i40e_pf_host_process_cmd_get_stats(struct i40e_pf_vf *vf)
830 i40e_update_vsi_stats(vf->vsi);
832 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_GET_STATS,
833 I40E_SUCCESS, (uint8_t *)&vf->vsi->eth_stats,
834 sizeof(vf->vsi->eth_stats));
840 i40e_pf_host_process_cmd_get_link_status(struct i40e_pf_vf *vf)
842 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vf->pf->main_vsi);
844 /* Update link status first to acquire latest link change */
845 i40e_dev_link_update(dev, 1);
846 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_GET_LINK_STAT,
847 I40E_SUCCESS, (uint8_t *)&dev->data->dev_link,
848 sizeof(struct rte_eth_link));
852 i40e_pf_host_process_cmd_cfg_vlan_offload(
853 struct i40e_pf_vf *vf,
857 int ret = I40E_SUCCESS;
858 struct i40e_virtchnl_vlan_offload_info *offload =
859 (struct i40e_virtchnl_vlan_offload_info *)msg;
861 if (msg == NULL || msglen != sizeof(*offload)) {
862 ret = I40E_ERR_PARAM;
866 ret = i40e_vsi_config_vlan_stripping(vf->vsi,
867 !!offload->enable_vlan_strip);
869 PMD_DRV_LOG(ERR, "Failed to configure vlan stripping");
872 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD,
879 i40e_pf_host_process_cmd_cfg_pvid(struct i40e_pf_vf *vf,
883 int ret = I40E_SUCCESS;
884 struct i40e_virtchnl_pvid_info *tpid_info =
885 (struct i40e_virtchnl_pvid_info *)msg;
887 if (msg == NULL || msglen != sizeof(*tpid_info)) {
888 ret = I40E_ERR_PARAM;
892 ret = i40e_vsi_vlan_pvid_set(vf->vsi, &tpid_info->info);
895 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_CFG_VLAN_PVID,
902 i40e_pf_host_handle_vf_msg(struct rte_eth_dev *dev,
903 uint16_t abs_vf_id, uint32_t opcode,
904 __rte_unused uint32_t retval,
908 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
909 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
910 struct i40e_pf_vf *vf;
911 /* AdminQ will pass absolute VF id, transfer to internal vf id */
912 uint16_t vf_id = abs_vf_id - hw->func_caps.vf_base_id;
914 if (!dev || vf_id > pf->vf_num - 1 || !pf->vfs) {
915 PMD_DRV_LOG(ERR, "invalid argument");
919 vf = &pf->vfs[vf_id];
921 PMD_DRV_LOG(ERR, "NO VSI associated with VF found");
922 i40e_pf_host_send_msg_to_vf(vf, opcode,
923 I40E_ERR_NO_AVAILABLE_VSI, NULL, 0);
928 case I40E_VIRTCHNL_OP_VERSION :
929 PMD_DRV_LOG(INFO, "OP_VERSION received");
930 i40e_pf_host_process_cmd_version(vf);
932 case I40E_VIRTCHNL_OP_RESET_VF :
933 PMD_DRV_LOG(INFO, "OP_RESET_VF received");
934 i40e_pf_host_process_cmd_reset_vf(vf);
936 case I40E_VIRTCHNL_OP_GET_VF_RESOURCES:
937 PMD_DRV_LOG(INFO, "OP_GET_VF_RESOURCES received");
938 i40e_pf_host_process_cmd_get_vf_resource(vf);
940 case I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES:
941 PMD_DRV_LOG(INFO, "OP_CONFIG_VSI_QUEUES received");
942 i40e_pf_host_process_cmd_config_vsi_queues(vf, msg, msglen);
944 case I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT:
945 PMD_DRV_LOG(INFO, "OP_CONFIG_VSI_QUEUES_EXT received");
946 i40e_pf_host_process_cmd_config_vsi_queues_ext(vf, msg,
949 case I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP:
950 PMD_DRV_LOG(INFO, "OP_CONFIG_IRQ_MAP received");
951 i40e_pf_host_process_cmd_config_irq_map(vf, msg, msglen);
953 case I40E_VIRTCHNL_OP_ENABLE_QUEUES:
954 PMD_DRV_LOG(INFO, "OP_ENABLE_QUEUES received");
955 i40e_pf_host_process_cmd_enable_queues(vf, msg, msglen);
957 case I40E_VIRTCHNL_OP_DISABLE_QUEUES:
958 PMD_DRV_LOG(INFO, "OP_DISABLE_QUEUE received");
959 i40e_pf_host_process_cmd_disable_queues(vf, msg, msglen);
961 case I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS:
962 PMD_DRV_LOG(INFO, "OP_ADD_ETHER_ADDRESS received");
963 i40e_pf_host_process_cmd_add_ether_address(vf, msg, msglen);
965 case I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS:
966 PMD_DRV_LOG(INFO, "OP_DEL_ETHER_ADDRESS received");
967 i40e_pf_host_process_cmd_del_ether_address(vf, msg, msglen);
969 case I40E_VIRTCHNL_OP_ADD_VLAN:
970 PMD_DRV_LOG(INFO, "OP_ADD_VLAN received");
971 i40e_pf_host_process_cmd_add_vlan(vf, msg, msglen);
973 case I40E_VIRTCHNL_OP_DEL_VLAN:
974 PMD_DRV_LOG(INFO, "OP_DEL_VLAN received");
975 i40e_pf_host_process_cmd_del_vlan(vf, msg, msglen);
977 case I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE:
978 PMD_DRV_LOG(INFO, "OP_CONFIG_PROMISCUOUS_MODE received");
979 i40e_pf_host_process_cmd_config_promisc_mode(vf, msg, msglen);
981 case I40E_VIRTCHNL_OP_GET_STATS:
982 PMD_DRV_LOG(INFO, "OP_GET_STATS received");
983 i40e_pf_host_process_cmd_get_stats(vf);
985 case I40E_VIRTCHNL_OP_GET_LINK_STAT:
986 PMD_DRV_LOG(INFO, "OP_GET_LINK_STAT received");
987 i40e_pf_host_process_cmd_get_link_status(vf);
989 case I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD:
990 PMD_DRV_LOG(INFO, "OP_CFG_VLAN_OFFLOAD received");
991 i40e_pf_host_process_cmd_cfg_vlan_offload(vf, msg, msglen);
993 case I40E_VIRTCHNL_OP_CFG_VLAN_PVID:
994 PMD_DRV_LOG(INFO, "OP_CFG_VLAN_PVID received");
995 i40e_pf_host_process_cmd_cfg_pvid(vf, msg, msglen);
997 /* Don't add command supported below, which will
998 * return an error code.
1000 case I40E_VIRTCHNL_OP_FCOE:
1001 PMD_DRV_LOG(ERR, "OP_FCOE received, not supported");
1003 PMD_DRV_LOG(ERR, "%u received, not supported", opcode);
1004 i40e_pf_host_send_msg_to_vf(vf, opcode, I40E_ERR_PARAM,
1011 i40e_pf_host_init(struct rte_eth_dev *dev)
1013 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1014 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1018 PMD_INIT_FUNC_TRACE();
1021 * return if SRIOV not enabled, VF number not configured or
1022 * no queue assigned.
1024 if(!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 || pf->vf_nb_qps == 0)
1025 return I40E_SUCCESS;
1027 /* Allocate memory to store VF structure */
1028 pf->vfs = rte_zmalloc("i40e_pf_vf",sizeof(*pf->vfs) * pf->vf_num, 0);
1032 /* Disable irq0 for VFR event */
1033 i40e_pf_disable_irq0(hw);
1035 /* Disable VF link status interrupt */
1036 val = I40E_READ_REG(hw, I40E_PFGEN_PORTMDIO_NUM);
1037 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
1038 I40E_WRITE_REG(hw, I40E_PFGEN_PORTMDIO_NUM, val);
1039 I40E_WRITE_FLUSH(hw);
1041 for (i = 0; i < pf->vf_num; i++) {
1043 pf->vfs[i].state = I40E_VF_INACTIVE;
1044 pf->vfs[i].vf_idx = i;
1045 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
1046 if (ret != I40E_SUCCESS)
1051 i40e_pf_enable_irq0(hw);
1053 return I40E_SUCCESS;
1057 i40e_pf_enable_irq0(hw);
1063 i40e_pf_host_uninit(struct rte_eth_dev *dev)
1065 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1066 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1069 PMD_INIT_FUNC_TRACE();
1072 * return if SRIOV not enabled, VF number not configured or
1073 * no queue assigned.
1075 if ((!hw->func_caps.sr_iov_1_1) ||
1076 (pf->vf_num == 0) ||
1077 (pf->vf_nb_qps == 0))
1078 return I40E_SUCCESS;
1080 /* free memory to store VF structure */
1084 /* Disable irq0 for VFR event */
1085 i40e_pf_disable_irq0(hw);
1087 /* Disable VF link status interrupt */
1088 val = I40E_READ_REG(hw, I40E_PFGEN_PORTMDIO_NUM);
1089 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
1090 I40E_WRITE_REG(hw, I40E_PFGEN_PORTMDIO_NUM, val);
1091 I40E_WRITE_FLUSH(hw);
1093 return I40E_SUCCESS;