1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #ifndef _I40E_ADMINQ_CMD_H_
35 #define _I40E_ADMINQ_CMD_H_
37 /* This header file defines the i40e Admin Queue commands and is shared between
38 * i40e Firmware and Software.
40 * This file needs to comply with the Linux Kernel coding style.
43 #define I40E_FW_API_VERSION_MAJOR 0x0001
44 #define I40E_FW_API_VERSION_MINOR 0x0005
70 /* Flags sub-structure
71 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
72 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
75 /* command flags and offsets*/
76 #define I40E_AQ_FLAG_DD_SHIFT 0
77 #define I40E_AQ_FLAG_CMP_SHIFT 1
78 #define I40E_AQ_FLAG_ERR_SHIFT 2
79 #define I40E_AQ_FLAG_VFE_SHIFT 3
80 #define I40E_AQ_FLAG_LB_SHIFT 9
81 #define I40E_AQ_FLAG_RD_SHIFT 10
82 #define I40E_AQ_FLAG_VFC_SHIFT 11
83 #define I40E_AQ_FLAG_BUF_SHIFT 12
84 #define I40E_AQ_FLAG_SI_SHIFT 13
85 #define I40E_AQ_FLAG_EI_SHIFT 14
86 #define I40E_AQ_FLAG_FE_SHIFT 15
88 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
89 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
90 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
91 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
92 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
93 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
94 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
95 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
96 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
97 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
98 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
101 enum i40e_admin_queue_err {
102 I40E_AQ_RC_OK = 0, /* success */
103 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
104 I40E_AQ_RC_ENOENT = 2, /* No such element */
105 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
106 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
107 I40E_AQ_RC_EIO = 5, /* I/O error */
108 I40E_AQ_RC_ENXIO = 6, /* No such resource */
109 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
110 I40E_AQ_RC_EAGAIN = 8, /* Try again */
111 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
112 I40E_AQ_RC_EACCES = 10, /* Permission denied */
113 I40E_AQ_RC_EFAULT = 11, /* Bad address */
114 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
115 I40E_AQ_RC_EEXIST = 13, /* object already exists */
116 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
117 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
118 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
119 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
120 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
121 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
122 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
123 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
124 I40E_AQ_RC_EFBIG = 22, /* File too large */
127 /* Admin Queue command opcodes */
128 enum i40e_admin_queue_opc {
130 i40e_aqc_opc_get_version = 0x0001,
131 i40e_aqc_opc_driver_version = 0x0002,
132 i40e_aqc_opc_queue_shutdown = 0x0003,
133 i40e_aqc_opc_set_pf_context = 0x0004,
135 /* resource ownership */
136 i40e_aqc_opc_request_resource = 0x0008,
137 i40e_aqc_opc_release_resource = 0x0009,
139 i40e_aqc_opc_list_func_capabilities = 0x000A,
140 i40e_aqc_opc_list_dev_capabilities = 0x000B,
144 i40e_aqc_opc_set_proxy_config = 0x0104,
145 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105,
149 i40e_aqc_opc_mac_address_read = 0x0107,
150 i40e_aqc_opc_mac_address_write = 0x0108,
153 i40e_aqc_opc_clear_pxe_mode = 0x0110,
157 i40e_aqc_opc_set_wol_filter = 0x0120,
158 i40e_aqc_opc_get_wake_reason = 0x0121,
161 /* internal switch commands */
162 i40e_aqc_opc_get_switch_config = 0x0200,
163 i40e_aqc_opc_add_statistics = 0x0201,
164 i40e_aqc_opc_remove_statistics = 0x0202,
165 i40e_aqc_opc_set_port_parameters = 0x0203,
166 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
167 i40e_aqc_opc_set_switch_config = 0x0205,
168 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
169 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
171 i40e_aqc_opc_add_vsi = 0x0210,
172 i40e_aqc_opc_update_vsi_parameters = 0x0211,
173 i40e_aqc_opc_get_vsi_parameters = 0x0212,
175 i40e_aqc_opc_add_pv = 0x0220,
176 i40e_aqc_opc_update_pv_parameters = 0x0221,
177 i40e_aqc_opc_get_pv_parameters = 0x0222,
179 i40e_aqc_opc_add_veb = 0x0230,
180 i40e_aqc_opc_update_veb_parameters = 0x0231,
181 i40e_aqc_opc_get_veb_parameters = 0x0232,
183 i40e_aqc_opc_delete_element = 0x0243,
185 i40e_aqc_opc_add_macvlan = 0x0250,
186 i40e_aqc_opc_remove_macvlan = 0x0251,
187 i40e_aqc_opc_add_vlan = 0x0252,
188 i40e_aqc_opc_remove_vlan = 0x0253,
189 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
190 i40e_aqc_opc_add_tag = 0x0255,
191 i40e_aqc_opc_remove_tag = 0x0256,
192 i40e_aqc_opc_add_multicast_etag = 0x0257,
193 i40e_aqc_opc_remove_multicast_etag = 0x0258,
194 i40e_aqc_opc_update_tag = 0x0259,
195 i40e_aqc_opc_add_control_packet_filter = 0x025A,
196 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
197 i40e_aqc_opc_add_cloud_filters = 0x025C,
198 i40e_aqc_opc_remove_cloud_filters = 0x025D,
200 i40e_aqc_opc_add_mirror_rule = 0x0260,
201 i40e_aqc_opc_delete_mirror_rule = 0x0261,
204 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
205 i40e_aqc_opc_dcb_updated = 0x0302,
208 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
209 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
210 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
211 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
212 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
213 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
215 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
216 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
217 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
218 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
219 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
220 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
221 i40e_aqc_opc_query_port_ets_config = 0x0419,
222 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
223 i40e_aqc_opc_suspend_port_tx = 0x041B,
224 i40e_aqc_opc_resume_port_tx = 0x041C,
225 i40e_aqc_opc_configure_partition_bw = 0x041D,
228 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
229 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
232 i40e_aqc_opc_get_phy_abilities = 0x0600,
233 i40e_aqc_opc_set_phy_config = 0x0601,
234 i40e_aqc_opc_set_mac_config = 0x0603,
235 i40e_aqc_opc_set_link_restart_an = 0x0605,
236 i40e_aqc_opc_get_link_status = 0x0607,
237 i40e_aqc_opc_set_phy_int_mask = 0x0613,
238 i40e_aqc_opc_get_local_advt_reg = 0x0614,
239 i40e_aqc_opc_set_local_advt_reg = 0x0615,
240 i40e_aqc_opc_get_partner_advt = 0x0616,
241 i40e_aqc_opc_set_lb_modes = 0x0618,
242 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
243 i40e_aqc_opc_set_phy_debug = 0x0622,
244 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
245 i40e_aqc_opc_run_phy_activity = 0x0626,
248 i40e_aqc_opc_nvm_read = 0x0701,
249 i40e_aqc_opc_nvm_erase = 0x0702,
250 i40e_aqc_opc_nvm_update = 0x0703,
251 i40e_aqc_opc_nvm_config_read = 0x0704,
252 i40e_aqc_opc_nvm_config_write = 0x0705,
253 i40e_aqc_opc_oem_post_update = 0x0720,
254 i40e_aqc_opc_thermal_sensor = 0x0721,
256 /* virtualization commands */
257 i40e_aqc_opc_send_msg_to_pf = 0x0801,
258 i40e_aqc_opc_send_msg_to_vf = 0x0802,
259 i40e_aqc_opc_send_msg_to_peer = 0x0803,
261 /* alternate structure */
262 i40e_aqc_opc_alternate_write = 0x0900,
263 i40e_aqc_opc_alternate_write_indirect = 0x0901,
264 i40e_aqc_opc_alternate_read = 0x0902,
265 i40e_aqc_opc_alternate_read_indirect = 0x0903,
266 i40e_aqc_opc_alternate_write_done = 0x0904,
267 i40e_aqc_opc_alternate_set_mode = 0x0905,
268 i40e_aqc_opc_alternate_clear_port = 0x0906,
271 i40e_aqc_opc_lldp_get_mib = 0x0A00,
272 i40e_aqc_opc_lldp_update_mib = 0x0A01,
273 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
274 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
275 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
276 i40e_aqc_opc_lldp_stop = 0x0A05,
277 i40e_aqc_opc_lldp_start = 0x0A06,
278 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
279 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
280 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
282 /* Tunnel commands */
283 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
284 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
286 i40e_aqc_opc_set_rss_key = 0x0B02,
287 i40e_aqc_opc_set_rss_lut = 0x0B03,
288 i40e_aqc_opc_get_rss_key = 0x0B04,
289 i40e_aqc_opc_get_rss_lut = 0x0B05,
293 i40e_aqc_opc_event_lan_overflow = 0x1001,
296 i40e_aqc_opc_oem_parameter_change = 0xFE00,
297 i40e_aqc_opc_oem_device_status_change = 0xFE01,
298 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
299 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
302 i40e_aqc_opc_debug_read_reg = 0xFF03,
303 i40e_aqc_opc_debug_write_reg = 0xFF04,
304 i40e_aqc_opc_debug_modify_reg = 0xFF07,
305 i40e_aqc_opc_debug_dump_internals = 0xFF08,
308 /* command structures and indirect data structures */
310 /* Structure naming conventions:
311 * - no suffix for direct command descriptor structures
312 * - _data for indirect sent data
313 * - _resp for indirect return data (data which is both will use _data)
314 * - _completion for direct return data
315 * - _element_ for repeated elements (may also be _data or _resp)
317 * Command structures are expected to overlay the params.raw member of the basic
318 * descriptor, and as such cannot exceed 16 bytes in length.
321 /* This macro is used to generate a compilation error if a structure
322 * is not exactly the correct length. It gives a divide by zero error if the
323 * structure is not of the correct size, otherwise it creates an enum that is
326 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
327 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
329 /* This macro is used extensively to ensure that command structures are 16
330 * bytes in length as they have to map to the raw array of that size.
332 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
334 /* internal (0x00XX) commands */
336 /* Get version (direct 0x0001) */
337 struct i40e_aqc_get_version {
346 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
348 /* Send driver version (indirect 0x0002) */
349 struct i40e_aqc_driver_version {
353 u8 driver_subbuild_ver;
359 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
361 /* Queue Shutdown (direct 0x0003) */
362 struct i40e_aqc_queue_shutdown {
363 __le32 driver_unloading;
364 #define I40E_AQ_DRIVER_UNLOADING 0x1
368 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
370 /* Set PF context (0x0004, direct) */
371 struct i40e_aqc_set_pf_context {
376 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
378 /* Request resource ownership (direct 0x0008)
379 * Release resource ownership (direct 0x0009)
381 #define I40E_AQ_RESOURCE_NVM 1
382 #define I40E_AQ_RESOURCE_SDP 2
383 #define I40E_AQ_RESOURCE_ACCESS_READ 1
384 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
385 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
386 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
388 struct i40e_aqc_request_resource {
392 __le32 resource_number;
396 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
398 /* Get function capabilities (indirect 0x000A)
399 * Get device capabilities (indirect 0x000B)
401 struct i40e_aqc_list_capabilites {
403 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
411 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
413 struct i40e_aqc_list_capabilities_element_resp {
425 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
426 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
427 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
428 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
429 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
430 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
431 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
432 #define I40E_AQ_CAP_ID_SRIOV 0x0012
433 #define I40E_AQ_CAP_ID_VF 0x0013
434 #define I40E_AQ_CAP_ID_VMDQ 0x0014
435 #define I40E_AQ_CAP_ID_8021QBG 0x0015
436 #define I40E_AQ_CAP_ID_8021QBR 0x0016
437 #define I40E_AQ_CAP_ID_VSI 0x0017
438 #define I40E_AQ_CAP_ID_DCB 0x0018
439 #define I40E_AQ_CAP_ID_FCOE 0x0021
440 #define I40E_AQ_CAP_ID_ISCSI 0x0022
441 #define I40E_AQ_CAP_ID_RSS 0x0040
442 #define I40E_AQ_CAP_ID_RXQ 0x0041
443 #define I40E_AQ_CAP_ID_TXQ 0x0042
444 #define I40E_AQ_CAP_ID_MSIX 0x0043
445 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
446 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
447 #define I40E_AQ_CAP_ID_1588 0x0046
448 #define I40E_AQ_CAP_ID_IWARP 0x0051
449 #define I40E_AQ_CAP_ID_LED 0x0061
450 #define I40E_AQ_CAP_ID_SDP 0x0062
451 #define I40E_AQ_CAP_ID_MDIO 0x0063
452 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
453 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
454 #define I40E_AQ_CAP_ID_CEM 0x00F2
456 /* Set CPPM Configuration (direct 0x0103) */
457 struct i40e_aqc_cppm_configuration {
458 __le16 command_flags;
459 #define I40E_AQ_CPPM_EN_LTRC 0x0800
460 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
461 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
462 #define I40E_AQ_CPPM_EN_HPTC 0x4000
463 #define I40E_AQ_CPPM_EN_DMARC 0x8000
472 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
474 /* Set ARP Proxy command / response (indirect 0x0104) */
475 struct i40e_aqc_arp_proxy_data {
476 __le16 command_flags;
477 #define I40E_AQ_ARP_INIT_IPV4 0x0008
478 #define I40E_AQ_ARP_UNSUP_CTL 0x0010
479 #define I40E_AQ_ARP_ENA 0x0020
480 #define I40E_AQ_ARP_ADD_IPV4 0x0040
481 #define I40E_AQ_ARP_DEL_IPV4 0x0080
489 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
491 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
492 struct i40e_aqc_ns_proxy_data {
493 __le16 table_idx_mac_addr_0;
494 __le16 table_idx_mac_addr_1;
495 __le16 table_idx_ipv6_0;
496 __le16 table_idx_ipv6_1;
498 #define I40E_AQ_NS_PROXY_ADD_0 0x0100
499 #define I40E_AQ_NS_PROXY_DEL_0 0x0200
500 #define I40E_AQ_NS_PROXY_ADD_1 0x0400
501 #define I40E_AQ_NS_PROXY_DEL_1 0x0800
502 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
503 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
504 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
505 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
506 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
507 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
508 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
511 u8 local_mac_addr[6];
512 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
516 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
518 /* Manage LAA Command (0x0106) - obsolete */
519 struct i40e_aqc_mng_laa {
520 __le16 command_flags;
521 #define I40E_AQ_LAA_FLAG_WR 0x8000
528 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
530 /* Manage MAC Address Read Command (indirect 0x0107) */
531 struct i40e_aqc_mac_address_read {
532 __le16 command_flags;
533 #define I40E_AQC_LAN_ADDR_VALID 0x10
534 #define I40E_AQC_SAN_ADDR_VALID 0x20
535 #define I40E_AQC_PORT_ADDR_VALID 0x40
536 #define I40E_AQC_WOL_ADDR_VALID 0x80
537 #define I40E_AQC_MC_MAG_EN_VALID 0x100
538 #define I40E_AQC_ADDR_VALID_MASK 0x1F0
544 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
546 struct i40e_aqc_mac_address_read_data {
553 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
555 /* Manage MAC Address Write Command (0x0108) */
556 struct i40e_aqc_mac_address_write {
557 __le16 command_flags;
558 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
559 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
560 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
561 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
562 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
569 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
571 /* PXE commands (0x011x) */
573 /* Clear PXE Command and response (direct 0x0110) */
574 struct i40e_aqc_clear_pxe {
579 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
582 /* Set WoL Filter (0x0120) */
584 struct i40e_aqc_set_wol_filter {
586 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8
588 #define I40E_AQC_SET_WOL_FILTER 0x8000
589 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
591 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
592 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
598 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
600 /* Get Wake Reason (0x0121) */
602 struct i40e_aqc_get_wake_reason_completion {
608 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
610 struct i40e_aqc_set_wol_filter_data {
615 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
617 #endif /* X722_SUPPORT */
618 /* Switch configuration commands (0x02xx) */
620 /* Used by many indirect commands that only pass an seid and a buffer in the
623 struct i40e_aqc_switch_seid {
630 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
632 /* Get Switch Configuration command (indirect 0x0200)
633 * uses i40e_aqc_switch_seid for the descriptor
635 struct i40e_aqc_get_switch_config_header_resp {
641 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
643 struct i40e_aqc_switch_config_element_resp {
645 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
646 #define I40E_AQ_SW_ELEM_TYPE_PF 2
647 #define I40E_AQ_SW_ELEM_TYPE_VF 3
648 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
649 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
650 #define I40E_AQ_SW_ELEM_TYPE_PV 16
651 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
652 #define I40E_AQ_SW_ELEM_TYPE_PA 18
653 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
655 #define I40E_AQ_SW_ELEM_REV_1 1
658 __le16 downlink_seid;
661 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
662 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
663 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
668 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
670 /* Get Switch Configuration (indirect 0x0200)
671 * an array of elements are returned in the response buffer
672 * the first in the array is the header, remainder are elements
674 struct i40e_aqc_get_switch_config_resp {
675 struct i40e_aqc_get_switch_config_header_resp header;
676 struct i40e_aqc_switch_config_element_resp element[1];
679 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
681 /* Add Statistics (direct 0x0201)
682 * Remove Statistics (direct 0x0202)
684 struct i40e_aqc_add_remove_statistics {
691 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
693 /* Set Port Parameters command (direct 0x0203) */
694 struct i40e_aqc_set_port_parameters {
695 __le16 command_flags;
696 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
697 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
698 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
699 __le16 bad_frame_vsi;
700 __le16 default_seid; /* reserved for command */
704 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
706 /* Get Switch Resource Allocation (indirect 0x0204) */
707 struct i40e_aqc_get_switch_resource_alloc {
708 u8 num_entries; /* reserved for command */
714 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
716 /* expect an array of these structs in the response buffer */
717 struct i40e_aqc_switch_resource_alloc_element_resp {
719 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
720 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
721 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
722 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
723 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
724 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
725 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
726 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
727 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
728 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
729 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
730 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
731 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
732 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
733 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
734 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
735 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
736 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
737 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
742 __le16 total_unalloced;
746 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
748 /* Set Switch Configuration (direct 0x0205) */
749 struct i40e_aqc_set_switch_config {
751 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
752 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
757 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
759 /* Read Receive control registers (direct 0x0206)
760 * Write Receive control registers (direct 0x0207)
761 * used for accessing Rx control registers that can be
762 * slow and need special handling when under high Rx load
764 struct i40e_aqc_rx_ctl_reg_read_write {
771 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
773 /* Add VSI (indirect 0x0210)
774 * this indirect command uses struct i40e_aqc_vsi_properties_data
775 * as the indirect buffer (128 bytes)
777 * Update VSI (indirect 0x211)
778 * uses the same data structure as Add VSI
780 * Get VSI (indirect 0x0212)
781 * uses the same completion and data structure as Add VSI
783 struct i40e_aqc_add_get_update_vsi {
786 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
787 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
788 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
793 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
794 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
795 #define I40E_AQ_VSI_TYPE_VF 0x0
796 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
797 #define I40E_AQ_VSI_TYPE_PF 0x2
798 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
799 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
804 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
806 struct i40e_aqc_add_get_update_vsi_completion {
815 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
817 struct i40e_aqc_vsi_properties_data {
818 /* first 96 byte are written by SW */
819 __le16 valid_sections;
820 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
821 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
822 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
823 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
824 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
825 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
826 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
827 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
828 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
829 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
831 __le16 switch_id; /* 12bit id combined with flags below */
832 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
833 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
834 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
835 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
836 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
838 /* security section */
840 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
841 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
842 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
845 __le16 pvid; /* VLANS include priority bits */
848 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
849 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
850 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
851 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
852 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
853 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
854 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
855 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
856 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
857 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
858 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
859 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
860 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
861 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
862 u8 pvlan_reserved[3];
863 /* ingress egress up sections */
864 __le32 ingress_table; /* bitmap, 3 bits per up */
865 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
866 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
867 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
868 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
869 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
870 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
871 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
872 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
873 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
874 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
875 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
876 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
877 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
878 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
879 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
880 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
881 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
882 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
883 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
884 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
885 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
886 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
887 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
888 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
889 __le32 egress_table; /* same defines as for ingress table */
890 /* cascaded PV section */
893 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
894 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
895 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
896 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
897 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
898 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
899 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
900 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
901 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
903 /* queue mapping section */
904 __le16 mapping_flags;
905 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
906 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
907 __le16 queue_mapping[16];
908 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
909 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
910 __le16 tc_mapping[8];
911 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
912 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
913 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
914 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
915 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
916 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
917 /* queueing option section */
918 u8 queueing_opt_flags;
920 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
921 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
923 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
924 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
926 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
927 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
929 u8 queueing_opt_reserved[3];
930 /* scheduler section */
933 /* outer up section */
934 __le32 outer_up_table; /* same structure and defines as ingress table */
936 /* last 32 bytes are written by FW */
938 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
939 __le16 stat_counter_idx;
941 u8 resp_reserved[12];
944 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
946 /* Add Port Virtualizer (direct 0x0220)
947 * also used for update PV (direct 0x0221) but only flags are used
948 * (IS_CTRL_PORT only works on add PV)
950 struct i40e_aqc_add_update_pv {
951 __le16 command_flags;
952 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
953 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
954 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
955 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
957 __le16 connected_seid;
961 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
963 struct i40e_aqc_add_update_pv_completion {
964 /* reserved for update; for add also encodes error if rc == ENOSPC */
966 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
967 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
968 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
969 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
973 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
975 /* Get PV Params (direct 0x0222)
976 * uses i40e_aqc_switch_seid for the descriptor
979 struct i40e_aqc_get_pv_params_completion {
982 __le16 pv_flags; /* same flags as add_pv */
983 #define I40E_AQC_GET_PV_PV_TYPE 0x1
984 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
985 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
987 __le16 default_port_seid;
990 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
992 /* Add VEB (direct 0x0230) */
993 struct i40e_aqc_add_veb {
995 __le16 downlink_seid;
997 #define I40E_AQC_ADD_VEB_FLOATING 0x1
998 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
999 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
1000 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
1001 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
1002 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
1003 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
1004 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
1009 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
1011 struct i40e_aqc_add_veb_completion {
1014 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1016 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
1017 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
1018 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
1019 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
1020 __le16 statistic_index;
1025 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
1027 /* Get VEB Parameters (direct 0x0232)
1028 * uses i40e_aqc_switch_seid for the descriptor
1030 struct i40e_aqc_get_veb_parameters_completion {
1033 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
1034 __le16 statistic_index;
1040 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
1042 /* Delete Element (direct 0x0243)
1043 * uses the generic i40e_aqc_switch_seid
1046 /* Add MAC-VLAN (indirect 0x0250) */
1048 /* used for the command for most vlan commands */
1049 struct i40e_aqc_macvlan {
1050 __le16 num_addresses;
1052 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
1053 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
1054 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1055 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
1060 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
1062 /* indirect data for command and response */
1063 struct i40e_aqc_add_macvlan_element_data {
1067 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1068 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1069 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1070 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1071 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
1072 __le16 queue_number;
1073 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1074 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1075 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1076 /* response section */
1078 #define I40E_AQC_MM_PERFECT_MATCH 0x01
1079 #define I40E_AQC_MM_HASH_MATCH 0x02
1080 #define I40E_AQC_MM_ERR_NO_RES 0xFF
1084 struct i40e_aqc_add_remove_macvlan_completion {
1085 __le16 perfect_mac_used;
1086 __le16 perfect_mac_free;
1087 __le16 unicast_hash_free;
1088 __le16 multicast_hash_free;
1093 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1095 /* Remove MAC-VLAN (indirect 0x0251)
1096 * uses i40e_aqc_macvlan for the descriptor
1097 * data points to an array of num_addresses of elements
1100 struct i40e_aqc_remove_macvlan_element_data {
1104 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1105 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1106 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1107 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1111 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1112 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1113 u8 reply_reserved[3];
1116 /* Add VLAN (indirect 0x0252)
1117 * Remove VLAN (indirect 0x0253)
1118 * use the generic i40e_aqc_macvlan for the command
1120 struct i40e_aqc_add_remove_vlan_element_data {
1123 /* flags for add VLAN */
1124 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1125 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1126 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1127 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1128 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1129 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1130 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1131 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1132 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1133 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1134 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1135 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1136 /* flags for remove VLAN */
1137 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1140 /* flags for add VLAN */
1141 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1142 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1143 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1144 /* flags for remove VLAN */
1145 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1146 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1150 struct i40e_aqc_add_remove_vlan_completion {
1158 /* Set VSI Promiscuous Modes (direct 0x0254) */
1159 struct i40e_aqc_set_vsi_promiscuous_modes {
1160 __le16 promiscuous_flags;
1162 /* flags used for both fields above */
1163 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1164 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1165 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1166 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1167 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1168 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
1170 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1172 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1173 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1177 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1179 /* Add S/E-tag command (direct 0x0255)
1180 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1182 struct i40e_aqc_add_tag {
1184 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1186 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1187 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1188 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1190 __le16 queue_number;
1194 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1196 struct i40e_aqc_add_remove_tag_completion {
1202 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1204 /* Remove S/E-tag command (direct 0x0256)
1205 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1207 struct i40e_aqc_remove_tag {
1209 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1210 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1211 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1216 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1218 /* Add multicast E-Tag (direct 0x0257)
1219 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1220 * and no external data
1222 struct i40e_aqc_add_remove_mcast_etag {
1225 u8 num_unicast_etags;
1227 __le32 addr_high; /* address of array of 2-byte s-tags */
1231 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1233 struct i40e_aqc_add_remove_mcast_etag_completion {
1235 __le16 mcast_etags_used;
1236 __le16 mcast_etags_free;
1242 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1244 /* Update S/E-Tag (direct 0x0259) */
1245 struct i40e_aqc_update_tag {
1247 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1248 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1249 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1255 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1257 struct i40e_aqc_update_tag_completion {
1263 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1265 /* Add Control Packet filter (direct 0x025A)
1266 * Remove Control Packet filter (direct 0x025B)
1267 * uses the i40e_aqc_add_oveb_cloud,
1268 * and the generic direct completion structure
1270 struct i40e_aqc_add_remove_control_packet_filter {
1274 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1275 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1276 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1277 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1278 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1280 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1281 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1282 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1287 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1289 struct i40e_aqc_add_remove_control_packet_filter_completion {
1290 __le16 mac_etype_used;
1292 __le16 mac_etype_free;
1297 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1299 /* Add Cloud filters (indirect 0x025C)
1300 * Remove Cloud filters (indirect 0x025D)
1301 * uses the i40e_aqc_add_remove_cloud_filters,
1302 * and the generic indirect completion structure
1304 struct i40e_aqc_add_remove_cloud_filters {
1308 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1309 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1310 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1316 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1318 struct i40e_aqc_add_remove_cloud_filters_element_data {
1332 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1333 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1334 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1335 /* 0x0000 reserved */
1336 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1337 /* 0x0002 reserved */
1338 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1339 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1340 /* 0x0005 reserved */
1341 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1342 /* 0x0007 reserved */
1343 /* 0x0008 reserved */
1344 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1345 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1346 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1347 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1349 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1350 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1351 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1352 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1353 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1355 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1356 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1357 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1358 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1359 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1360 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1361 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1362 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
1364 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1365 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1366 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1370 __le16 queue_number;
1371 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1372 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1373 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1375 /* response section */
1376 u8 allocation_result;
1377 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1378 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1379 u8 response_reserved[7];
1382 struct i40e_aqc_remove_cloud_filters_completion {
1383 __le16 perfect_ovlan_used;
1384 __le16 perfect_ovlan_free;
1391 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1393 /* Add Mirror Rule (indirect or direct 0x0260)
1394 * Delete Mirror Rule (indirect or direct 0x0261)
1395 * note: some rule types (4,5) do not use an external buffer.
1396 * take care to set the flags correctly.
1398 struct i40e_aqc_add_delete_mirror_rule {
1401 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1402 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1403 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1404 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1405 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1406 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1407 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1408 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1410 __le16 destination; /* VSI for add, rule id for delete */
1411 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1415 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1417 struct i40e_aqc_add_delete_mirror_rule_completion {
1419 __le16 rule_id; /* only used on add */
1420 __le16 mirror_rules_used;
1421 __le16 mirror_rules_free;
1426 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1430 /* PFC Ignore (direct 0x0301)
1431 * the command and response use the same descriptor structure
1433 struct i40e_aqc_pfc_ignore {
1435 u8 command_flags; /* unused on response */
1436 #define I40E_AQC_PFC_IGNORE_SET 0x80
1437 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1441 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1443 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1444 * with no parameters
1447 /* TX scheduler 0x04xx */
1449 /* Almost all the indirect commands use
1450 * this generic struct to pass the SEID in param0
1452 struct i40e_aqc_tx_sched_ind {
1459 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1461 /* Several commands respond with a set of queue set handles */
1462 struct i40e_aqc_qs_handles_resp {
1463 __le16 qs_handles[8];
1466 /* Configure VSI BW limits (direct 0x0400) */
1467 struct i40e_aqc_configure_vsi_bw_limit {
1472 u8 max_credit; /* 0-3, limit = 2^max */
1476 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1478 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1479 * responds with i40e_aqc_qs_handles_resp
1481 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1484 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1486 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1487 __le16 tc_bw_max[2];
1491 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1493 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1494 * responds with i40e_aqc_qs_handles_resp
1496 struct i40e_aqc_configure_vsi_tc_bw_data {
1499 u8 tc_bw_credits[8];
1501 __le16 qs_handles[8];
1504 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1506 /* Query vsi bw configuration (indirect 0x0408) */
1507 struct i40e_aqc_query_vsi_bw_config_resp {
1509 u8 tc_suspended_bits;
1511 __le16 qs_handles[8];
1513 __le16 port_bw_limit;
1515 u8 max_bw; /* 0-3, limit = 2^max */
1519 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1521 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1522 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1525 u8 share_credits[8];
1528 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1529 __le16 tc_bw_max[2];
1532 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1534 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1535 struct i40e_aqc_configure_switching_comp_bw_limit {
1540 u8 max_bw; /* 0-3, limit = 2^max */
1544 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1546 /* Enable Physical Port ETS (indirect 0x0413)
1547 * Modify Physical Port ETS (indirect 0x0414)
1548 * Disable Physical Port ETS (indirect 0x0415)
1550 struct i40e_aqc_configure_switching_comp_ets_data {
1554 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1555 u8 tc_strict_priority_flags;
1557 u8 tc_bw_share_credits[8];
1561 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1563 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1564 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1567 __le16 tc_bw_credit[8];
1569 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1570 __le16 tc_bw_max[2];
1574 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1576 /* Configure Switching Component Bandwidth Allocation per Tc
1579 struct i40e_aqc_configure_switching_comp_bw_config_data {
1582 u8 absolute_credits; /* bool */
1583 u8 tc_bw_share_credits[8];
1587 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1589 /* Query Switching Component Configuration (indirect 0x0418) */
1590 struct i40e_aqc_query_switching_comp_ets_config_resp {
1593 __le16 port_bw_limit;
1595 u8 tc_bw_max; /* 0-3, limit = 2^max */
1599 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1601 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1602 struct i40e_aqc_query_port_ets_config_resp {
1606 u8 tc_strict_priority_bits;
1608 u8 tc_bw_share_credits[8];
1609 __le16 tc_bw_limits[8];
1611 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1612 __le16 tc_bw_max[2];
1616 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1618 /* Query Switching Component Bandwidth Allocation per Traffic Type
1621 struct i40e_aqc_query_switching_comp_bw_config_resp {
1624 u8 absolute_credits_enable; /* bool */
1625 u8 tc_bw_share_credits[8];
1626 __le16 tc_bw_limits[8];
1628 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1629 __le16 tc_bw_max[2];
1632 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1634 /* Suspend/resume port TX traffic
1635 * (direct 0x041B and 0x041C) uses the generic SEID struct
1638 /* Configure partition BW
1641 struct i40e_aqc_configure_partition_bw_data {
1642 __le16 pf_valid_bits;
1643 u8 min_bw[16]; /* guaranteed bandwidth */
1644 u8 max_bw[16]; /* bandwidth limit */
1647 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1649 /* Get and set the active HMC resource profile and status.
1650 * (direct 0x0500) and (direct 0x0501)
1652 struct i40e_aq_get_set_hmc_resource_profile {
1658 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1660 enum i40e_aq_hmc_profile {
1661 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1662 I40E_HMC_PROFILE_DEFAULT = 1,
1663 I40E_HMC_PROFILE_FAVOR_VF = 2,
1664 I40E_HMC_PROFILE_EQUAL = 3,
1667 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF
1668 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F
1670 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1672 /* set in param0 for get phy abilities to report qualified modules */
1673 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1674 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1676 enum i40e_aq_phy_type {
1677 I40E_PHY_TYPE_SGMII = 0x0,
1678 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1679 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1680 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1681 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1682 I40E_PHY_TYPE_XAUI = 0x5,
1683 I40E_PHY_TYPE_XFI = 0x6,
1684 I40E_PHY_TYPE_SFI = 0x7,
1685 I40E_PHY_TYPE_XLAUI = 0x8,
1686 I40E_PHY_TYPE_XLPPI = 0x9,
1687 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1688 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1689 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1690 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1691 I40E_PHY_TYPE_100BASE_TX = 0x11,
1692 I40E_PHY_TYPE_1000BASE_T = 0x12,
1693 I40E_PHY_TYPE_10GBASE_T = 0x13,
1694 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1695 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1696 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1697 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1698 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1699 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1700 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1701 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1702 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1703 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1704 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1708 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1709 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1710 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1711 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1712 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1714 enum i40e_aq_link_speed {
1715 I40E_LINK_SPEED_UNKNOWN = 0,
1716 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1717 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1718 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1719 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1720 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT)
1723 struct i40e_aqc_module_desc {
1731 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1733 struct i40e_aq_get_phy_abilities_resp {
1734 __le32 phy_type; /* bitmap using the above enum for offsets */
1735 u8 link_speed; /* bitmap using the above enum bit patterns */
1737 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1738 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1739 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1740 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1741 #define I40E_AQ_PHY_AN_ENABLED 0x10
1742 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1743 __le16 eee_capability;
1744 #define I40E_AQ_EEE_100BASE_TX 0x0002
1745 #define I40E_AQ_EEE_1000BASE_T 0x0004
1746 #define I40E_AQ_EEE_10GBASE_T 0x0008
1747 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1748 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1749 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1752 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1756 u8 qualified_module_count;
1757 #define I40E_AQ_PHY_MAX_QMS 16
1758 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1761 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1763 /* Set PHY Config (direct 0x0601) */
1764 struct i40e_aq_set_phy_config { /* same bits as above in all */
1768 /* bits 0-2 use the values from get_phy_abilities_resp */
1769 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1770 #define I40E_AQ_PHY_ENABLE_AN 0x10
1771 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1772 __le16 eee_capability;
1778 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1780 /* Set MAC Config command data structure (direct 0x0603) */
1781 struct i40e_aq_set_mac_config {
1782 __le16 max_frame_size;
1784 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1785 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1786 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1787 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1788 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1789 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1790 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1791 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1792 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1793 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1794 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1795 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1796 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1797 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1798 u8 tx_timer_priority; /* bitmap */
1799 __le16 tx_timer_value;
1800 __le16 fc_refresh_threshold;
1804 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1806 /* Restart Auto-Negotiation (direct 0x605) */
1807 struct i40e_aqc_set_link_restart_an {
1809 #define I40E_AQ_PHY_RESTART_AN 0x02
1810 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1814 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1816 /* Get Link Status cmd & response data structure (direct 0x0607) */
1817 struct i40e_aqc_get_link_status {
1818 __le16 command_flags; /* only field set on command */
1819 #define I40E_AQ_LSE_MASK 0x3
1820 #define I40E_AQ_LSE_NOP 0x0
1821 #define I40E_AQ_LSE_DISABLE 0x2
1822 #define I40E_AQ_LSE_ENABLE 0x3
1823 /* only response uses this flag */
1824 #define I40E_AQ_LSE_IS_ENABLED 0x1
1825 u8 phy_type; /* i40e_aq_phy_type */
1826 u8 link_speed; /* i40e_aq_link_speed */
1828 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
1829 #define I40E_AQ_LINK_UP_FUNCTION 0x01
1830 #define I40E_AQ_LINK_FAULT 0x02
1831 #define I40E_AQ_LINK_FAULT_TX 0x04
1832 #define I40E_AQ_LINK_FAULT_RX 0x08
1833 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1834 #define I40E_AQ_LINK_UP_PORT 0x20
1835 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1836 #define I40E_AQ_SIGNAL_DETECT 0x80
1838 #define I40E_AQ_AN_COMPLETED 0x01
1839 #define I40E_AQ_LP_AN_ABILITY 0x02
1840 #define I40E_AQ_PD_FAULT 0x04
1841 #define I40E_AQ_FEC_EN 0x08
1842 #define I40E_AQ_PHY_LOW_POWER 0x10
1843 #define I40E_AQ_LINK_PAUSE_TX 0x20
1844 #define I40E_AQ_LINK_PAUSE_RX 0x40
1845 #define I40E_AQ_QUALIFIED_MODULE 0x80
1847 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1848 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1849 #define I40E_AQ_LINK_TX_SHIFT 0x02
1850 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1851 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1852 #define I40E_AQ_LINK_TX_DRAINED 0x01
1853 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1854 #define I40E_AQ_LINK_FORCED_40G 0x10
1855 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1856 __le16 max_frame_size;
1858 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1859 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1860 u8 external_power_ability;
1861 #define I40E_AQ_LINK_POWER_CLASS_1 0x00
1862 #define I40E_AQ_LINK_POWER_CLASS_2 0x01
1863 #define I40E_AQ_LINK_POWER_CLASS_3 0x02
1864 #define I40E_AQ_LINK_POWER_CLASS_4 0x03
1868 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1870 /* Set event mask command (direct 0x613) */
1871 struct i40e_aqc_set_phy_int_mask {
1874 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1875 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1876 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1877 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1878 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1879 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1880 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1881 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1882 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1886 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1888 /* Get Local AN advt register (direct 0x0614)
1889 * Set Local AN advt register (direct 0x0615)
1890 * Get Link Partner AN advt register (direct 0x0616)
1892 struct i40e_aqc_an_advt_reg {
1893 __le32 local_an_reg0;
1894 __le16 local_an_reg1;
1898 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1900 /* Set Loopback mode (0x0618) */
1901 struct i40e_aqc_set_lb_mode {
1903 #define I40E_AQ_LB_PHY_LOCAL 0x01
1904 #define I40E_AQ_LB_PHY_REMOTE 0x02
1905 #define I40E_AQ_LB_MAC_LOCAL 0x04
1909 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1911 /* Set PHY Debug command (0x0622) */
1912 struct i40e_aqc_set_phy_debug {
1914 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1915 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1916 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1917 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1918 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1919 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1920 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1921 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1925 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1927 enum i40e_aq_phy_reg_type {
1928 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1929 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1930 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1933 /* Run PHY Activity (0x0626) */
1934 struct i40e_aqc_run_phy_activity {
1943 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
1945 /* NVM Read command (indirect 0x0701)
1946 * NVM Erase commands (direct 0x0702)
1947 * NVM Update commands (indirect 0x0703)
1949 struct i40e_aqc_nvm_update {
1951 #define I40E_AQ_NVM_LAST_CMD 0x01
1952 #define I40E_AQ_NVM_FLASH_ONLY 0x80
1960 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1962 /* NVM Config Read (indirect 0x0704) */
1963 struct i40e_aqc_nvm_config_read {
1965 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
1966 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
1967 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
1968 __le16 element_count;
1969 __le16 element_id; /* Feature/field ID */
1970 __le16 element_id_msw; /* MSWord of field ID */
1971 __le32 address_high;
1975 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1977 /* NVM Config Write (indirect 0x0705) */
1978 struct i40e_aqc_nvm_config_write {
1980 __le16 element_count;
1982 __le32 address_high;
1986 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1988 /* Used for 0x0704 as well as for 0x0705 commands */
1989 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
1990 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
1991 #define I40E_AQ_ANVM_FEATURE 0
1992 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
1993 struct i40e_aqc_nvm_config_data_feature {
1995 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
1996 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
1997 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
1998 __le16 feature_options;
1999 __le16 feature_selection;
2002 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
2004 struct i40e_aqc_nvm_config_data_immediate_field {
2007 __le16 field_options;
2011 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
2013 /* OEM Post Update (indirect 0x0720)
2014 * no command data struct used
2016 struct i40e_aqc_nvm_oem_post_update {
2017 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
2022 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
2024 struct i40e_aqc_nvm_oem_post_update_buffer {
2031 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
2033 /* Thermal Sensor (indirect 0x0721)
2034 * read or set thermal sensor configs and values
2035 * takes a sensor and command specific data buffer, not detailed here
2037 struct i40e_aqc_thermal_sensor {
2039 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
2040 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
2041 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
2047 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
2049 /* Send to PF command (indirect 0x0801) id is only used by PF
2050 * Send to VF command (indirect 0x0802) id is only used by PF
2051 * Send to Peer PF command (indirect 0x0803)
2053 struct i40e_aqc_pf_vf_message {
2060 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
2062 /* Alternate structure */
2064 /* Direct write (direct 0x0900)
2065 * Direct read (direct 0x0902)
2067 struct i40e_aqc_alternate_write {
2074 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2076 /* Indirect write (indirect 0x0901)
2077 * Indirect read (indirect 0x0903)
2080 struct i40e_aqc_alternate_ind_write {
2087 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2089 /* Done alternate write (direct 0x0904)
2092 struct i40e_aqc_alternate_write_done {
2094 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2095 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2096 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2097 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
2101 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2103 /* Set OEM mode (direct 0x0905) */
2104 struct i40e_aqc_alternate_set_mode {
2106 #define I40E_AQ_ALTERNATE_MODE_NONE 0
2107 #define I40E_AQ_ALTERNATE_MODE_OEM 1
2111 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2113 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2115 /* async events 0x10xx */
2117 /* Lan Queue Overflow Event (direct, 0x1001) */
2118 struct i40e_aqc_lan_overflow {
2119 __le32 prtdcb_rupto;
2124 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2126 /* Get LLDP MIB (indirect 0x0A00) */
2127 struct i40e_aqc_lldp_get_mib {
2130 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2131 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2132 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2133 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2134 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2135 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2136 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2137 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2138 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2139 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2140 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2148 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2150 /* Configure LLDP MIB Change Event (direct 0x0A01)
2151 * also used for the event (with type in the command field)
2153 struct i40e_aqc_lldp_update_mib {
2155 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2156 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2162 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2164 /* Add LLDP TLV (indirect 0x0A02)
2165 * Delete LLDP TLV (indirect 0x0A04)
2167 struct i40e_aqc_lldp_add_tlv {
2168 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2176 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2178 /* Update LLDP TLV (indirect 0x0A03) */
2179 struct i40e_aqc_lldp_update_tlv {
2180 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2189 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2191 /* Stop LLDP (direct 0x0A05) */
2192 struct i40e_aqc_lldp_stop {
2194 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2195 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2199 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2201 /* Start LLDP (direct 0x0A06) */
2203 struct i40e_aqc_lldp_start {
2205 #define I40E_AQ_LLDP_AGENT_START 0x1
2209 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2211 /* Get CEE DCBX Oper Config (0x0A07)
2212 * uses the generic descriptor struct
2213 * returns below as indirect response
2216 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2217 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2218 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2219 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2220 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2221 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2223 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2224 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2225 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2226 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2227 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2228 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2229 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2230 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2231 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2232 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2233 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2234 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2236 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2237 * word boundary layout issues, which the Linux compilers silently deal
2238 * with by adding padding, making the actual struct larger than designed.
2239 * However, the FW compiler for the NIC is less lenient and complains
2240 * about the struct. Hence, the struct defined here has an extra byte in
2241 * fields reserved3 and reserved4 to directly acknowledge that padding,
2242 * and the new length is used in the length check macro.
2244 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2252 __le16 oper_app_prio;
2257 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2259 struct i40e_aqc_get_cee_dcb_cfg_resp {
2264 __le16 oper_app_prio;
2269 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2271 /* Set Local LLDP MIB (indirect 0x0A08)
2272 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2274 struct i40e_aqc_lldp_set_local_mib {
2275 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2276 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2277 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2278 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2279 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2280 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
2281 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2282 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2287 __le32 address_high;
2291 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2293 struct i40e_aqc_lldp_set_local_mib_resp {
2294 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01
2299 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp);
2301 /* Stop/Start LLDP Agent (direct 0x0A09)
2302 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2304 struct i40e_aqc_lldp_stop_start_specific_agent {
2305 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2306 #define I40E_AQC_START_SPECIFIC_AGENT_MASK (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2311 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2313 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2314 struct i40e_aqc_add_udp_tunnel {
2318 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2319 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2320 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2321 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2325 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2327 struct i40e_aqc_add_udp_tunnel_completion {
2329 u8 filter_entry_index;
2331 #define I40E_AQC_SINGLE_PF 0x0
2332 #define I40E_AQC_MULTIPLE_PFS 0x1
2337 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2339 /* remove UDP Tunnel command (0x0B01) */
2340 struct i40e_aqc_remove_udp_tunnel {
2342 u8 index; /* 0 to 15 */
2346 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2348 struct i40e_aqc_del_udp_tunnel_completion {
2350 u8 index; /* 0 to 15 */
2352 u8 total_filters_used;
2356 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2359 struct i40e_aqc_get_set_rss_key {
2360 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2361 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2362 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2363 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2370 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2372 struct i40e_aqc_get_set_rss_key_data {
2373 u8 standard_rss_key[0x28];
2374 u8 extended_hash_key[0xc];
2377 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2379 struct i40e_aqc_get_set_rss_lut {
2380 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2381 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2382 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2383 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2385 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2386 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2387 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2389 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2390 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2397 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2400 /* tunnel key structure 0x0B10 */
2402 struct i40e_aqc_tunnel_key_structure {
2405 u8 key1_len; /* 0 to 15 */
2406 u8 key2_len; /* 0 to 15 */
2408 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2409 /* response flags */
2410 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2411 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2412 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2413 u8 network_key_index;
2414 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2415 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2416 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2417 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2421 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2423 /* OEM mode commands (direct 0xFE0x) */
2424 struct i40e_aqc_oem_param_change {
2426 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2427 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2428 #define I40E_AQ_OEM_PARAM_MAC 2
2429 __le32 param_value1;
2430 __le16 param_value2;
2434 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2436 struct i40e_aqc_oem_state_change {
2438 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2439 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2443 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2445 /* Initialize OCSD (0xFE02, direct) */
2446 struct i40e_aqc_opc_oem_ocsd_initialize {
2449 __le32 ocsd_memory_block_addr_high;
2450 __le32 ocsd_memory_block_addr_low;
2451 __le32 requested_update_interval;
2454 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2456 /* Initialize OCBB (0xFE03, direct) */
2457 struct i40e_aqc_opc_oem_ocbb_initialize {
2460 __le32 ocbb_memory_block_addr_high;
2461 __le32 ocbb_memory_block_addr_low;
2465 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2467 /* debug commands */
2469 /* get device id (0xFF00) uses the generic structure */
2471 /* set test more (0xFF01, internal) */
2473 struct i40e_acq_set_test_mode {
2475 #define I40E_AQ_TEST_PARTIAL 0
2476 #define I40E_AQ_TEST_FULL 1
2477 #define I40E_AQ_TEST_NVM 2
2480 #define I40E_AQ_TEST_OPEN 0
2481 #define I40E_AQ_TEST_CLOSE 1
2482 #define I40E_AQ_TEST_INC 2
2484 __le32 address_high;
2488 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2490 /* Debug Read Register command (0xFF03)
2491 * Debug Write Register command (0xFF04)
2493 struct i40e_aqc_debug_reg_read_write {
2500 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2502 /* Scatter/gather Reg Read (indirect 0xFF05)
2503 * Scatter/gather Reg Write (indirect 0xFF06)
2506 /* i40e_aq_desc is used for the command */
2507 struct i40e_aqc_debug_reg_sg_element_data {
2512 /* Debug Modify register (direct 0xFF07) */
2513 struct i40e_aqc_debug_modify_reg {
2520 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2522 /* dump internal data (0xFF08, indirect) */
2524 #define I40E_AQ_CLUSTER_ID_AUX 0
2525 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2526 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2527 #define I40E_AQ_CLUSTER_ID_HMC 3
2528 #define I40E_AQ_CLUSTER_ID_MAC0 4
2529 #define I40E_AQ_CLUSTER_ID_MAC1 5
2530 #define I40E_AQ_CLUSTER_ID_MAC2 6
2531 #define I40E_AQ_CLUSTER_ID_MAC3 7
2532 #define I40E_AQ_CLUSTER_ID_DCB 8
2533 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2534 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2535 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2537 struct i40e_aqc_debug_dump_internals {
2542 __le32 address_high;
2546 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2548 struct i40e_aqc_debug_modify_internals {
2550 u8 cluster_specific_params[7];
2551 __le32 address_high;
2555 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2557 #endif /* _I40E_ADMINQ_CMD_H_ */