1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
29 #include <rte_bitmap.h>
31 #include "i40e_logs.h"
32 #include "base/i40e_prototype.h"
33 #include "base/i40e_adminq_cmd.h"
34 #include "base/i40e_type.h"
35 #include "base/i40e_register.h"
36 #include "base/i40e_dcb.h"
37 #include "i40e_ethdev.h"
38 #include "i40e_rxtx.h"
40 #include "i40e_regs.h"
41 #include "rte_pmd_i40e.h"
43 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
44 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
45 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
48 #define ETH_I40E_VF_MSG_CFG "vf_msg_cfg"
50 #define I40E_CLEAR_PXE_WAIT_MS 200
51 #define I40E_VSI_TSR_QINQ_STRIP 0x4010
52 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
54 /* Maximun number of capability elements */
55 #define I40E_MAX_CAP_ELE_NUM 128
57 /* Wait count and interval */
58 #define I40E_CHK_Q_ENA_COUNT 1000
59 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
61 /* Maximun number of VSI */
62 #define I40E_MAX_NUM_VSIS (384UL)
64 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
66 /* Flow control default timer */
67 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
69 /* Flow control enable fwd bit */
70 #define I40E_PRTMAC_FWD_CTRL 0x00000001
72 /* Receive Packet Buffer size */
73 #define I40E_RXPBSIZE (968 * 1024)
76 #define I40E_KILOSHIFT 10
78 /* Flow control default high water */
79 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
81 /* Flow control default low water */
82 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
84 /* Receive Average Packet Size in Byte*/
85 #define I40E_PACKET_AVERAGE_SIZE 128
87 /* Mask of PF interrupt causes */
88 #define I40E_PFINT_ICR0_ENA_MASK ( \
89 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
90 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
91 I40E_PFINT_ICR0_ENA_GRST_MASK | \
92 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
93 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
94 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
95 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
96 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
97 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
99 #define I40E_FLOW_TYPES ( \
100 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
105 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
107 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
108 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
109 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
110 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
112 /* Additional timesync values. */
113 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
114 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
115 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
116 #define I40E_PRTTSYN_TSYNENA 0x80000000
117 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
118 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
121 * Below are values for writing un-exposed registers suggested
124 /* Destination MAC address */
125 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
126 /* Source MAC address */
127 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
128 /* Outer (S-Tag) VLAN tag in the outer L2 header */
129 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
130 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
131 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
132 /* Single VLAN tag in the inner L2 header */
133 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
134 /* Source IPv4 address */
135 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
136 /* Destination IPv4 address */
137 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
138 /* Source IPv4 address for X722 */
139 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
140 /* Destination IPv4 address for X722 */
141 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
142 /* IPv4 Protocol for X722 */
143 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
144 /* IPv4 Time to Live for X722 */
145 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
146 /* IPv4 Type of Service (TOS) */
147 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
149 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
150 /* IPv4 Time to Live */
151 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
152 /* Source IPv6 address */
153 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
154 /* Destination IPv6 address */
155 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
156 /* IPv6 Traffic Class (TC) */
157 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
158 /* IPv6 Next Header */
159 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
161 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
163 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
164 /* Destination L4 port */
165 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
166 /* SCTP verification tag */
167 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
168 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
169 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
170 /* Source port of tunneling UDP */
171 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
172 /* Destination port of tunneling UDP */
173 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
174 /* UDP Tunneling ID, NVGRE/GRE key */
175 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
176 /* Last ether type */
177 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
178 /* Tunneling outer destination IPv4 address */
179 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
180 /* Tunneling outer destination IPv6 address */
181 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
182 /* 1st word of flex payload */
183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
184 /* 2nd word of flex payload */
185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
186 /* 3rd word of flex payload */
187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
188 /* 4th word of flex payload */
189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
190 /* 5th word of flex payload */
191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
192 /* 6th word of flex payload */
193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
194 /* 7th word of flex payload */
195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
196 /* 8th word of flex payload */
197 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
198 /* all 8 words flex payload */
199 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
200 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
202 #define I40E_TRANSLATE_INSET 0
203 #define I40E_TRANSLATE_REG 1
205 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
206 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
207 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
208 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
209 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
210 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
212 /* PCI offset for querying capability */
213 #define PCI_DEV_CAP_REG 0xA4
214 /* PCI offset for enabling/disabling Extended Tag */
215 #define PCI_DEV_CTRL_REG 0xA8
216 /* Bit mask of Extended Tag capability */
217 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
218 /* Bit shift of Extended Tag enable/disable */
219 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
220 /* Bit mask of Extended Tag enable/disable */
221 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
223 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
224 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
225 static int i40e_dev_configure(struct rte_eth_dev *dev);
226 static int i40e_dev_start(struct rte_eth_dev *dev);
227 static int i40e_dev_stop(struct rte_eth_dev *dev);
228 static int i40e_dev_close(struct rte_eth_dev *dev);
229 static int i40e_dev_reset(struct rte_eth_dev *dev);
230 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
231 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
232 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
233 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
234 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
235 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
236 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
237 struct rte_eth_stats *stats);
238 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
239 struct rte_eth_xstat *xstats, unsigned n);
240 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
241 struct rte_eth_xstat_name *xstats_names,
243 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
244 static int i40e_fw_version_get(struct rte_eth_dev *dev,
245 char *fw_version, size_t fw_size);
246 static int i40e_dev_info_get(struct rte_eth_dev *dev,
247 struct rte_eth_dev_info *dev_info);
248 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
251 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
252 enum rte_vlan_type vlan_type,
254 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
255 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
258 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
259 static int i40e_dev_led_on(struct rte_eth_dev *dev);
260 static int i40e_dev_led_off(struct rte_eth_dev *dev);
261 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
262 struct rte_eth_fc_conf *fc_conf);
263 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
264 struct rte_eth_fc_conf *fc_conf);
265 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
266 struct rte_eth_pfc_conf *pfc_conf);
267 static int i40e_macaddr_add(struct rte_eth_dev *dev,
268 struct rte_ether_addr *mac_addr,
271 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
272 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
273 struct rte_eth_rss_reta_entry64 *reta_conf,
275 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
276 struct rte_eth_rss_reta_entry64 *reta_conf,
279 static int i40e_get_cap(struct i40e_hw *hw);
280 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
281 static int i40e_pf_setup(struct i40e_pf *pf);
282 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
283 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
284 static int i40e_dcb_setup(struct rte_eth_dev *dev);
285 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
286 bool offset_loaded, uint64_t *offset, uint64_t *stat);
287 static void i40e_stat_update_48(struct i40e_hw *hw,
293 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
294 static void i40e_dev_interrupt_handler(void *param);
295 static void i40e_dev_alarm_handler(void *param);
296 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
297 uint32_t base, uint32_t num);
298 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
299 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
301 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
303 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
304 static int i40e_veb_release(struct i40e_veb *veb);
305 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
306 struct i40e_vsi *vsi);
307 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
308 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
309 struct i40e_macvlan_filter *mv_f,
312 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
313 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
314 struct rte_eth_rss_conf *rss_conf);
315 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
316 struct rte_eth_rss_conf *rss_conf);
317 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
318 struct rte_eth_udp_tunnel *udp_tunnel);
319 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
320 struct rte_eth_udp_tunnel *udp_tunnel);
321 static void i40e_filter_input_set_init(struct i40e_pf *pf);
322 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
323 enum rte_filter_op filter_op,
325 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
326 enum rte_filter_type filter_type,
327 enum rte_filter_op filter_op,
329 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
330 struct rte_eth_dcb_info *dcb_info);
331 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
332 static void i40e_configure_registers(struct i40e_hw *hw);
333 static void i40e_hw_init(struct rte_eth_dev *dev);
334 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
335 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
341 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
342 struct rte_eth_mirror_conf *mirror_conf,
343 uint8_t sw_id, uint8_t on);
344 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
346 static int i40e_timesync_enable(struct rte_eth_dev *dev);
347 static int i40e_timesync_disable(struct rte_eth_dev *dev);
348 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
349 struct timespec *timestamp,
351 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
352 struct timespec *timestamp);
353 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
355 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
357 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
358 struct timespec *timestamp);
359 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
360 const struct timespec *timestamp);
362 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
364 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
367 static int i40e_get_regs(struct rte_eth_dev *dev,
368 struct rte_dev_reg_info *regs);
370 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
372 static int i40e_get_eeprom(struct rte_eth_dev *dev,
373 struct rte_dev_eeprom_info *eeprom);
375 static int i40e_get_module_info(struct rte_eth_dev *dev,
376 struct rte_eth_dev_module_info *modinfo);
377 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
378 struct rte_dev_eeprom_info *info);
380 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
381 struct rte_ether_addr *mac_addr);
383 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
385 static int i40e_ethertype_filter_convert(
386 const struct rte_eth_ethertype_filter *input,
387 struct i40e_ethertype_filter *filter);
388 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
389 struct i40e_ethertype_filter *filter);
391 static int i40e_tunnel_filter_convert(
392 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
393 struct i40e_tunnel_filter *tunnel_filter);
394 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
395 struct i40e_tunnel_filter *tunnel_filter);
396 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
398 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
399 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
400 static void i40e_filter_restore(struct i40e_pf *pf);
401 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
402 static int i40e_pf_config_rss(struct i40e_pf *pf);
404 static const char *const valid_keys[] = {
405 ETH_I40E_FLOATING_VEB_ARG,
406 ETH_I40E_FLOATING_VEB_LIST_ARG,
407 ETH_I40E_SUPPORT_MULTI_DRIVER,
408 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
409 ETH_I40E_USE_LATEST_VEC,
413 static const struct rte_pci_id pci_id_i40e_map[] = {
414 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
415 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
440 { .vendor_id = 0, /* sentinel */ },
443 static const struct eth_dev_ops i40e_eth_dev_ops = {
444 .dev_configure = i40e_dev_configure,
445 .dev_start = i40e_dev_start,
446 .dev_stop = i40e_dev_stop,
447 .dev_close = i40e_dev_close,
448 .dev_reset = i40e_dev_reset,
449 .promiscuous_enable = i40e_dev_promiscuous_enable,
450 .promiscuous_disable = i40e_dev_promiscuous_disable,
451 .allmulticast_enable = i40e_dev_allmulticast_enable,
452 .allmulticast_disable = i40e_dev_allmulticast_disable,
453 .dev_set_link_up = i40e_dev_set_link_up,
454 .dev_set_link_down = i40e_dev_set_link_down,
455 .link_update = i40e_dev_link_update,
456 .stats_get = i40e_dev_stats_get,
457 .xstats_get = i40e_dev_xstats_get,
458 .xstats_get_names = i40e_dev_xstats_get_names,
459 .stats_reset = i40e_dev_stats_reset,
460 .xstats_reset = i40e_dev_stats_reset,
461 .fw_version_get = i40e_fw_version_get,
462 .dev_infos_get = i40e_dev_info_get,
463 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
464 .vlan_filter_set = i40e_vlan_filter_set,
465 .vlan_tpid_set = i40e_vlan_tpid_set,
466 .vlan_offload_set = i40e_vlan_offload_set,
467 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
468 .vlan_pvid_set = i40e_vlan_pvid_set,
469 .rx_queue_start = i40e_dev_rx_queue_start,
470 .rx_queue_stop = i40e_dev_rx_queue_stop,
471 .tx_queue_start = i40e_dev_tx_queue_start,
472 .tx_queue_stop = i40e_dev_tx_queue_stop,
473 .rx_queue_setup = i40e_dev_rx_queue_setup,
474 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
475 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
476 .rx_queue_release = i40e_dev_rx_queue_release,
477 .tx_queue_setup = i40e_dev_tx_queue_setup,
478 .tx_queue_release = i40e_dev_tx_queue_release,
479 .dev_led_on = i40e_dev_led_on,
480 .dev_led_off = i40e_dev_led_off,
481 .flow_ctrl_get = i40e_flow_ctrl_get,
482 .flow_ctrl_set = i40e_flow_ctrl_set,
483 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
484 .mac_addr_add = i40e_macaddr_add,
485 .mac_addr_remove = i40e_macaddr_remove,
486 .reta_update = i40e_dev_rss_reta_update,
487 .reta_query = i40e_dev_rss_reta_query,
488 .rss_hash_update = i40e_dev_rss_hash_update,
489 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
490 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
491 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
492 .filter_ctrl = i40e_dev_filter_ctrl,
493 .rxq_info_get = i40e_rxq_info_get,
494 .txq_info_get = i40e_txq_info_get,
495 .rx_burst_mode_get = i40e_rx_burst_mode_get,
496 .tx_burst_mode_get = i40e_tx_burst_mode_get,
497 .mirror_rule_set = i40e_mirror_rule_set,
498 .mirror_rule_reset = i40e_mirror_rule_reset,
499 .timesync_enable = i40e_timesync_enable,
500 .timesync_disable = i40e_timesync_disable,
501 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
502 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
503 .get_dcb_info = i40e_dev_get_dcb_info,
504 .timesync_adjust_time = i40e_timesync_adjust_time,
505 .timesync_read_time = i40e_timesync_read_time,
506 .timesync_write_time = i40e_timesync_write_time,
507 .get_reg = i40e_get_regs,
508 .get_eeprom_length = i40e_get_eeprom_length,
509 .get_eeprom = i40e_get_eeprom,
510 .get_module_info = i40e_get_module_info,
511 .get_module_eeprom = i40e_get_module_eeprom,
512 .mac_addr_set = i40e_set_default_mac_addr,
513 .mtu_set = i40e_dev_mtu_set,
514 .tm_ops_get = i40e_tm_ops_get,
515 .tx_done_cleanup = i40e_tx_done_cleanup,
518 /* store statistics names and its offset in stats structure */
519 struct rte_i40e_xstats_name_off {
520 char name[RTE_ETH_XSTATS_NAME_SIZE];
524 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
525 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
526 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
527 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
528 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
529 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
530 rx_unknown_protocol)},
531 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
532 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
533 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
534 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
537 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
538 sizeof(rte_i40e_stats_strings[0]))
540 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
541 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
542 tx_dropped_link_down)},
543 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
544 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
546 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
547 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
549 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
551 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
553 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
554 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
555 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
556 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
557 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
558 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
560 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
562 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
564 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
566 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
568 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
570 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
572 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
574 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
575 mac_short_packet_dropped)},
576 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
578 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
579 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
580 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
582 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
584 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
586 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
588 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
590 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
592 {"rx_flow_director_atr_match_packets",
593 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
594 {"rx_flow_director_sb_match_packets",
595 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
596 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
598 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
600 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
602 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
606 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
607 sizeof(rte_i40e_hw_port_strings[0]))
609 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
610 {"xon_packets", offsetof(struct i40e_hw_port_stats,
612 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
616 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
617 sizeof(rte_i40e_rxq_prio_strings[0]))
619 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
620 {"xon_packets", offsetof(struct i40e_hw_port_stats,
622 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
624 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
625 priority_xon_2_xoff)},
628 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
629 sizeof(rte_i40e_txq_prio_strings[0]))
632 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
633 struct rte_pci_device *pci_dev)
635 char name[RTE_ETH_NAME_MAX_LEN];
636 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
639 if (pci_dev->device.devargs) {
640 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
646 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
647 sizeof(struct i40e_adapter),
648 eth_dev_pci_specific_init, pci_dev,
649 eth_i40e_dev_init, NULL);
651 if (retval || eth_da.nb_representor_ports < 1)
654 /* probe VF representor ports */
655 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
656 pci_dev->device.name);
658 if (pf_ethdev == NULL)
661 for (i = 0; i < eth_da.nb_representor_ports; i++) {
662 struct i40e_vf_representor representor = {
663 .vf_id = eth_da.representor_ports[i],
664 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
665 pf_ethdev->data->dev_private)->switch_domain_id,
666 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
667 pf_ethdev->data->dev_private)
670 /* representor port net_bdf_port */
671 snprintf(name, sizeof(name), "net_%s_representor_%d",
672 pci_dev->device.name, eth_da.representor_ports[i]);
674 retval = rte_eth_dev_create(&pci_dev->device, name,
675 sizeof(struct i40e_vf_representor), NULL, NULL,
676 i40e_vf_representor_init, &representor);
679 PMD_DRV_LOG(ERR, "failed to create i40e vf "
680 "representor %s.", name);
686 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
688 struct rte_eth_dev *ethdev;
690 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
694 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
695 return rte_eth_dev_pci_generic_remove(pci_dev,
696 i40e_vf_representor_uninit);
698 return rte_eth_dev_pci_generic_remove(pci_dev,
699 eth_i40e_dev_uninit);
702 static struct rte_pci_driver rte_i40e_pmd = {
703 .id_table = pci_id_i40e_map,
704 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
705 .probe = eth_i40e_pci_probe,
706 .remove = eth_i40e_pci_remove,
710 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
713 uint32_t ori_reg_val;
714 struct rte_eth_dev *dev;
716 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
717 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
718 i40e_write_rx_ctl(hw, reg_addr, reg_val);
719 if (ori_reg_val != reg_val)
721 "i40e device %s changed global register [0x%08x]."
722 " original: 0x%08x, new: 0x%08x",
723 dev->device->name, reg_addr, ori_reg_val, reg_val);
726 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
727 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
728 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
730 #ifndef I40E_GLQF_ORT
731 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
733 #ifndef I40E_GLQF_PIT
734 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
736 #ifndef I40E_GLQF_L3_MAP
737 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
740 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
743 * Initialize registers for parsing packet type of QinQ
744 * This should be removed from code once proper
745 * configuration API is added to avoid configuration conflicts
746 * between ports of the same device.
748 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
749 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
752 static inline void i40e_config_automask(struct i40e_pf *pf)
754 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
757 /* INTENA flag is not auto-cleared for interrupt */
758 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
759 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
760 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
762 /* If support multi-driver, PF will use INT0. */
763 if (!pf->support_multi_driver)
764 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
766 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
769 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
772 * Add a ethertype filter to drop all flow control frames transmitted
776 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
778 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
779 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
780 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
781 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
784 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
785 I40E_FLOW_CONTROL_ETHERTYPE, flags,
786 pf->main_vsi_seid, 0,
790 "Failed to add filter to drop flow control frames from VSIs.");
794 floating_veb_list_handler(__rte_unused const char *key,
795 const char *floating_veb_value,
799 unsigned int count = 0;
802 bool *vf_floating_veb = opaque;
804 while (isblank(*floating_veb_value))
805 floating_veb_value++;
807 /* Reset floating VEB configuration for VFs */
808 for (idx = 0; idx < I40E_MAX_VF; idx++)
809 vf_floating_veb[idx] = false;
813 while (isblank(*floating_veb_value))
814 floating_veb_value++;
815 if (*floating_veb_value == '\0')
818 idx = strtoul(floating_veb_value, &end, 10);
819 if (errno || end == NULL)
821 while (isblank(*end))
825 } else if ((*end == ';') || (*end == '\0')) {
827 if (min == I40E_MAX_VF)
829 if (max >= I40E_MAX_VF)
830 max = I40E_MAX_VF - 1;
831 for (idx = min; idx <= max; idx++) {
832 vf_floating_veb[idx] = true;
839 floating_veb_value = end + 1;
840 } while (*end != '\0');
849 config_vf_floating_veb(struct rte_devargs *devargs,
850 uint16_t floating_veb,
851 bool *vf_floating_veb)
853 struct rte_kvargs *kvlist;
855 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
859 /* All the VFs attach to the floating VEB by default
860 * when the floating VEB is enabled.
862 for (i = 0; i < I40E_MAX_VF; i++)
863 vf_floating_veb[i] = true;
868 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
872 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
873 rte_kvargs_free(kvlist);
876 /* When the floating_veb_list parameter exists, all the VFs
877 * will attach to the legacy VEB firstly, then configure VFs
878 * to the floating VEB according to the floating_veb_list.
880 if (rte_kvargs_process(kvlist, floating_veb_list,
881 floating_veb_list_handler,
882 vf_floating_veb) < 0) {
883 rte_kvargs_free(kvlist);
886 rte_kvargs_free(kvlist);
890 i40e_check_floating_handler(__rte_unused const char *key,
892 __rte_unused void *opaque)
894 if (strcmp(value, "1"))
901 is_floating_veb_supported(struct rte_devargs *devargs)
903 struct rte_kvargs *kvlist;
904 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
909 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
913 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
914 rte_kvargs_free(kvlist);
917 /* Floating VEB is enabled when there's key-value:
918 * enable_floating_veb=1
920 if (rte_kvargs_process(kvlist, floating_veb_key,
921 i40e_check_floating_handler, NULL) < 0) {
922 rte_kvargs_free(kvlist);
925 rte_kvargs_free(kvlist);
931 config_floating_veb(struct rte_eth_dev *dev)
933 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
934 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
935 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
937 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
939 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
941 is_floating_veb_supported(pci_dev->device.devargs);
942 config_vf_floating_veb(pci_dev->device.devargs,
944 pf->floating_veb_list);
946 pf->floating_veb = false;
950 #define I40E_L2_TAGS_S_TAG_SHIFT 1
951 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
954 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
956 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
957 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
958 char ethertype_hash_name[RTE_HASH_NAMESIZE];
961 struct rte_hash_parameters ethertype_hash_params = {
962 .name = ethertype_hash_name,
963 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
964 .key_len = sizeof(struct i40e_ethertype_filter_input),
965 .hash_func = rte_hash_crc,
966 .hash_func_init_val = 0,
967 .socket_id = rte_socket_id(),
970 /* Initialize ethertype filter rule list and hash */
971 TAILQ_INIT(ðertype_rule->ethertype_list);
972 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
973 "ethertype_%s", dev->device->name);
974 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
975 if (!ethertype_rule->hash_table) {
976 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
979 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
980 sizeof(struct i40e_ethertype_filter *) *
981 I40E_MAX_ETHERTYPE_FILTER_NUM,
983 if (!ethertype_rule->hash_map) {
985 "Failed to allocate memory for ethertype hash map!");
987 goto err_ethertype_hash_map_alloc;
992 err_ethertype_hash_map_alloc:
993 rte_hash_free(ethertype_rule->hash_table);
999 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1001 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1002 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1003 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1006 struct rte_hash_parameters tunnel_hash_params = {
1007 .name = tunnel_hash_name,
1008 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1009 .key_len = sizeof(struct i40e_tunnel_filter_input),
1010 .hash_func = rte_hash_crc,
1011 .hash_func_init_val = 0,
1012 .socket_id = rte_socket_id(),
1015 /* Initialize tunnel filter rule list and hash */
1016 TAILQ_INIT(&tunnel_rule->tunnel_list);
1017 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1018 "tunnel_%s", dev->device->name);
1019 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1020 if (!tunnel_rule->hash_table) {
1021 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1024 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1025 sizeof(struct i40e_tunnel_filter *) *
1026 I40E_MAX_TUNNEL_FILTER_NUM,
1028 if (!tunnel_rule->hash_map) {
1030 "Failed to allocate memory for tunnel hash map!");
1032 goto err_tunnel_hash_map_alloc;
1037 err_tunnel_hash_map_alloc:
1038 rte_hash_free(tunnel_rule->hash_table);
1044 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1046 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1047 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1048 struct i40e_fdir_info *fdir_info = &pf->fdir;
1049 char fdir_hash_name[RTE_HASH_NAMESIZE];
1050 uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
1051 uint32_t best = hw->func_caps.fd_filters_best_effort;
1052 struct rte_bitmap *bmp = NULL;
1058 struct rte_hash_parameters fdir_hash_params = {
1059 .name = fdir_hash_name,
1060 .entries = I40E_MAX_FDIR_FILTER_NUM,
1061 .key_len = sizeof(struct i40e_fdir_input),
1062 .hash_func = rte_hash_crc,
1063 .hash_func_init_val = 0,
1064 .socket_id = rte_socket_id(),
1067 /* Initialize flow director filter rule list and hash */
1068 TAILQ_INIT(&fdir_info->fdir_list);
1069 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1070 "fdir_%s", dev->device->name);
1071 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1072 if (!fdir_info->hash_table) {
1073 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1077 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1078 sizeof(struct i40e_fdir_filter *) *
1079 I40E_MAX_FDIR_FILTER_NUM,
1081 if (!fdir_info->hash_map) {
1083 "Failed to allocate memory for fdir hash map!");
1085 goto err_fdir_hash_map_alloc;
1088 fdir_info->fdir_filter_array = rte_zmalloc("fdir_filter",
1089 sizeof(struct i40e_fdir_filter) *
1090 I40E_MAX_FDIR_FILTER_NUM,
1093 if (!fdir_info->fdir_filter_array) {
1095 "Failed to allocate memory for fdir filter array!");
1097 goto err_fdir_filter_array_alloc;
1100 fdir_info->fdir_space_size = alloc + best;
1101 fdir_info->fdir_actual_cnt = 0;
1102 fdir_info->fdir_guarantee_total_space = alloc;
1103 fdir_info->fdir_guarantee_free_space =
1104 fdir_info->fdir_guarantee_total_space;
1106 PMD_DRV_LOG(INFO, "FDIR guarantee space: %u, best_effort space %u.", alloc, best);
1108 fdir_info->fdir_flow_pool.pool =
1109 rte_zmalloc("i40e_fdir_entry",
1110 sizeof(struct i40e_fdir_entry) *
1111 fdir_info->fdir_space_size,
1114 if (!fdir_info->fdir_flow_pool.pool) {
1116 "Failed to allocate memory for bitmap flow!");
1118 goto err_fdir_bitmap_flow_alloc;
1121 for (i = 0; i < fdir_info->fdir_space_size; i++)
1122 fdir_info->fdir_flow_pool.pool[i].idx = i;
1125 rte_bitmap_get_memory_footprint(fdir_info->fdir_space_size);
1126 mem = rte_zmalloc("fdir_bmap", bmp_size, RTE_CACHE_LINE_SIZE);
1129 "Failed to allocate memory for fdir bitmap!");
1131 goto err_fdir_mem_alloc;
1133 bmp = rte_bitmap_init(fdir_info->fdir_space_size, mem, bmp_size);
1136 "Failed to initialization fdir bitmap!");
1138 goto err_fdir_bmp_alloc;
1140 for (i = 0; i < fdir_info->fdir_space_size; i++)
1141 rte_bitmap_set(bmp, i);
1143 fdir_info->fdir_flow_pool.bitmap = bmp;
1150 rte_free(fdir_info->fdir_flow_pool.pool);
1151 err_fdir_bitmap_flow_alloc:
1152 rte_free(fdir_info->fdir_filter_array);
1153 err_fdir_filter_array_alloc:
1154 rte_free(fdir_info->hash_map);
1155 err_fdir_hash_map_alloc:
1156 rte_hash_free(fdir_info->hash_table);
1162 i40e_init_customized_info(struct i40e_pf *pf)
1166 /* Initialize customized pctype */
1167 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1168 pf->customized_pctype[i].index = i;
1169 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1170 pf->customized_pctype[i].valid = false;
1173 pf->gtp_support = false;
1174 pf->esp_support = false;
1178 i40e_init_filter_invalidation(struct i40e_pf *pf)
1180 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1181 struct i40e_fdir_info *fdir_info = &pf->fdir;
1182 uint32_t glqf_ctl_reg = 0;
1184 glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
1185 if (!pf->support_multi_driver) {
1186 fdir_info->fdir_invalprio = 1;
1187 glqf_ctl_reg |= I40E_GLQF_CTL_INVALPRIO_MASK;
1188 PMD_DRV_LOG(INFO, "FDIR INVALPRIO set to guaranteed first");
1189 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, glqf_ctl_reg);
1191 if (glqf_ctl_reg & I40E_GLQF_CTL_INVALPRIO_MASK) {
1192 fdir_info->fdir_invalprio = 1;
1193 PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: guaranteed first");
1195 fdir_info->fdir_invalprio = 0;
1196 PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: shared first");
1202 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1204 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1205 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1206 struct i40e_queue_regions *info = &pf->queue_region;
1209 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1210 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1212 memset(info, 0, sizeof(struct i40e_queue_regions));
1216 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1221 unsigned long support_multi_driver;
1224 pf = (struct i40e_pf *)opaque;
1227 support_multi_driver = strtoul(value, &end, 10);
1228 if (errno != 0 || end == value || *end != 0) {
1229 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1233 if (support_multi_driver == 1 || support_multi_driver == 0)
1234 pf->support_multi_driver = (bool)support_multi_driver;
1236 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1237 "enable global configuration by default."
1238 ETH_I40E_SUPPORT_MULTI_DRIVER);
1243 i40e_support_multi_driver(struct rte_eth_dev *dev)
1245 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1246 struct rte_kvargs *kvlist;
1249 /* Enable global configuration by default */
1250 pf->support_multi_driver = false;
1252 if (!dev->device->devargs)
1255 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1259 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1260 if (!kvargs_count) {
1261 rte_kvargs_free(kvlist);
1265 if (kvargs_count > 1)
1266 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1267 "the first invalid or last valid one is used !",
1268 ETH_I40E_SUPPORT_MULTI_DRIVER);
1270 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1271 i40e_parse_multi_drv_handler, pf) < 0) {
1272 rte_kvargs_free(kvlist);
1276 rte_kvargs_free(kvlist);
1281 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1282 uint32_t reg_addr, uint64_t reg_val,
1283 struct i40e_asq_cmd_details *cmd_details)
1285 uint64_t ori_reg_val;
1286 struct rte_eth_dev *dev;
1289 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1290 if (ret != I40E_SUCCESS) {
1292 "Fail to debug read from 0x%08x",
1296 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1298 if (ori_reg_val != reg_val)
1299 PMD_DRV_LOG(WARNING,
1300 "i40e device %s changed global register [0x%08x]."
1301 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1302 dev->device->name, reg_addr, ori_reg_val, reg_val);
1304 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1308 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1312 struct i40e_adapter *ad = opaque;
1315 use_latest_vec = atoi(value);
1317 if (use_latest_vec != 0 && use_latest_vec != 1)
1318 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1320 ad->use_latest_vec = (uint8_t)use_latest_vec;
1326 i40e_use_latest_vec(struct rte_eth_dev *dev)
1328 struct i40e_adapter *ad =
1329 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1330 struct rte_kvargs *kvlist;
1333 ad->use_latest_vec = false;
1335 if (!dev->device->devargs)
1338 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1342 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1343 if (!kvargs_count) {
1344 rte_kvargs_free(kvlist);
1348 if (kvargs_count > 1)
1349 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1350 "the first invalid or last valid one is used !",
1351 ETH_I40E_USE_LATEST_VEC);
1353 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1354 i40e_parse_latest_vec_handler, ad) < 0) {
1355 rte_kvargs_free(kvlist);
1359 rte_kvargs_free(kvlist);
1364 read_vf_msg_config(__rte_unused const char *key,
1368 struct i40e_vf_msg_cfg *cfg = opaque;
1370 if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1371 &cfg->ignore_second) != 3) {
1372 memset(cfg, 0, sizeof(*cfg));
1373 PMD_DRV_LOG(ERR, "format error! example: "
1374 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1379 * If the message validation function been enabled, the 'period'
1380 * and 'ignore_second' must greater than 0.
1382 if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1383 memset(cfg, 0, sizeof(*cfg));
1384 PMD_DRV_LOG(ERR, "%s error! the second and third"
1385 " number must be greater than 0!",
1386 ETH_I40E_VF_MSG_CFG);
1394 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1395 struct i40e_vf_msg_cfg *msg_cfg)
1397 struct rte_kvargs *kvlist;
1401 memset(msg_cfg, 0, sizeof(*msg_cfg));
1403 if (!dev->device->devargs)
1406 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1410 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1414 if (kvargs_count > 1) {
1415 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1416 ETH_I40E_VF_MSG_CFG);
1421 if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1422 read_vf_msg_config, msg_cfg) < 0)
1426 rte_kvargs_free(kvlist);
1430 #define I40E_ALARM_INTERVAL 50000 /* us */
1433 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1435 struct rte_pci_device *pci_dev;
1436 struct rte_intr_handle *intr_handle;
1437 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1438 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1439 struct i40e_vsi *vsi;
1442 uint8_t aq_fail = 0;
1444 PMD_INIT_FUNC_TRACE();
1446 dev->dev_ops = &i40e_eth_dev_ops;
1447 dev->rx_queue_count = i40e_dev_rx_queue_count;
1448 dev->rx_descriptor_done = i40e_dev_rx_descriptor_done;
1449 dev->rx_descriptor_status = i40e_dev_rx_descriptor_status;
1450 dev->tx_descriptor_status = i40e_dev_tx_descriptor_status;
1451 dev->rx_pkt_burst = i40e_recv_pkts;
1452 dev->tx_pkt_burst = i40e_xmit_pkts;
1453 dev->tx_pkt_prepare = i40e_prep_pkts;
1455 /* for secondary processes, we don't initialise any further as primary
1456 * has already done this work. Only check we don't need a different
1458 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1459 i40e_set_rx_function(dev);
1460 i40e_set_tx_function(dev);
1463 i40e_set_default_ptype_table(dev);
1464 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1465 intr_handle = &pci_dev->intr_handle;
1467 rte_eth_copy_pci_info(dev, pci_dev);
1468 dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1470 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1471 pf->adapter->eth_dev = dev;
1472 pf->dev_data = dev->data;
1474 hw->back = I40E_PF_TO_ADAPTER(pf);
1475 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1478 "Hardware is not available, as address is NULL");
1482 hw->vendor_id = pci_dev->id.vendor_id;
1483 hw->device_id = pci_dev->id.device_id;
1484 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1485 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1486 hw->bus.device = pci_dev->addr.devid;
1487 hw->bus.func = pci_dev->addr.function;
1488 hw->adapter_stopped = 0;
1489 hw->adapter_closed = 0;
1491 /* Init switch device pointer */
1492 hw->switch_dev = NULL;
1495 * Switch Tag value should not be identical to either the First Tag
1496 * or Second Tag values. So set something other than common Ethertype
1497 * for internal switching.
1499 hw->switch_tag = 0xffff;
1501 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1502 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1503 PMD_INIT_LOG(ERR, "\nERROR: "
1504 "Firmware recovery mode detected. Limiting functionality.\n"
1505 "Refer to the Intel(R) Ethernet Adapters and Devices "
1506 "User Guide for details on firmware recovery mode.");
1510 i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1511 /* Check if need to support multi-driver */
1512 i40e_support_multi_driver(dev);
1513 /* Check if users want the latest supported vec path */
1514 i40e_use_latest_vec(dev);
1516 /* Make sure all is clean before doing PF reset */
1519 /* Reset here to make sure all is clean for each PF */
1520 ret = i40e_pf_reset(hw);
1522 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1526 /* Initialize the shared code (base driver) */
1527 ret = i40e_init_shared_code(hw);
1529 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1533 /* Initialize the parameters for adminq */
1534 i40e_init_adminq_parameter(hw);
1535 ret = i40e_init_adminq(hw);
1536 if (ret != I40E_SUCCESS) {
1537 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1540 /* Firmware of SFP x722 does not support adminq option */
1541 if (hw->device_id == I40E_DEV_ID_SFP_X722)
1542 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1544 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1545 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1546 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1547 ((hw->nvm.version >> 12) & 0xf),
1548 ((hw->nvm.version >> 4) & 0xff),
1549 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1551 /* Initialize the hardware */
1554 i40e_config_automask(pf);
1556 i40e_set_default_pctype_table(dev);
1559 * To work around the NVM issue, initialize registers
1560 * for packet type of QinQ by software.
1561 * It should be removed once issues are fixed in NVM.
1563 if (!pf->support_multi_driver)
1564 i40e_GLQF_reg_init(hw);
1566 /* Initialize the input set for filters (hash and fd) to default value */
1567 i40e_filter_input_set_init(pf);
1569 /* initialise the L3_MAP register */
1570 if (!pf->support_multi_driver) {
1571 ret = i40e_aq_debug_write_global_register(hw,
1572 I40E_GLQF_L3_MAP(40),
1575 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1578 "Global register 0x%08x is changed with 0x28",
1579 I40E_GLQF_L3_MAP(40));
1582 /* Need the special FW version to support floating VEB */
1583 config_floating_veb(dev);
1584 /* Clear PXE mode */
1585 i40e_clear_pxe_mode(hw);
1586 i40e_dev_sync_phy_type(hw);
1589 * On X710, performance number is far from the expectation on recent
1590 * firmware versions. The fix for this issue may not be integrated in
1591 * the following firmware version. So the workaround in software driver
1592 * is needed. It needs to modify the initial values of 3 internal only
1593 * registers. Note that the workaround can be removed when it is fixed
1594 * in firmware in the future.
1596 i40e_configure_registers(hw);
1598 /* Get hw capabilities */
1599 ret = i40e_get_cap(hw);
1600 if (ret != I40E_SUCCESS) {
1601 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1602 goto err_get_capabilities;
1605 /* Initialize parameters for PF */
1606 ret = i40e_pf_parameter_init(dev);
1608 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1609 goto err_parameter_init;
1612 /* Initialize the queue management */
1613 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1615 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1616 goto err_qp_pool_init;
1618 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1619 hw->func_caps.num_msix_vectors - 1);
1621 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1622 goto err_msix_pool_init;
1625 /* Initialize lan hmc */
1626 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1627 hw->func_caps.num_rx_qp, 0, 0);
1628 if (ret != I40E_SUCCESS) {
1629 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1630 goto err_init_lan_hmc;
1633 /* Configure lan hmc */
1634 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1635 if (ret != I40E_SUCCESS) {
1636 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1637 goto err_configure_lan_hmc;
1640 /* Get and check the mac address */
1641 i40e_get_mac_addr(hw, hw->mac.addr);
1642 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1643 PMD_INIT_LOG(ERR, "mac address is not valid");
1645 goto err_get_mac_addr;
1647 /* Copy the permanent MAC address */
1648 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1649 (struct rte_ether_addr *)hw->mac.perm_addr);
1651 /* Disable flow control */
1652 hw->fc.requested_mode = I40E_FC_NONE;
1653 i40e_set_fc(hw, &aq_fail, TRUE);
1655 /* Set the global registers with default ether type value */
1656 if (!pf->support_multi_driver) {
1657 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1658 RTE_ETHER_TYPE_VLAN);
1659 if (ret != I40E_SUCCESS) {
1661 "Failed to set the default outer "
1663 goto err_setup_pf_switch;
1667 /* PF setup, which includes VSI setup */
1668 ret = i40e_pf_setup(pf);
1670 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1671 goto err_setup_pf_switch;
1676 /* Disable double vlan by default */
1677 i40e_vsi_config_double_vlan(vsi, FALSE);
1679 /* Disable S-TAG identification when floating_veb is disabled */
1680 if (!pf->floating_veb) {
1681 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1682 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1683 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1684 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1688 if (!vsi->max_macaddrs)
1689 len = RTE_ETHER_ADDR_LEN;
1691 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1693 /* Should be after VSI initialized */
1694 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1695 if (!dev->data->mac_addrs) {
1697 "Failed to allocated memory for storing mac address");
1700 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1701 &dev->data->mac_addrs[0]);
1703 /* Init dcb to sw mode by default */
1704 ret = i40e_dcb_init_configure(dev, TRUE);
1705 if (ret != I40E_SUCCESS) {
1706 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1707 pf->flags &= ~I40E_FLAG_DCB;
1709 /* Update HW struct after DCB configuration */
1712 /* initialize pf host driver to setup SRIOV resource if applicable */
1713 i40e_pf_host_init(dev);
1715 /* register callback func to eal lib */
1716 rte_intr_callback_register(intr_handle,
1717 i40e_dev_interrupt_handler, dev);
1719 /* configure and enable device interrupt */
1720 i40e_pf_config_irq0(hw, TRUE);
1721 i40e_pf_enable_irq0(hw);
1723 /* enable uio intr after callback register */
1724 rte_intr_enable(intr_handle);
1726 /* By default disable flexible payload in global configuration */
1727 if (!pf->support_multi_driver)
1728 i40e_flex_payload_reg_set_default(hw);
1731 * Add an ethertype filter to drop all flow control frames transmitted
1732 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1735 i40e_add_tx_flow_control_drop_filter(pf);
1737 /* Set the max frame size to 0x2600 by default,
1738 * in case other drivers changed the default value.
1740 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1742 /* initialize mirror rule list */
1743 TAILQ_INIT(&pf->mirror_list);
1745 /* initialize RSS rule list */
1746 TAILQ_INIT(&pf->rss_config_list);
1748 /* initialize Traffic Manager configuration */
1749 i40e_tm_conf_init(dev);
1751 /* Initialize customized information */
1752 i40e_init_customized_info(pf);
1754 /* Initialize the filter invalidation configuration */
1755 i40e_init_filter_invalidation(pf);
1757 ret = i40e_init_ethtype_filter_list(dev);
1759 goto err_init_ethtype_filter_list;
1760 ret = i40e_init_tunnel_filter_list(dev);
1762 goto err_init_tunnel_filter_list;
1763 ret = i40e_init_fdir_filter_list(dev);
1765 goto err_init_fdir_filter_list;
1767 /* initialize queue region configuration */
1768 i40e_init_queue_region_conf(dev);
1770 /* initialize RSS configuration from rte_flow */
1771 memset(&pf->rss_info, 0,
1772 sizeof(struct i40e_rte_flow_rss_conf));
1774 /* reset all stats of the device, including pf and main vsi */
1775 i40e_dev_stats_reset(dev);
1779 err_init_fdir_filter_list:
1780 rte_free(pf->tunnel.hash_table);
1781 rte_free(pf->tunnel.hash_map);
1782 err_init_tunnel_filter_list:
1783 rte_free(pf->ethertype.hash_table);
1784 rte_free(pf->ethertype.hash_map);
1785 err_init_ethtype_filter_list:
1786 rte_free(dev->data->mac_addrs);
1787 dev->data->mac_addrs = NULL;
1789 i40e_vsi_release(pf->main_vsi);
1790 err_setup_pf_switch:
1792 err_configure_lan_hmc:
1793 (void)i40e_shutdown_lan_hmc(hw);
1795 i40e_res_pool_destroy(&pf->msix_pool);
1797 i40e_res_pool_destroy(&pf->qp_pool);
1800 err_get_capabilities:
1801 (void)i40e_shutdown_adminq(hw);
1807 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1809 struct i40e_ethertype_filter *p_ethertype;
1810 struct i40e_ethertype_rule *ethertype_rule;
1812 ethertype_rule = &pf->ethertype;
1813 /* Remove all ethertype filter rules and hash */
1814 if (ethertype_rule->hash_map)
1815 rte_free(ethertype_rule->hash_map);
1816 if (ethertype_rule->hash_table)
1817 rte_hash_free(ethertype_rule->hash_table);
1819 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1820 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1821 p_ethertype, rules);
1822 rte_free(p_ethertype);
1827 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1829 struct i40e_tunnel_filter *p_tunnel;
1830 struct i40e_tunnel_rule *tunnel_rule;
1832 tunnel_rule = &pf->tunnel;
1833 /* Remove all tunnel director rules and hash */
1834 if (tunnel_rule->hash_map)
1835 rte_free(tunnel_rule->hash_map);
1836 if (tunnel_rule->hash_table)
1837 rte_hash_free(tunnel_rule->hash_table);
1839 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1840 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1846 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1848 struct i40e_fdir_filter *p_fdir;
1849 struct i40e_fdir_info *fdir_info;
1851 fdir_info = &pf->fdir;
1853 /* Remove all flow director rules */
1854 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list)))
1855 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1859 i40e_fdir_memory_cleanup(struct i40e_pf *pf)
1861 struct i40e_fdir_info *fdir_info;
1863 fdir_info = &pf->fdir;
1865 /* flow director memory cleanup */
1866 if (fdir_info->hash_map)
1867 rte_free(fdir_info->hash_map);
1868 if (fdir_info->hash_table)
1869 rte_hash_free(fdir_info->hash_table);
1870 if (fdir_info->fdir_flow_pool.bitmap)
1871 rte_free(fdir_info->fdir_flow_pool.bitmap);
1872 if (fdir_info->fdir_flow_pool.pool)
1873 rte_free(fdir_info->fdir_flow_pool.pool);
1874 if (fdir_info->fdir_filter_array)
1875 rte_free(fdir_info->fdir_filter_array);
1878 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1881 * Disable by default flexible payload
1882 * for corresponding L2/L3/L4 layers.
1884 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1885 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1886 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1890 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1894 PMD_INIT_FUNC_TRACE();
1896 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1899 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1901 if (hw->adapter_closed == 0)
1902 i40e_dev_close(dev);
1908 i40e_dev_configure(struct rte_eth_dev *dev)
1910 struct i40e_adapter *ad =
1911 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1912 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1913 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1914 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1917 ret = i40e_dev_sync_phy_type(hw);
1921 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1922 * bulk allocation or vector Rx preconditions we will reset it.
1924 ad->rx_bulk_alloc_allowed = true;
1925 ad->rx_vec_allowed = true;
1926 ad->tx_simple_allowed = true;
1927 ad->tx_vec_allowed = true;
1929 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1930 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1932 /* Only legacy filter API needs the following fdir config. So when the
1933 * legacy filter API is deprecated, the following codes should also be
1936 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1937 ret = i40e_fdir_setup(pf);
1938 if (ret != I40E_SUCCESS) {
1939 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1942 ret = i40e_fdir_configure(dev);
1944 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1948 i40e_fdir_teardown(pf);
1950 ret = i40e_dev_init_vlan(dev);
1955 * General PMD driver call sequence are NIC init, configure,
1956 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1957 * will try to lookup the VSI that specific queue belongs to if VMDQ
1958 * applicable. So, VMDQ setting has to be done before
1959 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1960 * For RSS setting, it will try to calculate actual configured RX queue
1961 * number, which will be available after rx_queue_setup(). dev_start()
1962 * function is good to place RSS setup.
1964 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1965 ret = i40e_vmdq_setup(dev);
1970 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1971 ret = i40e_dcb_setup(dev);
1973 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1978 TAILQ_INIT(&pf->flow_list);
1983 /* need to release vmdq resource if exists */
1984 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1985 i40e_vsi_release(pf->vmdq[i].vsi);
1986 pf->vmdq[i].vsi = NULL;
1991 /* Need to release fdir resource if exists.
1992 * Only legacy filter API needs the following fdir config. So when the
1993 * legacy filter API is deprecated, the following code should also be
1996 i40e_fdir_teardown(pf);
2001 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
2003 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2004 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2005 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2006 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2007 uint16_t msix_vect = vsi->msix_intr;
2010 for (i = 0; i < vsi->nb_qps; i++) {
2011 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2012 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2016 if (vsi->type != I40E_VSI_SRIOV) {
2017 if (!rte_intr_allow_others(intr_handle)) {
2018 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2019 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
2021 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2024 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2025 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
2027 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2032 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2033 vsi->user_param + (msix_vect - 1);
2035 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2036 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
2038 I40E_WRITE_FLUSH(hw);
2042 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
2043 int base_queue, int nb_queue,
2048 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2049 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2051 /* Bind all RX queues to allocated MSIX interrupt */
2052 for (i = 0; i < nb_queue; i++) {
2053 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2054 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
2055 ((base_queue + i + 1) <<
2056 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2057 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
2058 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2060 if (i == nb_queue - 1)
2061 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
2062 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
2065 /* Write first RX queue to Link list register as the head element */
2066 if (vsi->type != I40E_VSI_SRIOV) {
2068 i40e_calc_itr_interval(1, pf->support_multi_driver);
2070 if (msix_vect == I40E_MISC_VEC_ID) {
2071 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2073 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2075 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2077 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2080 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2082 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2084 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2086 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2093 if (msix_vect == I40E_MISC_VEC_ID) {
2095 I40E_VPINT_LNKLST0(vsi->user_param),
2097 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2099 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2101 /* num_msix_vectors_vf needs to minus irq0 */
2102 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2103 vsi->user_param + (msix_vect - 1);
2105 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2107 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2109 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2113 I40E_WRITE_FLUSH(hw);
2117 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2119 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2120 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2121 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2122 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2123 uint16_t msix_vect = vsi->msix_intr;
2124 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2125 uint16_t queue_idx = 0;
2129 for (i = 0; i < vsi->nb_qps; i++) {
2130 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2131 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2134 /* VF bind interrupt */
2135 if (vsi->type == I40E_VSI_SRIOV) {
2136 if (vsi->nb_msix == 0) {
2137 PMD_DRV_LOG(ERR, "No msix resource");
2140 __vsi_queues_bind_intr(vsi, msix_vect,
2141 vsi->base_queue, vsi->nb_qps,
2146 /* PF & VMDq bind interrupt */
2147 if (rte_intr_dp_is_en(intr_handle)) {
2148 if (vsi->type == I40E_VSI_MAIN) {
2151 } else if (vsi->type == I40E_VSI_VMDQ2) {
2152 struct i40e_vsi *main_vsi =
2153 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2154 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2159 for (i = 0; i < vsi->nb_used_qps; i++) {
2160 if (vsi->nb_msix == 0) {
2161 PMD_DRV_LOG(ERR, "No msix resource");
2163 } else if (nb_msix <= 1) {
2164 if (!rte_intr_allow_others(intr_handle))
2165 /* allow to share MISC_VEC_ID */
2166 msix_vect = I40E_MISC_VEC_ID;
2168 /* no enough msix_vect, map all to one */
2169 __vsi_queues_bind_intr(vsi, msix_vect,
2170 vsi->base_queue + i,
2171 vsi->nb_used_qps - i,
2173 for (; !!record && i < vsi->nb_used_qps; i++)
2174 intr_handle->intr_vec[queue_idx + i] =
2178 /* 1:1 queue/msix_vect mapping */
2179 __vsi_queues_bind_intr(vsi, msix_vect,
2180 vsi->base_queue + i, 1,
2183 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2193 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2195 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2196 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2197 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2198 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2199 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2200 uint16_t msix_intr, i;
2202 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2203 for (i = 0; i < vsi->nb_msix; i++) {
2204 msix_intr = vsi->msix_intr + i;
2205 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2206 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2207 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2208 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2211 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2212 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2213 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2214 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2216 I40E_WRITE_FLUSH(hw);
2220 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2222 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2223 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2224 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2225 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2226 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2227 uint16_t msix_intr, i;
2229 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2230 for (i = 0; i < vsi->nb_msix; i++) {
2231 msix_intr = vsi->msix_intr + i;
2232 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2233 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2236 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2237 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2239 I40E_WRITE_FLUSH(hw);
2242 static inline uint8_t
2243 i40e_parse_link_speeds(uint16_t link_speeds)
2245 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2247 if (link_speeds & ETH_LINK_SPEED_40G)
2248 link_speed |= I40E_LINK_SPEED_40GB;
2249 if (link_speeds & ETH_LINK_SPEED_25G)
2250 link_speed |= I40E_LINK_SPEED_25GB;
2251 if (link_speeds & ETH_LINK_SPEED_20G)
2252 link_speed |= I40E_LINK_SPEED_20GB;
2253 if (link_speeds & ETH_LINK_SPEED_10G)
2254 link_speed |= I40E_LINK_SPEED_10GB;
2255 if (link_speeds & ETH_LINK_SPEED_1G)
2256 link_speed |= I40E_LINK_SPEED_1GB;
2257 if (link_speeds & ETH_LINK_SPEED_100M)
2258 link_speed |= I40E_LINK_SPEED_100MB;
2264 i40e_phy_conf_link(struct i40e_hw *hw,
2266 uint8_t force_speed,
2269 enum i40e_status_code status;
2270 struct i40e_aq_get_phy_abilities_resp phy_ab;
2271 struct i40e_aq_set_phy_config phy_conf;
2272 enum i40e_aq_phy_type cnt;
2273 uint8_t avail_speed;
2274 uint32_t phy_type_mask = 0;
2276 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2277 I40E_AQ_PHY_FLAG_PAUSE_RX |
2278 I40E_AQ_PHY_FLAG_PAUSE_RX |
2279 I40E_AQ_PHY_FLAG_LOW_POWER;
2282 /* To get phy capabilities of available speeds. */
2283 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2286 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2290 avail_speed = phy_ab.link_speed;
2292 /* To get the current phy config. */
2293 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2296 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2301 /* If link needs to go up and it is in autoneg mode the speed is OK,
2302 * no need to set up again.
2304 if (is_up && phy_ab.phy_type != 0 &&
2305 abilities & I40E_AQ_PHY_AN_ENABLED &&
2306 phy_ab.link_speed != 0)
2307 return I40E_SUCCESS;
2309 memset(&phy_conf, 0, sizeof(phy_conf));
2311 /* bits 0-2 use the values from get_phy_abilities_resp */
2313 abilities |= phy_ab.abilities & mask;
2315 phy_conf.abilities = abilities;
2317 /* If link needs to go up, but the force speed is not supported,
2318 * Warn users and config the default available speeds.
2320 if (is_up && !(force_speed & avail_speed)) {
2321 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2322 phy_conf.link_speed = avail_speed;
2324 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2327 /* PHY type mask needs to include each type except PHY type extension */
2328 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2329 phy_type_mask |= 1 << cnt;
2331 /* use get_phy_abilities_resp value for the rest */
2332 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2333 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2334 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2335 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2336 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2337 phy_conf.eee_capability = phy_ab.eee_capability;
2338 phy_conf.eeer = phy_ab.eeer_val;
2339 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2341 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2342 phy_ab.abilities, phy_ab.link_speed);
2343 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2344 phy_conf.abilities, phy_conf.link_speed);
2346 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2350 return I40E_SUCCESS;
2354 i40e_apply_link_speed(struct rte_eth_dev *dev)
2357 uint8_t abilities = 0;
2358 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2359 struct rte_eth_conf *conf = &dev->data->dev_conf;
2361 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2362 I40E_AQ_PHY_LINK_ENABLED;
2364 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2365 conf->link_speeds = ETH_LINK_SPEED_40G |
2366 ETH_LINK_SPEED_25G |
2367 ETH_LINK_SPEED_20G |
2368 ETH_LINK_SPEED_10G |
2370 ETH_LINK_SPEED_100M;
2372 abilities |= I40E_AQ_PHY_AN_ENABLED;
2374 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2376 speed = i40e_parse_link_speeds(conf->link_speeds);
2378 return i40e_phy_conf_link(hw, abilities, speed, true);
2382 i40e_dev_start(struct rte_eth_dev *dev)
2384 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2385 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2386 struct i40e_vsi *main_vsi = pf->main_vsi;
2388 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2389 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2390 uint32_t intr_vector = 0;
2391 struct i40e_vsi *vsi;
2392 uint16_t nb_rxq, nb_txq;
2394 hw->adapter_stopped = 0;
2396 rte_intr_disable(intr_handle);
2398 if ((rte_intr_cap_multiple(intr_handle) ||
2399 !RTE_ETH_DEV_SRIOV(dev).active) &&
2400 dev->data->dev_conf.intr_conf.rxq != 0) {
2401 intr_vector = dev->data->nb_rx_queues;
2402 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2407 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2408 intr_handle->intr_vec =
2409 rte_zmalloc("intr_vec",
2410 dev->data->nb_rx_queues * sizeof(int),
2412 if (!intr_handle->intr_vec) {
2414 "Failed to allocate %d rx_queues intr_vec",
2415 dev->data->nb_rx_queues);
2420 /* Initialize VSI */
2421 ret = i40e_dev_rxtx_init(pf);
2422 if (ret != I40E_SUCCESS) {
2423 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2427 /* Map queues with MSIX interrupt */
2428 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2429 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2430 ret = i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2433 i40e_vsi_enable_queues_intr(main_vsi);
2435 /* Map VMDQ VSI queues with MSIX interrupt */
2436 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2437 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2438 ret = i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2439 I40E_ITR_INDEX_DEFAULT);
2442 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2445 /* Enable all queues which have been configured */
2446 for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2447 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2452 for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2453 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2458 /* Enable receiving broadcast packets */
2459 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2460 if (ret != I40E_SUCCESS)
2461 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2463 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2464 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2466 if (ret != I40E_SUCCESS)
2467 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2470 /* Enable the VLAN promiscuous mode. */
2472 for (i = 0; i < pf->vf_num; i++) {
2473 vsi = pf->vfs[i].vsi;
2474 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2479 /* Enable mac loopback mode */
2480 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2481 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2482 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2483 if (ret != I40E_SUCCESS) {
2484 PMD_DRV_LOG(ERR, "fail to set loopback link");
2489 /* Apply link configure */
2490 ret = i40e_apply_link_speed(dev);
2491 if (I40E_SUCCESS != ret) {
2492 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2496 if (!rte_intr_allow_others(intr_handle)) {
2497 rte_intr_callback_unregister(intr_handle,
2498 i40e_dev_interrupt_handler,
2500 /* configure and enable device interrupt */
2501 i40e_pf_config_irq0(hw, FALSE);
2502 i40e_pf_enable_irq0(hw);
2504 if (dev->data->dev_conf.intr_conf.lsc != 0)
2506 "lsc won't enable because of no intr multiplex");
2508 ret = i40e_aq_set_phy_int_mask(hw,
2509 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2510 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2511 I40E_AQ_EVENT_MEDIA_NA), NULL);
2512 if (ret != I40E_SUCCESS)
2513 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2515 /* Call get_link_info aq commond to enable/disable LSE */
2516 i40e_dev_link_update(dev, 0);
2519 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2520 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2521 i40e_dev_alarm_handler, dev);
2523 /* enable uio intr after callback register */
2524 rte_intr_enable(intr_handle);
2527 i40e_filter_restore(pf);
2529 if (pf->tm_conf.root && !pf->tm_conf.committed)
2530 PMD_DRV_LOG(WARNING,
2531 "please call hierarchy_commit() "
2532 "before starting the port");
2534 return I40E_SUCCESS;
2537 for (i = 0; i < nb_txq; i++)
2538 i40e_dev_tx_queue_stop(dev, i);
2540 for (i = 0; i < nb_rxq; i++)
2541 i40e_dev_rx_queue_stop(dev, i);
2547 i40e_dev_stop(struct rte_eth_dev *dev)
2549 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2550 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2551 struct i40e_vsi *main_vsi = pf->main_vsi;
2552 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2553 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2556 if (hw->adapter_stopped == 1)
2559 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2560 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2561 rte_intr_enable(intr_handle);
2564 /* Disable all queues */
2565 for (i = 0; i < dev->data->nb_tx_queues; i++)
2566 i40e_dev_tx_queue_stop(dev, i);
2568 for (i = 0; i < dev->data->nb_rx_queues; i++)
2569 i40e_dev_rx_queue_stop(dev, i);
2571 /* un-map queues with interrupt registers */
2572 i40e_vsi_disable_queues_intr(main_vsi);
2573 i40e_vsi_queues_unbind_intr(main_vsi);
2575 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2576 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2577 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2580 /* Clear all queues and release memory */
2581 i40e_dev_clear_queues(dev);
2584 i40e_dev_set_link_down(dev);
2586 if (!rte_intr_allow_others(intr_handle))
2587 /* resume to the default handler */
2588 rte_intr_callback_register(intr_handle,
2589 i40e_dev_interrupt_handler,
2592 /* Clean datapath event and queue/vec mapping */
2593 rte_intr_efd_disable(intr_handle);
2594 if (intr_handle->intr_vec) {
2595 rte_free(intr_handle->intr_vec);
2596 intr_handle->intr_vec = NULL;
2599 /* reset hierarchy commit */
2600 pf->tm_conf.committed = false;
2602 hw->adapter_stopped = 1;
2603 dev->data->dev_started = 0;
2605 pf->adapter->rss_reta_updated = 0;
2611 i40e_dev_close(struct rte_eth_dev *dev)
2613 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2614 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2615 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2616 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2617 struct i40e_mirror_rule *p_mirror;
2618 struct i40e_filter_control_settings settings;
2619 struct rte_flow *p_flow;
2623 uint8_t aq_fail = 0;
2626 PMD_INIT_FUNC_TRACE();
2627 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2630 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2632 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2635 ret = i40e_dev_stop(dev);
2637 /* Remove all mirror rules */
2638 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2639 ret = i40e_aq_del_mirror_rule(hw,
2640 pf->main_vsi->veb->seid,
2641 p_mirror->rule_type,
2643 p_mirror->num_entries,
2646 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2647 "status = %d, aq_err = %d.", ret,
2648 hw->aq.asq_last_status);
2650 /* remove mirror software resource anyway */
2651 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2653 pf->nb_mirror_rule--;
2656 i40e_dev_free_queues(dev);
2658 /* Disable interrupt */
2659 i40e_pf_disable_irq0(hw);
2660 rte_intr_disable(intr_handle);
2663 * Only legacy filter API needs the following fdir config. So when the
2664 * legacy filter API is deprecated, the following code should also be
2667 i40e_fdir_teardown(pf);
2669 /* shutdown and destroy the HMC */
2670 i40e_shutdown_lan_hmc(hw);
2672 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2673 i40e_vsi_release(pf->vmdq[i].vsi);
2674 pf->vmdq[i].vsi = NULL;
2679 /* release all the existing VSIs and VEBs */
2680 i40e_vsi_release(pf->main_vsi);
2682 /* shutdown the adminq */
2683 i40e_aq_queue_shutdown(hw, true);
2684 i40e_shutdown_adminq(hw);
2686 i40e_res_pool_destroy(&pf->qp_pool);
2687 i40e_res_pool_destroy(&pf->msix_pool);
2689 /* Disable flexible payload in global configuration */
2690 if (!pf->support_multi_driver)
2691 i40e_flex_payload_reg_set_default(hw);
2693 /* force a PF reset to clean anything leftover */
2694 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2695 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2696 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2697 I40E_WRITE_FLUSH(hw);
2699 /* Clear PXE mode */
2700 i40e_clear_pxe_mode(hw);
2702 /* Unconfigure filter control */
2703 memset(&settings, 0, sizeof(settings));
2704 ret = i40e_set_filter_control(hw, &settings);
2706 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2709 /* Disable flow control */
2710 hw->fc.requested_mode = I40E_FC_NONE;
2711 i40e_set_fc(hw, &aq_fail, TRUE);
2713 /* uninitialize pf host driver */
2714 i40e_pf_host_uninit(dev);
2717 ret = rte_intr_callback_unregister(intr_handle,
2718 i40e_dev_interrupt_handler, dev);
2719 if (ret >= 0 || ret == -ENOENT) {
2721 } else if (ret != -EAGAIN) {
2723 "intr callback unregister failed: %d",
2726 i40e_msec_delay(500);
2727 } while (retries++ < 5);
2729 i40e_rm_ethtype_filter_list(pf);
2730 i40e_rm_tunnel_filter_list(pf);
2731 i40e_rm_fdir_filter_list(pf);
2733 /* Remove all flows */
2734 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2735 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2736 /* Do not free FDIR flows since they are static allocated */
2737 if (p_flow->filter_type != RTE_ETH_FILTER_FDIR)
2741 /* release the fdir static allocated memory */
2742 i40e_fdir_memory_cleanup(pf);
2744 /* Remove all Traffic Manager configuration */
2745 i40e_tm_conf_uninit(dev);
2747 hw->adapter_closed = 1;
2752 * Reset PF device only to re-initialize resources in PMD layer
2755 i40e_dev_reset(struct rte_eth_dev *dev)
2759 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2760 * its VF to make them align with it. The detailed notification
2761 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2762 * To avoid unexpected behavior in VF, currently reset of PF with
2763 * SR-IOV activation is not supported. It might be supported later.
2765 if (dev->data->sriov.active)
2768 ret = eth_i40e_dev_uninit(dev);
2772 ret = eth_i40e_dev_init(dev, NULL);
2778 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2780 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2781 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2782 struct i40e_vsi *vsi = pf->main_vsi;
2785 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2787 if (status != I40E_SUCCESS) {
2788 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2792 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2794 if (status != I40E_SUCCESS) {
2795 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2796 /* Rollback unicast promiscuous mode */
2797 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2806 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2808 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2809 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2810 struct i40e_vsi *vsi = pf->main_vsi;
2813 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2815 if (status != I40E_SUCCESS) {
2816 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2820 /* must remain in all_multicast mode */
2821 if (dev->data->all_multicast == 1)
2824 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2826 if (status != I40E_SUCCESS) {
2827 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2828 /* Rollback unicast promiscuous mode */
2829 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2838 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2840 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2841 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2842 struct i40e_vsi *vsi = pf->main_vsi;
2845 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2846 if (ret != I40E_SUCCESS) {
2847 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2855 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2857 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2858 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2859 struct i40e_vsi *vsi = pf->main_vsi;
2862 if (dev->data->promiscuous == 1)
2863 return 0; /* must remain in all_multicast mode */
2865 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2866 vsi->seid, FALSE, NULL);
2867 if (ret != I40E_SUCCESS) {
2868 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2876 * Set device link up.
2879 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2881 /* re-apply link speed setting */
2882 return i40e_apply_link_speed(dev);
2886 * Set device link down.
2889 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2891 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2892 uint8_t abilities = 0;
2893 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2895 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2896 return i40e_phy_conf_link(hw, abilities, speed, false);
2899 static __rte_always_inline void
2900 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2902 /* Link status registers and values*/
2903 #define I40E_PRTMAC_LINKSTA 0x001E2420
2904 #define I40E_REG_LINK_UP 0x40000080
2905 #define I40E_PRTMAC_MACC 0x001E24E0
2906 #define I40E_REG_MACC_25GB 0x00020000
2907 #define I40E_REG_SPEED_MASK 0x38000000
2908 #define I40E_REG_SPEED_0 0x00000000
2909 #define I40E_REG_SPEED_1 0x08000000
2910 #define I40E_REG_SPEED_2 0x10000000
2911 #define I40E_REG_SPEED_3 0x18000000
2912 #define I40E_REG_SPEED_4 0x20000000
2913 uint32_t link_speed;
2916 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2917 link_speed = reg_val & I40E_REG_SPEED_MASK;
2918 reg_val &= I40E_REG_LINK_UP;
2919 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2921 if (unlikely(link->link_status == 0))
2924 /* Parse the link status */
2925 switch (link_speed) {
2926 case I40E_REG_SPEED_0:
2927 link->link_speed = ETH_SPEED_NUM_100M;
2929 case I40E_REG_SPEED_1:
2930 link->link_speed = ETH_SPEED_NUM_1G;
2932 case I40E_REG_SPEED_2:
2933 if (hw->mac.type == I40E_MAC_X722)
2934 link->link_speed = ETH_SPEED_NUM_2_5G;
2936 link->link_speed = ETH_SPEED_NUM_10G;
2938 case I40E_REG_SPEED_3:
2939 if (hw->mac.type == I40E_MAC_X722) {
2940 link->link_speed = ETH_SPEED_NUM_5G;
2942 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2944 if (reg_val & I40E_REG_MACC_25GB)
2945 link->link_speed = ETH_SPEED_NUM_25G;
2947 link->link_speed = ETH_SPEED_NUM_40G;
2950 case I40E_REG_SPEED_4:
2951 if (hw->mac.type == I40E_MAC_X722)
2952 link->link_speed = ETH_SPEED_NUM_10G;
2954 link->link_speed = ETH_SPEED_NUM_20G;
2957 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2962 static __rte_always_inline void
2963 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2964 bool enable_lse, int wait_to_complete)
2966 #define CHECK_INTERVAL 100 /* 100ms */
2967 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2968 uint32_t rep_cnt = MAX_REPEAT_TIME;
2969 struct i40e_link_status link_status;
2972 memset(&link_status, 0, sizeof(link_status));
2975 memset(&link_status, 0, sizeof(link_status));
2977 /* Get link status information from hardware */
2978 status = i40e_aq_get_link_info(hw, enable_lse,
2979 &link_status, NULL);
2980 if (unlikely(status != I40E_SUCCESS)) {
2981 link->link_speed = ETH_SPEED_NUM_NONE;
2982 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2983 PMD_DRV_LOG(ERR, "Failed to get link info");
2987 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2988 if (!wait_to_complete || link->link_status)
2991 rte_delay_ms(CHECK_INTERVAL);
2992 } while (--rep_cnt);
2994 /* Parse the link status */
2995 switch (link_status.link_speed) {
2996 case I40E_LINK_SPEED_100MB:
2997 link->link_speed = ETH_SPEED_NUM_100M;
2999 case I40E_LINK_SPEED_1GB:
3000 link->link_speed = ETH_SPEED_NUM_1G;
3002 case I40E_LINK_SPEED_10GB:
3003 link->link_speed = ETH_SPEED_NUM_10G;
3005 case I40E_LINK_SPEED_20GB:
3006 link->link_speed = ETH_SPEED_NUM_20G;
3008 case I40E_LINK_SPEED_25GB:
3009 link->link_speed = ETH_SPEED_NUM_25G;
3011 case I40E_LINK_SPEED_40GB:
3012 link->link_speed = ETH_SPEED_NUM_40G;
3015 if (link->link_status)
3016 link->link_speed = ETH_SPEED_NUM_UNKNOWN;
3018 link->link_speed = ETH_SPEED_NUM_NONE;
3024 i40e_dev_link_update(struct rte_eth_dev *dev,
3025 int wait_to_complete)
3027 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3028 struct rte_eth_link link;
3029 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3032 memset(&link, 0, sizeof(link));
3034 /* i40e uses full duplex only */
3035 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3036 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3037 ETH_LINK_SPEED_FIXED);
3039 if (!wait_to_complete && !enable_lse)
3040 update_link_reg(hw, &link);
3042 update_link_aq(hw, &link, enable_lse, wait_to_complete);
3045 rte_eth_linkstatus_get(hw->switch_dev, &link);
3047 ret = rte_eth_linkstatus_set(dev, &link);
3048 i40e_notify_all_vfs_link_status(dev);
3054 i40e_stat_update_48_in_64(struct i40e_hw *hw, uint32_t hireg,
3055 uint32_t loreg, bool offset_loaded, uint64_t *offset,
3056 uint64_t *stat, uint64_t *prev_stat)
3058 i40e_stat_update_48(hw, hireg, loreg, offset_loaded, offset, stat);
3059 /* enlarge the limitation when statistics counters overflowed */
3060 if (offset_loaded) {
3061 if (I40E_RXTX_BYTES_L_48_BIT(*prev_stat) > *stat)
3062 *stat += (uint64_t)1 << I40E_48_BIT_WIDTH;
3063 *stat += I40E_RXTX_BYTES_H_16_BIT(*prev_stat);
3068 /* Get all the statistics of a VSI */
3070 i40e_update_vsi_stats(struct i40e_vsi *vsi)
3072 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
3073 struct i40e_eth_stats *nes = &vsi->eth_stats;
3074 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3075 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
3077 i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
3078 vsi->offset_loaded, &oes->rx_bytes,
3079 &nes->rx_bytes, &vsi->prev_rx_bytes);
3080 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
3081 vsi->offset_loaded, &oes->rx_unicast,
3083 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
3084 vsi->offset_loaded, &oes->rx_multicast,
3085 &nes->rx_multicast);
3086 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
3087 vsi->offset_loaded, &oes->rx_broadcast,
3088 &nes->rx_broadcast);
3089 /* exclude CRC bytes */
3090 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3091 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3093 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
3094 &oes->rx_discards, &nes->rx_discards);
3095 /* GLV_REPC not supported */
3096 /* GLV_RMPC not supported */
3097 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
3098 &oes->rx_unknown_protocol,
3099 &nes->rx_unknown_protocol);
3100 i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
3101 vsi->offset_loaded, &oes->tx_bytes,
3102 &nes->tx_bytes, &vsi->prev_tx_bytes);
3103 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
3104 vsi->offset_loaded, &oes->tx_unicast,
3106 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
3107 vsi->offset_loaded, &oes->tx_multicast,
3108 &nes->tx_multicast);
3109 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
3110 vsi->offset_loaded, &oes->tx_broadcast,
3111 &nes->tx_broadcast);
3112 /* GLV_TDPC not supported */
3113 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
3114 &oes->tx_errors, &nes->tx_errors);
3115 vsi->offset_loaded = true;
3117 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
3119 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
3120 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
3121 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
3122 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
3123 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
3124 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3125 nes->rx_unknown_protocol);
3126 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
3127 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
3128 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
3129 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
3130 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
3131 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
3132 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
3137 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3140 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3141 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3143 /* Get rx/tx bytes of internal transfer packets */
3144 i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(hw->port),
3145 I40E_GLV_GORCL(hw->port),
3147 &pf->internal_stats_offset.rx_bytes,
3148 &pf->internal_stats.rx_bytes,
3149 &pf->internal_prev_rx_bytes);
3150 i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(hw->port),
3151 I40E_GLV_GOTCL(hw->port),
3153 &pf->internal_stats_offset.tx_bytes,
3154 &pf->internal_stats.tx_bytes,
3155 &pf->internal_prev_tx_bytes);
3156 /* Get total internal rx packet count */
3157 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3158 I40E_GLV_UPRCL(hw->port),
3160 &pf->internal_stats_offset.rx_unicast,
3161 &pf->internal_stats.rx_unicast);
3162 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3163 I40E_GLV_MPRCL(hw->port),
3165 &pf->internal_stats_offset.rx_multicast,
3166 &pf->internal_stats.rx_multicast);
3167 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3168 I40E_GLV_BPRCL(hw->port),
3170 &pf->internal_stats_offset.rx_broadcast,
3171 &pf->internal_stats.rx_broadcast);
3172 /* Get total internal tx packet count */
3173 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3174 I40E_GLV_UPTCL(hw->port),
3176 &pf->internal_stats_offset.tx_unicast,
3177 &pf->internal_stats.tx_unicast);
3178 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3179 I40E_GLV_MPTCL(hw->port),
3181 &pf->internal_stats_offset.tx_multicast,
3182 &pf->internal_stats.tx_multicast);
3183 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3184 I40E_GLV_BPTCL(hw->port),
3186 &pf->internal_stats_offset.tx_broadcast,
3187 &pf->internal_stats.tx_broadcast);
3189 /* exclude CRC size */
3190 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3191 pf->internal_stats.rx_multicast +
3192 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3194 /* Get statistics of struct i40e_eth_stats */
3195 i40e_stat_update_48_in_64(hw, I40E_GLPRT_GORCH(hw->port),
3196 I40E_GLPRT_GORCL(hw->port),
3197 pf->offset_loaded, &os->eth.rx_bytes,
3198 &ns->eth.rx_bytes, &pf->prev_rx_bytes);
3199 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3200 I40E_GLPRT_UPRCL(hw->port),
3201 pf->offset_loaded, &os->eth.rx_unicast,
3202 &ns->eth.rx_unicast);
3203 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3204 I40E_GLPRT_MPRCL(hw->port),
3205 pf->offset_loaded, &os->eth.rx_multicast,
3206 &ns->eth.rx_multicast);
3207 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3208 I40E_GLPRT_BPRCL(hw->port),
3209 pf->offset_loaded, &os->eth.rx_broadcast,
3210 &ns->eth.rx_broadcast);
3211 /* Workaround: CRC size should not be included in byte statistics,
3212 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3215 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3216 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3218 /* exclude internal rx bytes
3219 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3220 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3222 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3224 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3225 ns->eth.rx_bytes = 0;
3227 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3229 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3230 ns->eth.rx_unicast = 0;
3232 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3234 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3235 ns->eth.rx_multicast = 0;
3237 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3239 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3240 ns->eth.rx_broadcast = 0;
3242 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3244 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3245 pf->offset_loaded, &os->eth.rx_discards,
3246 &ns->eth.rx_discards);
3247 /* GLPRT_REPC not supported */
3248 /* GLPRT_RMPC not supported */
3249 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3251 &os->eth.rx_unknown_protocol,
3252 &ns->eth.rx_unknown_protocol);
3253 i40e_stat_update_48_in_64(hw, I40E_GLPRT_GOTCH(hw->port),
3254 I40E_GLPRT_GOTCL(hw->port),
3255 pf->offset_loaded, &os->eth.tx_bytes,
3256 &ns->eth.tx_bytes, &pf->prev_tx_bytes);
3257 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3258 I40E_GLPRT_UPTCL(hw->port),
3259 pf->offset_loaded, &os->eth.tx_unicast,
3260 &ns->eth.tx_unicast);
3261 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3262 I40E_GLPRT_MPTCL(hw->port),
3263 pf->offset_loaded, &os->eth.tx_multicast,
3264 &ns->eth.tx_multicast);
3265 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3266 I40E_GLPRT_BPTCL(hw->port),
3267 pf->offset_loaded, &os->eth.tx_broadcast,
3268 &ns->eth.tx_broadcast);
3269 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3270 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3272 /* exclude internal tx bytes
3273 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3274 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3276 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3278 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3279 ns->eth.tx_bytes = 0;
3281 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3283 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3284 ns->eth.tx_unicast = 0;
3286 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3288 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3289 ns->eth.tx_multicast = 0;
3291 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3293 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3294 ns->eth.tx_broadcast = 0;
3296 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3298 /* GLPRT_TEPC not supported */
3300 /* additional port specific stats */
3301 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3302 pf->offset_loaded, &os->tx_dropped_link_down,
3303 &ns->tx_dropped_link_down);
3304 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3305 pf->offset_loaded, &os->crc_errors,
3307 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3308 pf->offset_loaded, &os->illegal_bytes,
3309 &ns->illegal_bytes);
3310 /* GLPRT_ERRBC not supported */
3311 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3312 pf->offset_loaded, &os->mac_local_faults,
3313 &ns->mac_local_faults);
3314 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3315 pf->offset_loaded, &os->mac_remote_faults,
3316 &ns->mac_remote_faults);
3317 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3318 pf->offset_loaded, &os->rx_length_errors,
3319 &ns->rx_length_errors);
3320 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3321 pf->offset_loaded, &os->link_xon_rx,
3323 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3324 pf->offset_loaded, &os->link_xoff_rx,
3326 for (i = 0; i < 8; i++) {
3327 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3329 &os->priority_xon_rx[i],
3330 &ns->priority_xon_rx[i]);
3331 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3333 &os->priority_xoff_rx[i],
3334 &ns->priority_xoff_rx[i]);
3336 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3337 pf->offset_loaded, &os->link_xon_tx,
3339 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3340 pf->offset_loaded, &os->link_xoff_tx,
3342 for (i = 0; i < 8; i++) {
3343 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3345 &os->priority_xon_tx[i],
3346 &ns->priority_xon_tx[i]);
3347 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3349 &os->priority_xoff_tx[i],
3350 &ns->priority_xoff_tx[i]);
3351 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3353 &os->priority_xon_2_xoff[i],
3354 &ns->priority_xon_2_xoff[i]);
3356 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3357 I40E_GLPRT_PRC64L(hw->port),
3358 pf->offset_loaded, &os->rx_size_64,
3360 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3361 I40E_GLPRT_PRC127L(hw->port),
3362 pf->offset_loaded, &os->rx_size_127,
3364 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3365 I40E_GLPRT_PRC255L(hw->port),
3366 pf->offset_loaded, &os->rx_size_255,
3368 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3369 I40E_GLPRT_PRC511L(hw->port),
3370 pf->offset_loaded, &os->rx_size_511,
3372 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3373 I40E_GLPRT_PRC1023L(hw->port),
3374 pf->offset_loaded, &os->rx_size_1023,
3376 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3377 I40E_GLPRT_PRC1522L(hw->port),
3378 pf->offset_loaded, &os->rx_size_1522,
3380 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3381 I40E_GLPRT_PRC9522L(hw->port),
3382 pf->offset_loaded, &os->rx_size_big,
3384 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3385 pf->offset_loaded, &os->rx_undersize,
3387 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3388 pf->offset_loaded, &os->rx_fragments,
3390 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3391 pf->offset_loaded, &os->rx_oversize,
3393 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3394 pf->offset_loaded, &os->rx_jabber,
3396 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3397 I40E_GLPRT_PTC64L(hw->port),
3398 pf->offset_loaded, &os->tx_size_64,
3400 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3401 I40E_GLPRT_PTC127L(hw->port),
3402 pf->offset_loaded, &os->tx_size_127,
3404 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3405 I40E_GLPRT_PTC255L(hw->port),
3406 pf->offset_loaded, &os->tx_size_255,
3408 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3409 I40E_GLPRT_PTC511L(hw->port),
3410 pf->offset_loaded, &os->tx_size_511,
3412 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3413 I40E_GLPRT_PTC1023L(hw->port),
3414 pf->offset_loaded, &os->tx_size_1023,
3416 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3417 I40E_GLPRT_PTC1522L(hw->port),
3418 pf->offset_loaded, &os->tx_size_1522,
3420 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3421 I40E_GLPRT_PTC9522L(hw->port),
3422 pf->offset_loaded, &os->tx_size_big,
3424 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3426 &os->fd_sb_match, &ns->fd_sb_match);
3427 /* GLPRT_MSPDC not supported */
3428 /* GLPRT_XEC not supported */
3430 pf->offset_loaded = true;
3433 i40e_update_vsi_stats(pf->main_vsi);
3436 /* Get all statistics of a port */
3438 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3440 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3441 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3442 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3443 struct i40e_vsi *vsi;
3446 /* call read registers - updates values, now write them to struct */
3447 i40e_read_stats_registers(pf, hw);
3449 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3450 pf->main_vsi->eth_stats.rx_multicast +
3451 pf->main_vsi->eth_stats.rx_broadcast -
3452 pf->main_vsi->eth_stats.rx_discards;
3453 stats->opackets = ns->eth.tx_unicast +
3454 ns->eth.tx_multicast +
3455 ns->eth.tx_broadcast;
3456 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
3457 stats->obytes = ns->eth.tx_bytes;
3458 stats->oerrors = ns->eth.tx_errors +
3459 pf->main_vsi->eth_stats.tx_errors;
3462 stats->imissed = ns->eth.rx_discards +
3463 pf->main_vsi->eth_stats.rx_discards;
3464 stats->ierrors = ns->crc_errors +
3465 ns->rx_length_errors + ns->rx_undersize +
3466 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3469 for (i = 0; i < pf->vf_num; i++) {
3470 vsi = pf->vfs[i].vsi;
3471 i40e_update_vsi_stats(vsi);
3473 stats->ipackets += (vsi->eth_stats.rx_unicast +
3474 vsi->eth_stats.rx_multicast +
3475 vsi->eth_stats.rx_broadcast -
3476 vsi->eth_stats.rx_discards);
3477 stats->ibytes += vsi->eth_stats.rx_bytes;
3478 stats->oerrors += vsi->eth_stats.tx_errors;
3479 stats->imissed += vsi->eth_stats.rx_discards;
3483 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3484 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3485 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3486 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3487 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3488 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3489 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3490 ns->eth.rx_unknown_protocol);
3491 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3492 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3493 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3494 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3495 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3496 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3498 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3499 ns->tx_dropped_link_down);
3500 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3501 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3503 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3504 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3505 ns->mac_local_faults);
3506 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3507 ns->mac_remote_faults);
3508 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3509 ns->rx_length_errors);
3510 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3511 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3512 for (i = 0; i < 8; i++) {
3513 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3514 i, ns->priority_xon_rx[i]);
3515 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3516 i, ns->priority_xoff_rx[i]);
3518 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3519 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3520 for (i = 0; i < 8; i++) {
3521 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3522 i, ns->priority_xon_tx[i]);
3523 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3524 i, ns->priority_xoff_tx[i]);
3525 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3526 i, ns->priority_xon_2_xoff[i]);
3528 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3529 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3530 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3531 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3532 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3533 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3534 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3535 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3536 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3537 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3538 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3539 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3540 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3541 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3542 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3543 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3544 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3545 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3546 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3547 ns->mac_short_packet_dropped);
3548 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3549 ns->checksum_error);
3550 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3551 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3555 /* Reset the statistics */
3557 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3559 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3560 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3562 /* Mark PF and VSI stats to update the offset, aka "reset" */
3563 pf->offset_loaded = false;
3565 pf->main_vsi->offset_loaded = false;
3567 /* read the stats, reading current register values into offset */
3568 i40e_read_stats_registers(pf, hw);
3574 i40e_xstats_calc_num(void)
3576 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3577 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3578 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3581 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3582 struct rte_eth_xstat_name *xstats_names,
3583 __rte_unused unsigned limit)
3588 if (xstats_names == NULL)
3589 return i40e_xstats_calc_num();
3591 /* Note: limit checked in rte_eth_xstats_names() */
3593 /* Get stats from i40e_eth_stats struct */
3594 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3595 strlcpy(xstats_names[count].name,
3596 rte_i40e_stats_strings[i].name,
3597 sizeof(xstats_names[count].name));
3601 /* Get individiual stats from i40e_hw_port struct */
3602 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3603 strlcpy(xstats_names[count].name,
3604 rte_i40e_hw_port_strings[i].name,
3605 sizeof(xstats_names[count].name));
3609 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3610 for (prio = 0; prio < 8; prio++) {
3611 snprintf(xstats_names[count].name,
3612 sizeof(xstats_names[count].name),
3613 "rx_priority%u_%s", prio,
3614 rte_i40e_rxq_prio_strings[i].name);
3619 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3620 for (prio = 0; prio < 8; prio++) {
3621 snprintf(xstats_names[count].name,
3622 sizeof(xstats_names[count].name),
3623 "tx_priority%u_%s", prio,
3624 rte_i40e_txq_prio_strings[i].name);
3632 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3635 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3636 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3637 unsigned i, count, prio;
3638 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3640 count = i40e_xstats_calc_num();
3644 i40e_read_stats_registers(pf, hw);
3651 /* Get stats from i40e_eth_stats struct */
3652 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3653 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3654 rte_i40e_stats_strings[i].offset);
3655 xstats[count].id = count;
3659 /* Get individiual stats from i40e_hw_port struct */
3660 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3661 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3662 rte_i40e_hw_port_strings[i].offset);
3663 xstats[count].id = count;
3667 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3668 for (prio = 0; prio < 8; prio++) {
3669 xstats[count].value =
3670 *(uint64_t *)(((char *)hw_stats) +
3671 rte_i40e_rxq_prio_strings[i].offset +
3672 (sizeof(uint64_t) * prio));
3673 xstats[count].id = count;
3678 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3679 for (prio = 0; prio < 8; prio++) {
3680 xstats[count].value =
3681 *(uint64_t *)(((char *)hw_stats) +
3682 rte_i40e_txq_prio_strings[i].offset +
3683 (sizeof(uint64_t) * prio));
3684 xstats[count].id = count;
3693 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3695 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3701 full_ver = hw->nvm.oem_ver;
3702 ver = (u8)(full_ver >> 24);
3703 build = (u16)((full_ver >> 8) & 0xffff);
3704 patch = (u8)(full_ver & 0xff);
3706 ret = snprintf(fw_version, fw_size,
3707 "%d.%d%d 0x%08x %d.%d.%d",
3708 ((hw->nvm.version >> 12) & 0xf),
3709 ((hw->nvm.version >> 4) & 0xff),
3710 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3713 ret += 1; /* add the size of '\0' */
3714 if (fw_size < (u32)ret)
3721 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3722 * the Rx data path does not hang if the FW LLDP is stopped.
3723 * return true if lldp need to stop
3724 * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3727 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3730 char ver_str[64] = {0};
3731 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3733 i40e_fw_version_get(dev, ver_str, 64);
3734 nvm_ver = atof(ver_str);
3735 if ((hw->mac.type == I40E_MAC_X722 ||
3736 hw->mac.type == I40E_MAC_X722_VF) &&
3737 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3739 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3746 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3748 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3749 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3750 struct i40e_vsi *vsi = pf->main_vsi;
3751 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3753 dev_info->max_rx_queues = vsi->nb_qps;
3754 dev_info->max_tx_queues = vsi->nb_qps;
3755 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3756 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3757 dev_info->max_mac_addrs = vsi->max_macaddrs;
3758 dev_info->max_vfs = pci_dev->max_vfs;
3759 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3760 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3761 dev_info->rx_queue_offload_capa = 0;
3762 dev_info->rx_offload_capa =
3763 DEV_RX_OFFLOAD_VLAN_STRIP |
3764 DEV_RX_OFFLOAD_QINQ_STRIP |
3765 DEV_RX_OFFLOAD_IPV4_CKSUM |
3766 DEV_RX_OFFLOAD_UDP_CKSUM |
3767 DEV_RX_OFFLOAD_TCP_CKSUM |
3768 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3769 DEV_RX_OFFLOAD_KEEP_CRC |
3770 DEV_RX_OFFLOAD_SCATTER |
3771 DEV_RX_OFFLOAD_VLAN_EXTEND |
3772 DEV_RX_OFFLOAD_VLAN_FILTER |
3773 DEV_RX_OFFLOAD_JUMBO_FRAME |
3774 DEV_RX_OFFLOAD_RSS_HASH;
3776 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3777 dev_info->tx_offload_capa =
3778 DEV_TX_OFFLOAD_VLAN_INSERT |
3779 DEV_TX_OFFLOAD_QINQ_INSERT |
3780 DEV_TX_OFFLOAD_IPV4_CKSUM |
3781 DEV_TX_OFFLOAD_UDP_CKSUM |
3782 DEV_TX_OFFLOAD_TCP_CKSUM |
3783 DEV_TX_OFFLOAD_SCTP_CKSUM |
3784 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3785 DEV_TX_OFFLOAD_TCP_TSO |
3786 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3787 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3788 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3789 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3790 DEV_TX_OFFLOAD_MULTI_SEGS |
3791 dev_info->tx_queue_offload_capa;
3792 dev_info->dev_capa =
3793 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3794 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3796 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3798 dev_info->reta_size = pf->hash_lut_size;
3799 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3801 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3803 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3804 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3805 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3807 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3812 dev_info->default_txconf = (struct rte_eth_txconf) {
3814 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3815 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3816 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3818 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3819 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3823 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3824 .nb_max = I40E_MAX_RING_DESC,
3825 .nb_min = I40E_MIN_RING_DESC,
3826 .nb_align = I40E_ALIGN_RING_DESC,
3829 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3830 .nb_max = I40E_MAX_RING_DESC,
3831 .nb_min = I40E_MIN_RING_DESC,
3832 .nb_align = I40E_ALIGN_RING_DESC,
3833 .nb_seg_max = I40E_TX_MAX_SEG,
3834 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3837 if (pf->flags & I40E_FLAG_VMDQ) {
3838 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3839 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3840 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3841 pf->max_nb_vmdq_vsi;
3842 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3843 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3844 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3847 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3849 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3850 dev_info->default_rxportconf.nb_queues = 2;
3851 dev_info->default_txportconf.nb_queues = 2;
3852 if (dev->data->nb_rx_queues == 1)
3853 dev_info->default_rxportconf.ring_size = 2048;
3855 dev_info->default_rxportconf.ring_size = 1024;
3856 if (dev->data->nb_tx_queues == 1)
3857 dev_info->default_txportconf.ring_size = 1024;
3859 dev_info->default_txportconf.ring_size = 512;
3861 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3863 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3864 dev_info->default_rxportconf.nb_queues = 1;
3865 dev_info->default_txportconf.nb_queues = 1;
3866 dev_info->default_rxportconf.ring_size = 256;
3867 dev_info->default_txportconf.ring_size = 256;
3870 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3871 dev_info->default_rxportconf.nb_queues = 1;
3872 dev_info->default_txportconf.nb_queues = 1;
3873 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3874 dev_info->default_rxportconf.ring_size = 512;
3875 dev_info->default_txportconf.ring_size = 256;
3877 dev_info->default_rxportconf.ring_size = 256;
3878 dev_info->default_txportconf.ring_size = 256;
3881 dev_info->default_rxportconf.burst_size = 32;
3882 dev_info->default_txportconf.burst_size = 32;
3888 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3890 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3891 struct i40e_vsi *vsi = pf->main_vsi;
3892 PMD_INIT_FUNC_TRACE();
3895 return i40e_vsi_add_vlan(vsi, vlan_id);
3897 return i40e_vsi_delete_vlan(vsi, vlan_id);
3901 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3902 enum rte_vlan_type vlan_type,
3903 uint16_t tpid, int qinq)
3905 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3908 uint16_t reg_id = 3;
3912 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3916 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3918 if (ret != I40E_SUCCESS) {
3920 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3925 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3928 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3929 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3930 if (reg_r == reg_w) {
3931 PMD_DRV_LOG(DEBUG, "No need to write");
3935 ret = i40e_aq_debug_write_global_register(hw,
3936 I40E_GL_SWT_L2TAGCTRL(reg_id),
3938 if (ret != I40E_SUCCESS) {
3940 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3945 "Global register 0x%08x is changed with value 0x%08x",
3946 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3952 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3953 enum rte_vlan_type vlan_type,
3956 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3957 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3958 int qinq = dev->data->dev_conf.rxmode.offloads &
3959 DEV_RX_OFFLOAD_VLAN_EXTEND;
3962 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3963 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3964 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3966 "Unsupported vlan type.");
3970 if (pf->support_multi_driver) {
3971 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3975 /* 802.1ad frames ability is added in NVM API 1.7*/
3976 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3978 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3979 hw->first_tag = rte_cpu_to_le_16(tpid);
3980 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3981 hw->second_tag = rte_cpu_to_le_16(tpid);
3983 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3984 hw->second_tag = rte_cpu_to_le_16(tpid);
3986 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3987 if (ret != I40E_SUCCESS) {
3989 "Set switch config failed aq_err: %d",
3990 hw->aq.asq_last_status);
3994 /* If NVM API < 1.7, keep the register setting */
3995 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
4001 /* Configure outer vlan stripping on or off in QinQ mode */
4003 i40e_vsi_config_outer_vlan_stripping(struct i40e_vsi *vsi, bool on)
4005 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4006 int ret = I40E_SUCCESS;
4009 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
4010 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
4014 /* Configure for outer VLAN RX stripping */
4015 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
4018 reg |= I40E_VSI_TSR_QINQ_STRIP;
4020 reg &= ~I40E_VSI_TSR_QINQ_STRIP;
4022 ret = i40e_aq_debug_write_register(hw,
4023 I40E_VSI_TSR(vsi->vsi_id),
4026 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
4028 return I40E_ERR_CONFIG;
4035 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4037 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4038 struct i40e_vsi *vsi = pf->main_vsi;
4039 struct rte_eth_rxmode *rxmode;
4041 rxmode = &dev->data->dev_conf.rxmode;
4042 if (mask & ETH_VLAN_FILTER_MASK) {
4043 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4044 i40e_vsi_config_vlan_filter(vsi, TRUE);
4046 i40e_vsi_config_vlan_filter(vsi, FALSE);
4049 if (mask & ETH_VLAN_STRIP_MASK) {
4050 /* Enable or disable VLAN stripping */
4051 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4052 i40e_vsi_config_vlan_stripping(vsi, TRUE);
4054 i40e_vsi_config_vlan_stripping(vsi, FALSE);
4057 if (mask & ETH_VLAN_EXTEND_MASK) {
4058 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
4059 i40e_vsi_config_double_vlan(vsi, TRUE);
4060 /* Set global registers with default ethertype. */
4061 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
4062 RTE_ETHER_TYPE_VLAN);
4063 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
4064 RTE_ETHER_TYPE_VLAN);
4067 i40e_vsi_config_double_vlan(vsi, FALSE);
4070 if (mask & ETH_QINQ_STRIP_MASK) {
4071 /* Enable or disable outer VLAN stripping */
4072 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP)
4073 i40e_vsi_config_outer_vlan_stripping(vsi, TRUE);
4075 i40e_vsi_config_outer_vlan_stripping(vsi, FALSE);
4082 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
4083 __rte_unused uint16_t queue,
4084 __rte_unused int on)
4086 PMD_INIT_FUNC_TRACE();
4090 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4092 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4093 struct i40e_vsi *vsi = pf->main_vsi;
4094 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
4095 struct i40e_vsi_vlan_pvid_info info;
4097 memset(&info, 0, sizeof(info));
4100 info.config.pvid = pvid;
4102 info.config.reject.tagged =
4103 data->dev_conf.txmode.hw_vlan_reject_tagged;
4104 info.config.reject.untagged =
4105 data->dev_conf.txmode.hw_vlan_reject_untagged;
4108 return i40e_vsi_vlan_pvid_set(vsi, &info);
4112 i40e_dev_led_on(struct rte_eth_dev *dev)
4114 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4115 uint32_t mode = i40e_led_get(hw);
4118 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
4124 i40e_dev_led_off(struct rte_eth_dev *dev)
4126 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4127 uint32_t mode = i40e_led_get(hw);
4130 i40e_led_set(hw, 0, false);
4136 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4138 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4139 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4141 fc_conf->pause_time = pf->fc_conf.pause_time;
4143 /* read out from register, in case they are modified by other port */
4144 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
4145 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
4146 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
4147 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
4149 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
4150 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
4152 /* Return current mode according to actual setting*/
4153 switch (hw->fc.current_mode) {
4155 fc_conf->mode = RTE_FC_FULL;
4157 case I40E_FC_TX_PAUSE:
4158 fc_conf->mode = RTE_FC_TX_PAUSE;
4160 case I40E_FC_RX_PAUSE:
4161 fc_conf->mode = RTE_FC_RX_PAUSE;
4165 fc_conf->mode = RTE_FC_NONE;
4172 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4174 uint32_t mflcn_reg, fctrl_reg, reg;
4175 uint32_t max_high_water;
4176 uint8_t i, aq_failure;
4180 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4181 [RTE_FC_NONE] = I40E_FC_NONE,
4182 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4183 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4184 [RTE_FC_FULL] = I40E_FC_FULL
4187 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4189 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4190 if ((fc_conf->high_water > max_high_water) ||
4191 (fc_conf->high_water < fc_conf->low_water)) {
4193 "Invalid high/low water setup value in KB, High_water must be <= %d.",
4198 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4199 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4200 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4202 pf->fc_conf.pause_time = fc_conf->pause_time;
4203 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4204 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4206 PMD_INIT_FUNC_TRACE();
4208 /* All the link flow control related enable/disable register
4209 * configuration is handle by the F/W
4211 err = i40e_set_fc(hw, &aq_failure, true);
4215 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4216 /* Configure flow control refresh threshold,
4217 * the value for stat_tx_pause_refresh_timer[8]
4218 * is used for global pause operation.
4222 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4223 pf->fc_conf.pause_time);
4225 /* configure the timer value included in transmitted pause
4227 * the value for stat_tx_pause_quanta[8] is used for global
4230 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4231 pf->fc_conf.pause_time);
4233 fctrl_reg = I40E_READ_REG(hw,
4234 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4236 if (fc_conf->mac_ctrl_frame_fwd != 0)
4237 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4239 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4241 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4244 /* Configure pause time (2 TCs per register) */
4245 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4246 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4247 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4249 /* Configure flow control refresh threshold value */
4250 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4251 pf->fc_conf.pause_time / 2);
4253 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4255 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4256 *depending on configuration
4258 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4259 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4260 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4262 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4263 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4266 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4269 if (!pf->support_multi_driver) {
4270 /* config water marker both based on the packets and bytes */
4271 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4272 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4273 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4274 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4275 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4276 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4277 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4278 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4280 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4281 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4285 "Water marker configuration is not supported.");
4288 I40E_WRITE_FLUSH(hw);
4294 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4295 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4297 PMD_INIT_FUNC_TRACE();
4302 /* Add a MAC address, and update filters */
4304 i40e_macaddr_add(struct rte_eth_dev *dev,
4305 struct rte_ether_addr *mac_addr,
4306 __rte_unused uint32_t index,
4309 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4310 struct i40e_mac_filter_info mac_filter;
4311 struct i40e_vsi *vsi;
4312 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4315 /* If VMDQ not enabled or configured, return */
4316 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4317 !pf->nb_cfg_vmdq_vsi)) {
4318 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4319 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4324 if (pool > pf->nb_cfg_vmdq_vsi) {
4325 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4326 pool, pf->nb_cfg_vmdq_vsi);
4330 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4331 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4332 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4334 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4339 vsi = pf->vmdq[pool - 1].vsi;
4341 ret = i40e_vsi_add_mac(vsi, &mac_filter);
4342 if (ret != I40E_SUCCESS) {
4343 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4349 /* Remove a MAC address, and update filters */
4351 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4353 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4354 struct i40e_vsi *vsi;
4355 struct rte_eth_dev_data *data = dev->data;
4356 struct rte_ether_addr *macaddr;
4361 macaddr = &(data->mac_addrs[index]);
4363 pool_sel = dev->data->mac_pool_sel[index];
4365 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4366 if (pool_sel & (1ULL << i)) {
4370 /* No VMDQ pool enabled or configured */
4371 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4372 (i > pf->nb_cfg_vmdq_vsi)) {
4374 "No VMDQ pool enabled/configured");
4377 vsi = pf->vmdq[i - 1].vsi;
4379 ret = i40e_vsi_delete_mac(vsi, macaddr);
4382 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4389 /* Set perfect match or hash match of MAC and VLAN for a VF */
4391 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4392 struct rte_eth_mac_filter *filter,
4396 struct i40e_mac_filter_info mac_filter;
4397 struct rte_ether_addr old_mac;
4398 struct rte_ether_addr *new_mac;
4399 struct i40e_pf_vf *vf = NULL;
4404 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4407 hw = I40E_PF_TO_HW(pf);
4409 if (filter == NULL) {
4410 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4414 new_mac = &filter->mac_addr;
4416 if (rte_is_zero_ether_addr(new_mac)) {
4417 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4421 vf_id = filter->dst_id;
4423 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4424 PMD_DRV_LOG(ERR, "Invalid argument.");
4427 vf = &pf->vfs[vf_id];
4429 if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4430 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4435 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4436 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4437 RTE_ETHER_ADDR_LEN);
4438 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4439 RTE_ETHER_ADDR_LEN);
4441 mac_filter.filter_type = filter->filter_type;
4442 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4443 if (ret != I40E_SUCCESS) {
4444 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4447 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4449 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4450 RTE_ETHER_ADDR_LEN);
4451 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4452 if (ret != I40E_SUCCESS) {
4453 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4457 /* Clear device address as it has been removed */
4458 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4459 memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4465 /* MAC filter handle */
4467 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4470 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4471 struct rte_eth_mac_filter *filter;
4472 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4473 int ret = I40E_NOT_SUPPORTED;
4475 filter = (struct rte_eth_mac_filter *)(arg);
4477 switch (filter_op) {
4478 case RTE_ETH_FILTER_NOP:
4481 case RTE_ETH_FILTER_ADD:
4482 i40e_pf_disable_irq0(hw);
4484 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4485 i40e_pf_enable_irq0(hw);
4487 case RTE_ETH_FILTER_DELETE:
4488 i40e_pf_disable_irq0(hw);
4490 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4491 i40e_pf_enable_irq0(hw);
4494 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4495 ret = I40E_ERR_PARAM;
4503 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4505 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4506 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4513 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4514 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4515 vsi->type != I40E_VSI_SRIOV,
4518 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4522 uint32_t *lut_dw = (uint32_t *)lut;
4523 uint16_t i, lut_size_dw = lut_size / 4;
4525 if (vsi->type == I40E_VSI_SRIOV) {
4526 for (i = 0; i <= lut_size_dw; i++) {
4527 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4528 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4531 for (i = 0; i < lut_size_dw; i++)
4532 lut_dw[i] = I40E_READ_REG(hw,
4541 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4550 pf = I40E_VSI_TO_PF(vsi);
4551 hw = I40E_VSI_TO_HW(vsi);
4553 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4554 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4555 vsi->type != I40E_VSI_SRIOV,
4558 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4562 uint32_t *lut_dw = (uint32_t *)lut;
4563 uint16_t i, lut_size_dw = lut_size / 4;
4565 if (vsi->type == I40E_VSI_SRIOV) {
4566 for (i = 0; i < lut_size_dw; i++)
4569 I40E_VFQF_HLUT1(i, vsi->user_param),
4572 for (i = 0; i < lut_size_dw; i++)
4573 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4576 I40E_WRITE_FLUSH(hw);
4583 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4584 struct rte_eth_rss_reta_entry64 *reta_conf,
4587 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4588 uint16_t i, lut_size = pf->hash_lut_size;
4589 uint16_t idx, shift;
4593 if (reta_size != lut_size ||
4594 reta_size > ETH_RSS_RETA_SIZE_512) {
4596 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4597 reta_size, lut_size);
4601 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4603 PMD_DRV_LOG(ERR, "No memory can be allocated");
4606 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4609 for (i = 0; i < reta_size; i++) {
4610 idx = i / RTE_RETA_GROUP_SIZE;
4611 shift = i % RTE_RETA_GROUP_SIZE;
4612 if (reta_conf[idx].mask & (1ULL << shift))
4613 lut[i] = reta_conf[idx].reta[shift];
4615 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4617 pf->adapter->rss_reta_updated = 1;
4626 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4627 struct rte_eth_rss_reta_entry64 *reta_conf,
4630 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4631 uint16_t i, lut_size = pf->hash_lut_size;
4632 uint16_t idx, shift;
4636 if (reta_size != lut_size ||
4637 reta_size > ETH_RSS_RETA_SIZE_512) {
4639 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4640 reta_size, lut_size);
4644 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4646 PMD_DRV_LOG(ERR, "No memory can be allocated");
4650 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4653 for (i = 0; i < reta_size; i++) {
4654 idx = i / RTE_RETA_GROUP_SIZE;
4655 shift = i % RTE_RETA_GROUP_SIZE;
4656 if (reta_conf[idx].mask & (1ULL << shift))
4657 reta_conf[idx].reta[shift] = lut[i];
4667 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4668 * @hw: pointer to the HW structure
4669 * @mem: pointer to mem struct to fill out
4670 * @size: size of memory requested
4671 * @alignment: what to align the allocation to
4673 enum i40e_status_code
4674 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4675 struct i40e_dma_mem *mem,
4679 const struct rte_memzone *mz = NULL;
4680 char z_name[RTE_MEMZONE_NAMESIZE];
4683 return I40E_ERR_PARAM;
4685 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4686 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4687 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4689 return I40E_ERR_NO_MEMORY;
4694 mem->zone = (const void *)mz;
4696 "memzone %s allocated with physical address: %"PRIu64,
4699 return I40E_SUCCESS;
4703 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4704 * @hw: pointer to the HW structure
4705 * @mem: ptr to mem struct to free
4707 enum i40e_status_code
4708 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4709 struct i40e_dma_mem *mem)
4712 return I40E_ERR_PARAM;
4715 "memzone %s to be freed with physical address: %"PRIu64,
4716 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4717 rte_memzone_free((const struct rte_memzone *)mem->zone);
4722 return I40E_SUCCESS;
4726 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4727 * @hw: pointer to the HW structure
4728 * @mem: pointer to mem struct to fill out
4729 * @size: size of memory requested
4731 enum i40e_status_code
4732 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4733 struct i40e_virt_mem *mem,
4737 return I40E_ERR_PARAM;
4740 mem->va = rte_zmalloc("i40e", size, 0);
4743 return I40E_SUCCESS;
4745 return I40E_ERR_NO_MEMORY;
4749 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4750 * @hw: pointer to the HW structure
4751 * @mem: pointer to mem struct to free
4753 enum i40e_status_code
4754 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4755 struct i40e_virt_mem *mem)
4758 return I40E_ERR_PARAM;
4763 return I40E_SUCCESS;
4767 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4769 rte_spinlock_init(&sp->spinlock);
4773 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4775 rte_spinlock_lock(&sp->spinlock);
4779 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4781 rte_spinlock_unlock(&sp->spinlock);
4785 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4791 * Get the hardware capabilities, which will be parsed
4792 * and saved into struct i40e_hw.
4795 i40e_get_cap(struct i40e_hw *hw)
4797 struct i40e_aqc_list_capabilities_element_resp *buf;
4798 uint16_t len, size = 0;
4801 /* Calculate a huge enough buff for saving response data temporarily */
4802 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4803 I40E_MAX_CAP_ELE_NUM;
4804 buf = rte_zmalloc("i40e", len, 0);
4806 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4807 return I40E_ERR_NO_MEMORY;
4810 /* Get, parse the capabilities and save it to hw */
4811 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4812 i40e_aqc_opc_list_func_capabilities, NULL);
4813 if (ret != I40E_SUCCESS)
4814 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4816 /* Free the temporary buffer after being used */
4822 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4824 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4832 pf = (struct i40e_pf *)opaque;
4836 num = strtoul(value, &end, 0);
4837 if (errno != 0 || end == value || *end != 0) {
4838 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4839 "kept the value = %hu", value, pf->vf_nb_qp_max);
4843 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4844 pf->vf_nb_qp_max = (uint16_t)num;
4846 /* here return 0 to make next valid same argument work */
4847 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4848 "power of 2 and equal or less than 16 !, Now it is "
4849 "kept the value = %hu", num, pf->vf_nb_qp_max);
4854 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4856 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4857 struct rte_kvargs *kvlist;
4860 /* set default queue number per VF as 4 */
4861 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4863 if (dev->device->devargs == NULL)
4866 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4870 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4871 if (!kvargs_count) {
4872 rte_kvargs_free(kvlist);
4876 if (kvargs_count > 1)
4877 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4878 "the first invalid or last valid one is used !",
4879 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4881 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4882 i40e_pf_parse_vf_queue_number_handler, pf);
4884 rte_kvargs_free(kvlist);
4890 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4892 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4893 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4894 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4895 uint16_t qp_count = 0, vsi_count = 0;
4897 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4898 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4902 i40e_pf_config_vf_rxq_number(dev);
4904 /* Add the parameter init for LFC */
4905 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4906 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4907 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4909 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4910 pf->max_num_vsi = hw->func_caps.num_vsis;
4911 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4912 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4914 /* FDir queue/VSI allocation */
4915 pf->fdir_qp_offset = 0;
4916 if (hw->func_caps.fd) {
4917 pf->flags |= I40E_FLAG_FDIR;
4918 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4920 pf->fdir_nb_qps = 0;
4922 qp_count += pf->fdir_nb_qps;
4925 /* LAN queue/VSI allocation */
4926 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4927 if (!hw->func_caps.rss) {
4930 pf->flags |= I40E_FLAG_RSS;
4931 if (hw->mac.type == I40E_MAC_X722)
4932 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4933 pf->lan_nb_qps = pf->lan_nb_qp_max;
4935 qp_count += pf->lan_nb_qps;
4938 /* VF queue/VSI allocation */
4939 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4940 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4941 pf->flags |= I40E_FLAG_SRIOV;
4942 pf->vf_nb_qps = pf->vf_nb_qp_max;
4943 pf->vf_num = pci_dev->max_vfs;
4945 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4946 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4951 qp_count += pf->vf_nb_qps * pf->vf_num;
4952 vsi_count += pf->vf_num;
4954 /* VMDq queue/VSI allocation */
4955 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4956 pf->vmdq_nb_qps = 0;
4957 pf->max_nb_vmdq_vsi = 0;
4958 if (hw->func_caps.vmdq) {
4959 if (qp_count < hw->func_caps.num_tx_qp &&
4960 vsi_count < hw->func_caps.num_vsis) {
4961 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4962 qp_count) / pf->vmdq_nb_qp_max;
4964 /* Limit the maximum number of VMDq vsi to the maximum
4965 * ethdev can support
4967 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4968 hw->func_caps.num_vsis - vsi_count);
4969 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4971 if (pf->max_nb_vmdq_vsi) {
4972 pf->flags |= I40E_FLAG_VMDQ;
4973 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4975 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4976 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4977 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4980 "No enough queues left for VMDq");
4983 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4986 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4987 vsi_count += pf->max_nb_vmdq_vsi;
4989 if (hw->func_caps.dcb)
4990 pf->flags |= I40E_FLAG_DCB;
4992 if (qp_count > hw->func_caps.num_tx_qp) {
4994 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4995 qp_count, hw->func_caps.num_tx_qp);
4998 if (vsi_count > hw->func_caps.num_vsis) {
5000 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
5001 vsi_count, hw->func_caps.num_vsis);
5009 i40e_pf_get_switch_config(struct i40e_pf *pf)
5011 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5012 struct i40e_aqc_get_switch_config_resp *switch_config;
5013 struct i40e_aqc_switch_config_element_resp *element;
5014 uint16_t start_seid = 0, num_reported;
5017 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
5018 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
5019 if (!switch_config) {
5020 PMD_DRV_LOG(ERR, "Failed to allocated memory");
5024 /* Get the switch configurations */
5025 ret = i40e_aq_get_switch_config(hw, switch_config,
5026 I40E_AQ_LARGE_BUF, &start_seid, NULL);
5027 if (ret != I40E_SUCCESS) {
5028 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
5031 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
5032 if (num_reported != 1) { /* The number should be 1 */
5033 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
5037 /* Parse the switch configuration elements */
5038 element = &(switch_config->element[0]);
5039 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
5040 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
5041 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
5043 PMD_DRV_LOG(INFO, "Unknown element type");
5046 rte_free(switch_config);
5052 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
5055 struct pool_entry *entry;
5057 if (pool == NULL || num == 0)
5060 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
5061 if (entry == NULL) {
5062 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
5066 /* queue heap initialize */
5067 pool->num_free = num;
5068 pool->num_alloc = 0;
5070 LIST_INIT(&pool->alloc_list);
5071 LIST_INIT(&pool->free_list);
5073 /* Initialize element */
5077 LIST_INSERT_HEAD(&pool->free_list, entry, next);
5082 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
5084 struct pool_entry *entry, *next_entry;
5089 for (entry = LIST_FIRST(&pool->alloc_list);
5090 entry && (next_entry = LIST_NEXT(entry, next), 1);
5091 entry = next_entry) {
5092 LIST_REMOVE(entry, next);
5096 for (entry = LIST_FIRST(&pool->free_list);
5097 entry && (next_entry = LIST_NEXT(entry, next), 1);
5098 entry = next_entry) {
5099 LIST_REMOVE(entry, next);
5104 pool->num_alloc = 0;
5106 LIST_INIT(&pool->alloc_list);
5107 LIST_INIT(&pool->free_list);
5111 i40e_res_pool_free(struct i40e_res_pool_info *pool,
5114 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
5115 uint32_t pool_offset;
5120 PMD_DRV_LOG(ERR, "Invalid parameter");
5124 pool_offset = base - pool->base;
5125 /* Lookup in alloc list */
5126 LIST_FOREACH(entry, &pool->alloc_list, next) {
5127 if (entry->base == pool_offset) {
5128 valid_entry = entry;
5129 LIST_REMOVE(entry, next);
5134 /* Not find, return */
5135 if (valid_entry == NULL) {
5136 PMD_DRV_LOG(ERR, "Failed to find entry");
5141 * Found it, move it to free list and try to merge.
5142 * In order to make merge easier, always sort it by qbase.
5143 * Find adjacent prev and last entries.
5146 LIST_FOREACH(entry, &pool->free_list, next) {
5147 if (entry->base > valid_entry->base) {
5155 len = valid_entry->len;
5156 /* Try to merge with next one*/
5158 /* Merge with next one */
5159 if (valid_entry->base + len == next->base) {
5160 next->base = valid_entry->base;
5162 rte_free(valid_entry);
5169 /* Merge with previous one */
5170 if (prev->base + prev->len == valid_entry->base) {
5172 /* If it merge with next one, remove next node */
5174 LIST_REMOVE(valid_entry, next);
5175 rte_free(valid_entry);
5178 rte_free(valid_entry);
5185 /* Not find any entry to merge, insert */
5188 LIST_INSERT_AFTER(prev, valid_entry, next);
5189 else if (next != NULL)
5190 LIST_INSERT_BEFORE(next, valid_entry, next);
5191 else /* It's empty list, insert to head */
5192 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5195 pool->num_free += len;
5196 pool->num_alloc -= len;
5202 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5205 struct pool_entry *entry, *valid_entry;
5207 if (pool == NULL || num == 0) {
5208 PMD_DRV_LOG(ERR, "Invalid parameter");
5212 if (pool->num_free < num) {
5213 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5214 num, pool->num_free);
5219 /* Lookup in free list and find most fit one */
5220 LIST_FOREACH(entry, &pool->free_list, next) {
5221 if (entry->len >= num) {
5223 if (entry->len == num) {
5224 valid_entry = entry;
5227 if (valid_entry == NULL || valid_entry->len > entry->len)
5228 valid_entry = entry;
5232 /* Not find one to satisfy the request, return */
5233 if (valid_entry == NULL) {
5234 PMD_DRV_LOG(ERR, "No valid entry found");
5238 * The entry have equal queue number as requested,
5239 * remove it from alloc_list.
5241 if (valid_entry->len == num) {
5242 LIST_REMOVE(valid_entry, next);
5245 * The entry have more numbers than requested,
5246 * create a new entry for alloc_list and minus its
5247 * queue base and number in free_list.
5249 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5250 if (entry == NULL) {
5252 "Failed to allocate memory for resource pool");
5255 entry->base = valid_entry->base;
5257 valid_entry->base += num;
5258 valid_entry->len -= num;
5259 valid_entry = entry;
5262 /* Insert it into alloc list, not sorted */
5263 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5265 pool->num_free -= valid_entry->len;
5266 pool->num_alloc += valid_entry->len;
5268 return valid_entry->base + pool->base;
5272 * bitmap_is_subset - Check whether src2 is subset of src1
5275 bitmap_is_subset(uint8_t src1, uint8_t src2)
5277 return !((src1 ^ src2) & src2);
5280 static enum i40e_status_code
5281 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5283 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5285 /* If DCB is not supported, only default TC is supported */
5286 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5287 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5288 return I40E_NOT_SUPPORTED;
5291 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5293 "Enabled TC map 0x%x not applicable to HW support 0x%x",
5294 hw->func_caps.enabled_tcmap, enabled_tcmap);
5295 return I40E_NOT_SUPPORTED;
5297 return I40E_SUCCESS;
5301 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5302 struct i40e_vsi_vlan_pvid_info *info)
5305 struct i40e_vsi_context ctxt;
5306 uint8_t vlan_flags = 0;
5309 if (vsi == NULL || info == NULL) {
5310 PMD_DRV_LOG(ERR, "invalid parameters");
5311 return I40E_ERR_PARAM;
5315 vsi->info.pvid = info->config.pvid;
5317 * If insert pvid is enabled, only tagged pkts are
5318 * allowed to be sent out.
5320 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5321 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5324 if (info->config.reject.tagged == 0)
5325 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5327 if (info->config.reject.untagged == 0)
5328 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5330 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5331 I40E_AQ_VSI_PVLAN_MODE_MASK);
5332 vsi->info.port_vlan_flags |= vlan_flags;
5333 vsi->info.valid_sections =
5334 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5335 memset(&ctxt, 0, sizeof(ctxt));
5336 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5337 ctxt.seid = vsi->seid;
5339 hw = I40E_VSI_TO_HW(vsi);
5340 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5341 if (ret != I40E_SUCCESS)
5342 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5348 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5350 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5352 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5354 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5355 if (ret != I40E_SUCCESS)
5359 PMD_DRV_LOG(ERR, "seid not valid");
5363 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5364 tc_bw_data.tc_valid_bits = enabled_tcmap;
5365 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5366 tc_bw_data.tc_bw_credits[i] =
5367 (enabled_tcmap & (1 << i)) ? 1 : 0;
5369 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5370 if (ret != I40E_SUCCESS) {
5371 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5375 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5376 sizeof(vsi->info.qs_handle));
5377 return I40E_SUCCESS;
5380 static enum i40e_status_code
5381 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5382 struct i40e_aqc_vsi_properties_data *info,
5383 uint8_t enabled_tcmap)
5385 enum i40e_status_code ret;
5386 int i, total_tc = 0;
5387 uint16_t qpnum_per_tc, bsf, qp_idx;
5389 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5390 if (ret != I40E_SUCCESS)
5393 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5394 if (enabled_tcmap & (1 << i))
5398 vsi->enabled_tc = enabled_tcmap;
5400 /* Number of queues per enabled TC */
5401 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5402 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5403 bsf = rte_bsf32(qpnum_per_tc);
5405 /* Adjust the queue number to actual queues that can be applied */
5406 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5407 vsi->nb_qps = qpnum_per_tc * total_tc;
5410 * Configure TC and queue mapping parameters, for enabled TC,
5411 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5412 * default queue will serve it.
5415 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5416 if (vsi->enabled_tc & (1 << i)) {
5417 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5418 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5419 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5420 qp_idx += qpnum_per_tc;
5422 info->tc_mapping[i] = 0;
5425 /* Associate queue number with VSI */
5426 if (vsi->type == I40E_VSI_SRIOV) {
5427 info->mapping_flags |=
5428 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5429 for (i = 0; i < vsi->nb_qps; i++)
5430 info->queue_mapping[i] =
5431 rte_cpu_to_le_16(vsi->base_queue + i);
5433 info->mapping_flags |=
5434 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5435 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5437 info->valid_sections |=
5438 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5440 return I40E_SUCCESS;
5444 i40e_veb_release(struct i40e_veb *veb)
5446 struct i40e_vsi *vsi;
5452 if (!TAILQ_EMPTY(&veb->head)) {
5453 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5456 /* associate_vsi field is NULL for floating VEB */
5457 if (veb->associate_vsi != NULL) {
5458 vsi = veb->associate_vsi;
5459 hw = I40E_VSI_TO_HW(vsi);
5461 vsi->uplink_seid = veb->uplink_seid;
5464 veb->associate_pf->main_vsi->floating_veb = NULL;
5465 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5468 i40e_aq_delete_element(hw, veb->seid, NULL);
5470 return I40E_SUCCESS;
5474 static struct i40e_veb *
5475 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5477 struct i40e_veb *veb;
5483 "veb setup failed, associated PF shouldn't null");
5486 hw = I40E_PF_TO_HW(pf);
5488 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5490 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5494 veb->associate_vsi = vsi;
5495 veb->associate_pf = pf;
5496 TAILQ_INIT(&veb->head);
5497 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5499 /* create floating veb if vsi is NULL */
5501 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5502 I40E_DEFAULT_TCMAP, false,
5503 &veb->seid, false, NULL);
5505 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5506 true, &veb->seid, false, NULL);
5509 if (ret != I40E_SUCCESS) {
5510 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5511 hw->aq.asq_last_status);
5514 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5516 /* get statistics index */
5517 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5518 &veb->stats_idx, NULL, NULL, NULL);
5519 if (ret != I40E_SUCCESS) {
5520 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5521 hw->aq.asq_last_status);
5524 /* Get VEB bandwidth, to be implemented */
5525 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5527 vsi->uplink_seid = veb->seid;
5536 i40e_vsi_release(struct i40e_vsi *vsi)
5540 struct i40e_vsi_list *vsi_list;
5543 struct i40e_mac_filter *f;
5544 uint16_t user_param;
5547 return I40E_SUCCESS;
5552 user_param = vsi->user_param;
5554 pf = I40E_VSI_TO_PF(vsi);
5555 hw = I40E_VSI_TO_HW(vsi);
5557 /* VSI has child to attach, release child first */
5559 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5560 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5563 i40e_veb_release(vsi->veb);
5566 if (vsi->floating_veb) {
5567 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5568 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5573 /* Remove all macvlan filters of the VSI */
5574 i40e_vsi_remove_all_macvlan_filter(vsi);
5575 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5578 if (vsi->type != I40E_VSI_MAIN &&
5579 ((vsi->type != I40E_VSI_SRIOV) ||
5580 !pf->floating_veb_list[user_param])) {
5581 /* Remove vsi from parent's sibling list */
5582 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5583 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5584 return I40E_ERR_PARAM;
5586 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5587 &vsi->sib_vsi_list, list);
5589 /* Remove all switch element of the VSI */
5590 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5591 if (ret != I40E_SUCCESS)
5592 PMD_DRV_LOG(ERR, "Failed to delete element");
5595 if ((vsi->type == I40E_VSI_SRIOV) &&
5596 pf->floating_veb_list[user_param]) {
5597 /* Remove vsi from parent's sibling list */
5598 if (vsi->parent_vsi == NULL ||
5599 vsi->parent_vsi->floating_veb == NULL) {
5600 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5601 return I40E_ERR_PARAM;
5603 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5604 &vsi->sib_vsi_list, list);
5606 /* Remove all switch element of the VSI */
5607 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5608 if (ret != I40E_SUCCESS)
5609 PMD_DRV_LOG(ERR, "Failed to delete element");
5612 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5614 if (vsi->type != I40E_VSI_SRIOV)
5615 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5618 return I40E_SUCCESS;
5622 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5624 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5625 struct i40e_aqc_remove_macvlan_element_data def_filter;
5626 struct i40e_mac_filter_info filter;
5629 if (vsi->type != I40E_VSI_MAIN)
5630 return I40E_ERR_CONFIG;
5631 memset(&def_filter, 0, sizeof(def_filter));
5632 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5634 def_filter.vlan_tag = 0;
5635 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5636 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5637 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5638 if (ret != I40E_SUCCESS) {
5639 struct i40e_mac_filter *f;
5640 struct rte_ether_addr *mac;
5643 "Cannot remove the default macvlan filter");
5644 /* It needs to add the permanent mac into mac list */
5645 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5647 PMD_DRV_LOG(ERR, "failed to allocate memory");
5648 return I40E_ERR_NO_MEMORY;
5650 mac = &f->mac_info.mac_addr;
5651 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5653 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5654 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5659 rte_memcpy(&filter.mac_addr,
5660 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5661 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5662 return i40e_vsi_add_mac(vsi, &filter);
5666 * i40e_vsi_get_bw_config - Query VSI BW Information
5667 * @vsi: the VSI to be queried
5669 * Returns 0 on success, negative value on failure
5671 static enum i40e_status_code
5672 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5674 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5675 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5676 struct i40e_hw *hw = &vsi->adapter->hw;
5681 memset(&bw_config, 0, sizeof(bw_config));
5682 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5683 if (ret != I40E_SUCCESS) {
5684 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5685 hw->aq.asq_last_status);
5689 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5690 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5691 &ets_sla_config, NULL);
5692 if (ret != I40E_SUCCESS) {
5694 "VSI failed to get TC bandwdith configuration %u",
5695 hw->aq.asq_last_status);
5699 /* store and print out BW info */
5700 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5701 vsi->bw_info.bw_max = bw_config.max_bw;
5702 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5703 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5704 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5705 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5707 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5708 vsi->bw_info.bw_ets_share_credits[i] =
5709 ets_sla_config.share_credits[i];
5710 vsi->bw_info.bw_ets_credits[i] =
5711 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5712 /* 4 bits per TC, 4th bit is reserved */
5713 vsi->bw_info.bw_ets_max[i] =
5714 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5715 RTE_LEN2MASK(3, uint8_t));
5716 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5717 vsi->bw_info.bw_ets_share_credits[i]);
5718 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5719 vsi->bw_info.bw_ets_credits[i]);
5720 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5721 vsi->bw_info.bw_ets_max[i]);
5724 return I40E_SUCCESS;
5727 /* i40e_enable_pf_lb
5728 * @pf: pointer to the pf structure
5730 * allow loopback on pf
5733 i40e_enable_pf_lb(struct i40e_pf *pf)
5735 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5736 struct i40e_vsi_context ctxt;
5739 /* Use the FW API if FW >= v5.0 */
5740 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5741 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5745 memset(&ctxt, 0, sizeof(ctxt));
5746 ctxt.seid = pf->main_vsi_seid;
5747 ctxt.pf_num = hw->pf_id;
5748 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5750 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5751 ret, hw->aq.asq_last_status);
5754 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5755 ctxt.info.valid_sections =
5756 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5757 ctxt.info.switch_id |=
5758 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5760 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5762 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5763 hw->aq.asq_last_status);
5768 i40e_vsi_setup(struct i40e_pf *pf,
5769 enum i40e_vsi_type type,
5770 struct i40e_vsi *uplink_vsi,
5771 uint16_t user_param)
5773 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5774 struct i40e_vsi *vsi;
5775 struct i40e_mac_filter_info filter;
5777 struct i40e_vsi_context ctxt;
5778 struct rte_ether_addr broadcast =
5779 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5781 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5782 uplink_vsi == NULL) {
5784 "VSI setup failed, VSI link shouldn't be NULL");
5788 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5790 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5795 * 1.type is not MAIN and uplink vsi is not NULL
5796 * If uplink vsi didn't setup VEB, create one first under veb field
5797 * 2.type is SRIOV and the uplink is NULL
5798 * If floating VEB is NULL, create one veb under floating veb field
5801 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5802 uplink_vsi->veb == NULL) {
5803 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5805 if (uplink_vsi->veb == NULL) {
5806 PMD_DRV_LOG(ERR, "VEB setup failed");
5809 /* set ALLOWLOOPBACk on pf, when veb is created */
5810 i40e_enable_pf_lb(pf);
5813 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5814 pf->main_vsi->floating_veb == NULL) {
5815 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5817 if (pf->main_vsi->floating_veb == NULL) {
5818 PMD_DRV_LOG(ERR, "VEB setup failed");
5823 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5825 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5828 TAILQ_INIT(&vsi->mac_list);
5830 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5831 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5832 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5833 vsi->user_param = user_param;
5834 vsi->vlan_anti_spoof_on = 0;
5835 vsi->vlan_filter_on = 0;
5836 /* Allocate queues */
5837 switch (vsi->type) {
5838 case I40E_VSI_MAIN :
5839 vsi->nb_qps = pf->lan_nb_qps;
5841 case I40E_VSI_SRIOV :
5842 vsi->nb_qps = pf->vf_nb_qps;
5844 case I40E_VSI_VMDQ2:
5845 vsi->nb_qps = pf->vmdq_nb_qps;
5848 vsi->nb_qps = pf->fdir_nb_qps;
5854 * The filter status descriptor is reported in rx queue 0,
5855 * while the tx queue for fdir filter programming has no
5856 * such constraints, can be non-zero queues.
5857 * To simplify it, choose FDIR vsi use queue 0 pair.
5858 * To make sure it will use queue 0 pair, queue allocation
5859 * need be done before this function is called
5861 if (type != I40E_VSI_FDIR) {
5862 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5864 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5868 vsi->base_queue = ret;
5870 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5872 /* VF has MSIX interrupt in VF range, don't allocate here */
5873 if (type == I40E_VSI_MAIN) {
5874 if (pf->support_multi_driver) {
5875 /* If support multi-driver, need to use INT0 instead of
5876 * allocating from msix pool. The Msix pool is init from
5877 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5878 * to 1 without calling i40e_res_pool_alloc.
5883 ret = i40e_res_pool_alloc(&pf->msix_pool,
5884 RTE_MIN(vsi->nb_qps,
5885 RTE_MAX_RXTX_INTR_VEC_ID));
5888 "VSI MAIN %d get heap failed %d",
5890 goto fail_queue_alloc;
5892 vsi->msix_intr = ret;
5893 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5894 RTE_MAX_RXTX_INTR_VEC_ID);
5896 } else if (type != I40E_VSI_SRIOV) {
5897 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5899 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5900 if (type != I40E_VSI_FDIR)
5901 goto fail_queue_alloc;
5905 vsi->msix_intr = ret;
5914 if (type == I40E_VSI_MAIN) {
5915 /* For main VSI, no need to add since it's default one */
5916 vsi->uplink_seid = pf->mac_seid;
5917 vsi->seid = pf->main_vsi_seid;
5918 /* Bind queues with specific MSIX interrupt */
5920 * Needs 2 interrupt at least, one for misc cause which will
5921 * enabled from OS side, Another for queues binding the
5922 * interrupt from device side only.
5925 /* Get default VSI parameters from hardware */
5926 memset(&ctxt, 0, sizeof(ctxt));
5927 ctxt.seid = vsi->seid;
5928 ctxt.pf_num = hw->pf_id;
5929 ctxt.uplink_seid = vsi->uplink_seid;
5931 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5932 if (ret != I40E_SUCCESS) {
5933 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5934 goto fail_msix_alloc;
5936 rte_memcpy(&vsi->info, &ctxt.info,
5937 sizeof(struct i40e_aqc_vsi_properties_data));
5938 vsi->vsi_id = ctxt.vsi_number;
5939 vsi->info.valid_sections = 0;
5941 /* Configure tc, enabled TC0 only */
5942 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5944 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5945 goto fail_msix_alloc;
5948 /* TC, queue mapping */
5949 memset(&ctxt, 0, sizeof(ctxt));
5950 vsi->info.valid_sections |=
5951 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5952 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5953 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5954 rte_memcpy(&ctxt.info, &vsi->info,
5955 sizeof(struct i40e_aqc_vsi_properties_data));
5956 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5957 I40E_DEFAULT_TCMAP);
5958 if (ret != I40E_SUCCESS) {
5960 "Failed to configure TC queue mapping");
5961 goto fail_msix_alloc;
5963 ctxt.seid = vsi->seid;
5964 ctxt.pf_num = hw->pf_id;
5965 ctxt.uplink_seid = vsi->uplink_seid;
5968 /* Update VSI parameters */
5969 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5970 if (ret != I40E_SUCCESS) {
5971 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5972 goto fail_msix_alloc;
5975 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5976 sizeof(vsi->info.tc_mapping));
5977 rte_memcpy(&vsi->info.queue_mapping,
5978 &ctxt.info.queue_mapping,
5979 sizeof(vsi->info.queue_mapping));
5980 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5981 vsi->info.valid_sections = 0;
5983 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5987 * Updating default filter settings are necessary to prevent
5988 * reception of tagged packets.
5989 * Some old firmware configurations load a default macvlan
5990 * filter which accepts both tagged and untagged packets.
5991 * The updating is to use a normal filter instead if needed.
5992 * For NVM 4.2.2 or after, the updating is not needed anymore.
5993 * The firmware with correct configurations load the default
5994 * macvlan filter which is expected and cannot be removed.
5996 i40e_update_default_filter_setting(vsi);
5997 i40e_config_qinq(hw, vsi);
5998 } else if (type == I40E_VSI_SRIOV) {
5999 memset(&ctxt, 0, sizeof(ctxt));
6001 * For other VSI, the uplink_seid equals to uplink VSI's
6002 * uplink_seid since they share same VEB
6004 if (uplink_vsi == NULL)
6005 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
6007 vsi->uplink_seid = uplink_vsi->uplink_seid;
6008 ctxt.pf_num = hw->pf_id;
6009 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
6010 ctxt.uplink_seid = vsi->uplink_seid;
6011 ctxt.connection_type = 0x1;
6012 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
6014 /* Use the VEB configuration if FW >= v5.0 */
6015 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
6016 /* Configure switch ID */
6017 ctxt.info.valid_sections |=
6018 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6019 ctxt.info.switch_id =
6020 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6023 /* Configure port/vlan */
6024 ctxt.info.valid_sections |=
6025 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6026 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6027 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6028 hw->func_caps.enabled_tcmap);
6029 if (ret != I40E_SUCCESS) {
6031 "Failed to configure TC queue mapping");
6032 goto fail_msix_alloc;
6035 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
6036 ctxt.info.valid_sections |=
6037 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6039 * Since VSI is not created yet, only configure parameter,
6040 * will add vsi below.
6043 i40e_config_qinq(hw, vsi);
6044 } else if (type == I40E_VSI_VMDQ2) {
6045 memset(&ctxt, 0, sizeof(ctxt));
6047 * For other VSI, the uplink_seid equals to uplink VSI's
6048 * uplink_seid since they share same VEB
6050 vsi->uplink_seid = uplink_vsi->uplink_seid;
6051 ctxt.pf_num = hw->pf_id;
6053 ctxt.uplink_seid = vsi->uplink_seid;
6054 ctxt.connection_type = 0x1;
6055 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
6057 ctxt.info.valid_sections |=
6058 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6059 /* user_param carries flag to enable loop back */
6061 ctxt.info.switch_id =
6062 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6063 ctxt.info.switch_id |=
6064 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6067 /* Configure port/vlan */
6068 ctxt.info.valid_sections |=
6069 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6070 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6071 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6072 I40E_DEFAULT_TCMAP);
6073 if (ret != I40E_SUCCESS) {
6075 "Failed to configure TC queue mapping");
6076 goto fail_msix_alloc;
6078 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
6079 ctxt.info.valid_sections |=
6080 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6081 } else if (type == I40E_VSI_FDIR) {
6082 memset(&ctxt, 0, sizeof(ctxt));
6083 vsi->uplink_seid = uplink_vsi->uplink_seid;
6084 ctxt.pf_num = hw->pf_id;
6086 ctxt.uplink_seid = vsi->uplink_seid;
6087 ctxt.connection_type = 0x1; /* regular data port */
6088 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6089 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6090 I40E_DEFAULT_TCMAP);
6091 if (ret != I40E_SUCCESS) {
6093 "Failed to configure TC queue mapping.");
6094 goto fail_msix_alloc;
6096 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
6097 ctxt.info.valid_sections |=
6098 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6100 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
6101 goto fail_msix_alloc;
6104 if (vsi->type != I40E_VSI_MAIN) {
6105 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6106 if (ret != I40E_SUCCESS) {
6107 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
6108 hw->aq.asq_last_status);
6109 goto fail_msix_alloc;
6111 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6112 vsi->info.valid_sections = 0;
6113 vsi->seid = ctxt.seid;
6114 vsi->vsi_id = ctxt.vsi_number;
6115 vsi->sib_vsi_list.vsi = vsi;
6116 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
6117 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
6118 &vsi->sib_vsi_list, list);
6120 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
6121 &vsi->sib_vsi_list, list);
6125 /* MAC/VLAN configuration */
6126 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
6127 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
6129 ret = i40e_vsi_add_mac(vsi, &filter);
6130 if (ret != I40E_SUCCESS) {
6131 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
6132 goto fail_msix_alloc;
6135 /* Get VSI BW information */
6136 i40e_vsi_get_bw_config(vsi);
6139 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
6141 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
6147 /* Configure vlan filter on or off */
6149 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
6152 struct i40e_mac_filter *f;
6154 struct i40e_mac_filter_info *mac_filter;
6155 enum rte_mac_filter_type desired_filter;
6156 int ret = I40E_SUCCESS;
6159 /* Filter to match MAC and VLAN */
6160 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
6162 /* Filter to match only MAC */
6163 desired_filter = RTE_MAC_PERFECT_MATCH;
6168 mac_filter = rte_zmalloc("mac_filter_info_data",
6169 num * sizeof(*mac_filter), 0);
6170 if (mac_filter == NULL) {
6171 PMD_DRV_LOG(ERR, "failed to allocate memory");
6172 return I40E_ERR_NO_MEMORY;
6177 /* Remove all existing mac */
6178 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
6179 mac_filter[i] = f->mac_info;
6180 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6182 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6183 on ? "enable" : "disable");
6189 /* Override with new filter */
6190 for (i = 0; i < num; i++) {
6191 mac_filter[i].filter_type = desired_filter;
6192 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6194 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6195 on ? "enable" : "disable");
6201 rte_free(mac_filter);
6205 /* Configure vlan stripping on or off */
6207 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6209 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6210 struct i40e_vsi_context ctxt;
6212 int ret = I40E_SUCCESS;
6214 /* Check if it has been already on or off */
6215 if (vsi->info.valid_sections &
6216 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6218 if ((vsi->info.port_vlan_flags &
6219 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6220 return 0; /* already on */
6222 if ((vsi->info.port_vlan_flags &
6223 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6224 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6225 return 0; /* already off */
6230 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6232 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6233 vsi->info.valid_sections =
6234 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6235 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6236 vsi->info.port_vlan_flags |= vlan_flags;
6237 ctxt.seid = vsi->seid;
6238 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6239 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6241 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6242 on ? "enable" : "disable");
6248 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6250 struct rte_eth_dev_data *data = dev->data;
6254 /* Apply vlan offload setting */
6255 mask = ETH_VLAN_STRIP_MASK |
6256 ETH_QINQ_STRIP_MASK |
6257 ETH_VLAN_FILTER_MASK |
6258 ETH_VLAN_EXTEND_MASK;
6259 ret = i40e_vlan_offload_set(dev, mask);
6261 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6265 /* Apply pvid setting */
6266 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6267 data->dev_conf.txmode.hw_vlan_insert_pvid);
6269 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6275 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6277 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6279 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6283 i40e_update_flow_control(struct i40e_hw *hw)
6285 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6286 struct i40e_link_status link_status;
6287 uint32_t rxfc = 0, txfc = 0, reg;
6291 memset(&link_status, 0, sizeof(link_status));
6292 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6293 if (ret != I40E_SUCCESS) {
6294 PMD_DRV_LOG(ERR, "Failed to get link status information");
6295 goto write_reg; /* Disable flow control */
6298 an_info = hw->phy.link_info.an_info;
6299 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6300 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6301 ret = I40E_ERR_NOT_READY;
6302 goto write_reg; /* Disable flow control */
6305 * If link auto negotiation is enabled, flow control needs to
6306 * be configured according to it
6308 switch (an_info & I40E_LINK_PAUSE_RXTX) {
6309 case I40E_LINK_PAUSE_RXTX:
6312 hw->fc.current_mode = I40E_FC_FULL;
6314 case I40E_AQ_LINK_PAUSE_RX:
6316 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6318 case I40E_AQ_LINK_PAUSE_TX:
6320 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6323 hw->fc.current_mode = I40E_FC_NONE;
6328 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6329 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6330 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6331 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6332 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6333 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6340 i40e_pf_setup(struct i40e_pf *pf)
6342 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6343 struct i40e_filter_control_settings settings;
6344 struct i40e_vsi *vsi;
6347 /* Clear all stats counters */
6348 pf->offset_loaded = FALSE;
6349 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6350 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6351 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6352 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6354 ret = i40e_pf_get_switch_config(pf);
6355 if (ret != I40E_SUCCESS) {
6356 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6360 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6362 PMD_INIT_LOG(WARNING,
6363 "failed to allocate switch domain for device %d", ret);
6365 if (pf->flags & I40E_FLAG_FDIR) {
6366 /* make queue allocated first, let FDIR use queue pair 0*/
6367 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6368 if (ret != I40E_FDIR_QUEUE_ID) {
6370 "queue allocation fails for FDIR: ret =%d",
6372 pf->flags &= ~I40E_FLAG_FDIR;
6375 /* main VSI setup */
6376 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6378 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6379 return I40E_ERR_NOT_READY;
6383 /* Configure filter control */
6384 memset(&settings, 0, sizeof(settings));
6385 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6386 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6387 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6388 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6390 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6391 hw->func_caps.rss_table_size);
6392 return I40E_ERR_PARAM;
6394 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6395 hw->func_caps.rss_table_size);
6396 pf->hash_lut_size = hw->func_caps.rss_table_size;
6398 /* Enable ethtype and macvlan filters */
6399 settings.enable_ethtype = TRUE;
6400 settings.enable_macvlan = TRUE;
6401 ret = i40e_set_filter_control(hw, &settings);
6403 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6406 /* Update flow control according to the auto negotiation */
6407 i40e_update_flow_control(hw);
6409 return I40E_SUCCESS;
6413 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6419 * Set or clear TX Queue Disable flags,
6420 * which is required by hardware.
6422 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6423 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6425 /* Wait until the request is finished */
6426 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6427 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6428 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6429 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6430 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6436 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6437 return I40E_SUCCESS; /* already on, skip next steps */
6439 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6440 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6442 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6443 return I40E_SUCCESS; /* already off, skip next steps */
6444 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6446 /* Write the register */
6447 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6448 /* Check the result */
6449 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6450 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6451 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6453 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6454 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6457 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6458 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6462 /* Check if it is timeout */
6463 if (j >= I40E_CHK_Q_ENA_COUNT) {
6464 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6465 (on ? "enable" : "disable"), q_idx);
6466 return I40E_ERR_TIMEOUT;
6469 return I40E_SUCCESS;
6473 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6478 /* Wait until the request is finished */
6479 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6480 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6481 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6482 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6483 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6488 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6489 return I40E_SUCCESS; /* Already on, skip next steps */
6490 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6492 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6493 return I40E_SUCCESS; /* Already off, skip next steps */
6494 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6497 /* Write the register */
6498 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6499 /* Check the result */
6500 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6501 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6502 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6504 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6505 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6508 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6509 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6514 /* Check if it is timeout */
6515 if (j >= I40E_CHK_Q_ENA_COUNT) {
6516 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6517 (on ? "enable" : "disable"), q_idx);
6518 return I40E_ERR_TIMEOUT;
6521 return I40E_SUCCESS;
6524 /* Initialize VSI for TX */
6526 i40e_dev_tx_init(struct i40e_pf *pf)
6528 struct rte_eth_dev_data *data = pf->dev_data;
6530 uint32_t ret = I40E_SUCCESS;
6531 struct i40e_tx_queue *txq;
6533 for (i = 0; i < data->nb_tx_queues; i++) {
6534 txq = data->tx_queues[i];
6535 if (!txq || !txq->q_set)
6537 ret = i40e_tx_queue_init(txq);
6538 if (ret != I40E_SUCCESS)
6541 if (ret == I40E_SUCCESS)
6542 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6548 /* Initialize VSI for RX */
6550 i40e_dev_rx_init(struct i40e_pf *pf)
6552 struct rte_eth_dev_data *data = pf->dev_data;
6553 int ret = I40E_SUCCESS;
6555 struct i40e_rx_queue *rxq;
6557 i40e_pf_config_rss(pf);
6558 for (i = 0; i < data->nb_rx_queues; i++) {
6559 rxq = data->rx_queues[i];
6560 if (!rxq || !rxq->q_set)
6563 ret = i40e_rx_queue_init(rxq);
6564 if (ret != I40E_SUCCESS) {
6566 "Failed to do RX queue initialization");
6570 if (ret == I40E_SUCCESS)
6571 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6578 i40e_dev_rxtx_init(struct i40e_pf *pf)
6582 err = i40e_dev_tx_init(pf);
6584 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6587 err = i40e_dev_rx_init(pf);
6589 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6597 i40e_vmdq_setup(struct rte_eth_dev *dev)
6599 struct rte_eth_conf *conf = &dev->data->dev_conf;
6600 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6601 int i, err, conf_vsis, j, loop;
6602 struct i40e_vsi *vsi;
6603 struct i40e_vmdq_info *vmdq_info;
6604 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6605 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6608 * Disable interrupt to avoid message from VF. Furthermore, it will
6609 * avoid race condition in VSI creation/destroy.
6611 i40e_pf_disable_irq0(hw);
6613 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6614 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6618 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6619 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6620 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6621 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6622 pf->max_nb_vmdq_vsi);
6626 if (pf->vmdq != NULL) {
6627 PMD_INIT_LOG(INFO, "VMDQ already configured");
6631 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6632 sizeof(*vmdq_info) * conf_vsis, 0);
6634 if (pf->vmdq == NULL) {
6635 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6639 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6641 /* Create VMDQ VSI */
6642 for (i = 0; i < conf_vsis; i++) {
6643 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6644 vmdq_conf->enable_loop_back);
6646 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6650 vmdq_info = &pf->vmdq[i];
6652 vmdq_info->vsi = vsi;
6654 pf->nb_cfg_vmdq_vsi = conf_vsis;
6656 /* Configure Vlan */
6657 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6658 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6659 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6660 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6661 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6662 vmdq_conf->pool_map[i].vlan_id, j);
6664 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6665 vmdq_conf->pool_map[i].vlan_id);
6667 PMD_INIT_LOG(ERR, "Failed to add vlan");
6675 i40e_pf_enable_irq0(hw);
6680 for (i = 0; i < conf_vsis; i++)
6681 if (pf->vmdq[i].vsi == NULL)
6684 i40e_vsi_release(pf->vmdq[i].vsi);
6688 i40e_pf_enable_irq0(hw);
6693 i40e_stat_update_32(struct i40e_hw *hw,
6701 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6705 if (new_data >= *offset)
6706 *stat = (uint64_t)(new_data - *offset);
6708 *stat = (uint64_t)((new_data +
6709 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6713 i40e_stat_update_48(struct i40e_hw *hw,
6722 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6723 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6724 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6729 if (new_data >= *offset)
6730 *stat = new_data - *offset;
6732 *stat = (uint64_t)((new_data +
6733 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6735 *stat &= I40E_48_BIT_MASK;
6740 i40e_pf_disable_irq0(struct i40e_hw *hw)
6742 /* Disable all interrupt types */
6743 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6744 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6745 I40E_WRITE_FLUSH(hw);
6750 i40e_pf_enable_irq0(struct i40e_hw *hw)
6752 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6753 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6754 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6755 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6756 I40E_WRITE_FLUSH(hw);
6760 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6762 /* read pending request and disable first */
6763 i40e_pf_disable_irq0(hw);
6764 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6765 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6766 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6769 /* Link no queues with irq0 */
6770 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6771 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6775 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6777 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6778 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6781 uint32_t index, offset, val;
6786 * Try to find which VF trigger a reset, use absolute VF id to access
6787 * since the reg is global register.
6789 for (i = 0; i < pf->vf_num; i++) {
6790 abs_vf_id = hw->func_caps.vf_base_id + i;
6791 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6792 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6793 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6794 /* VFR event occurred */
6795 if (val & (0x1 << offset)) {
6798 /* Clear the event first */
6799 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6801 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6803 * Only notify a VF reset event occurred,
6804 * don't trigger another SW reset
6806 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6807 if (ret != I40E_SUCCESS)
6808 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6814 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6816 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6819 for (i = 0; i < pf->vf_num; i++)
6820 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6824 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6826 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6827 struct i40e_arq_event_info info;
6828 uint16_t pending, opcode;
6831 info.buf_len = I40E_AQ_BUF_SZ;
6832 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6833 if (!info.msg_buf) {
6834 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6840 ret = i40e_clean_arq_element(hw, &info, &pending);
6842 if (ret != I40E_SUCCESS) {
6844 "Failed to read msg from AdminQ, aq_err: %u",
6845 hw->aq.asq_last_status);
6848 opcode = rte_le_to_cpu_16(info.desc.opcode);
6851 case i40e_aqc_opc_send_msg_to_pf:
6852 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6853 i40e_pf_host_handle_vf_msg(dev,
6854 rte_le_to_cpu_16(info.desc.retval),
6855 rte_le_to_cpu_32(info.desc.cookie_high),
6856 rte_le_to_cpu_32(info.desc.cookie_low),
6860 case i40e_aqc_opc_get_link_status:
6861 ret = i40e_dev_link_update(dev, 0);
6863 rte_eth_dev_callback_process(dev,
6864 RTE_ETH_EVENT_INTR_LSC, NULL);
6867 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6872 rte_free(info.msg_buf);
6876 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6878 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6879 #define I40E_MDD_CLEAR16 0xFFFF
6880 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6881 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6882 bool mdd_detected = false;
6883 struct i40e_pf_vf *vf;
6887 /* find what triggered the MDD event */
6888 reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6889 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6890 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6891 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6892 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6893 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6894 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6895 I40E_GL_MDET_TX_EVENT_SHIFT;
6896 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6897 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6898 hw->func_caps.base_queue;
6899 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6900 "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6901 event, queue, pf_num, vf_num, dev->data->name);
6902 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6903 mdd_detected = true;
6905 reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6906 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6907 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6908 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6909 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6910 I40E_GL_MDET_RX_EVENT_SHIFT;
6911 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6912 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6913 hw->func_caps.base_queue;
6915 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6916 "queue %d of function 0x%02x device %s\n",
6917 event, queue, func, dev->data->name);
6918 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6919 mdd_detected = true;
6923 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6924 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6925 I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6926 PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6928 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6929 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6930 I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6932 PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6936 /* see if one of the VFs needs its hand slapped */
6937 for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6939 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6940 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6941 I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6943 vf->num_mdd_events++;
6944 PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6946 i, vf->num_mdd_events);
6949 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6950 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6951 I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6953 vf->num_mdd_events++;
6954 PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6956 i, vf->num_mdd_events);
6962 * Interrupt handler triggered by NIC for handling
6963 * specific interrupt.
6966 * Pointer to interrupt handle.
6968 * The address of parameter (struct rte_eth_dev *) regsitered before.
6974 i40e_dev_interrupt_handler(void *param)
6976 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6977 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6980 /* Disable interrupt */
6981 i40e_pf_disable_irq0(hw);
6983 /* read out interrupt causes */
6984 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6986 /* No interrupt event indicated */
6987 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6988 PMD_DRV_LOG(INFO, "No interrupt event");
6991 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6992 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6993 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6994 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6995 i40e_handle_mdd_event(dev);
6997 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6998 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6999 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
7000 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
7001 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
7002 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
7003 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
7004 PMD_DRV_LOG(ERR, "ICR0: HMC error");
7005 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
7006 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
7008 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
7009 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
7010 i40e_dev_handle_vfr_event(dev);
7012 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
7013 PMD_DRV_LOG(INFO, "ICR0: adminq event");
7014 i40e_dev_handle_aq_msg(dev);
7018 /* Enable interrupt */
7019 i40e_pf_enable_irq0(hw);
7023 i40e_dev_alarm_handler(void *param)
7025 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7026 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7029 /* Disable interrupt */
7030 i40e_pf_disable_irq0(hw);
7032 /* read out interrupt causes */
7033 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
7035 /* No interrupt event indicated */
7036 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
7038 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
7039 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
7040 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
7041 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
7042 i40e_handle_mdd_event(dev);
7044 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
7045 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
7046 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
7047 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
7048 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
7049 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
7050 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
7051 PMD_DRV_LOG(ERR, "ICR0: HMC error");
7052 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
7053 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
7055 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
7056 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
7057 i40e_dev_handle_vfr_event(dev);
7059 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
7060 PMD_DRV_LOG(INFO, "ICR0: adminq event");
7061 i40e_dev_handle_aq_msg(dev);
7065 /* Enable interrupt */
7066 i40e_pf_enable_irq0(hw);
7067 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
7068 i40e_dev_alarm_handler, dev);
7072 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
7073 struct i40e_macvlan_filter *filter,
7076 int ele_num, ele_buff_size;
7077 int num, actual_num, i;
7079 int ret = I40E_SUCCESS;
7080 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7081 struct i40e_aqc_add_macvlan_element_data *req_list;
7083 if (filter == NULL || total == 0)
7084 return I40E_ERR_PARAM;
7085 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7086 ele_buff_size = hw->aq.asq_buf_size;
7088 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
7089 if (req_list == NULL) {
7090 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7091 return I40E_ERR_NO_MEMORY;
7096 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7097 memset(req_list, 0, ele_buff_size);
7099 for (i = 0; i < actual_num; i++) {
7100 rte_memcpy(req_list[i].mac_addr,
7101 &filter[num + i].macaddr, ETH_ADDR_LEN);
7102 req_list[i].vlan_tag =
7103 rte_cpu_to_le_16(filter[num + i].vlan_id);
7105 switch (filter[num + i].filter_type) {
7106 case RTE_MAC_PERFECT_MATCH:
7107 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
7108 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7110 case RTE_MACVLAN_PERFECT_MATCH:
7111 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
7113 case RTE_MAC_HASH_MATCH:
7114 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
7115 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7117 case RTE_MACVLAN_HASH_MATCH:
7118 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
7121 PMD_DRV_LOG(ERR, "Invalid MAC match type");
7122 ret = I40E_ERR_PARAM;
7126 req_list[i].queue_number = 0;
7128 req_list[i].flags = rte_cpu_to_le_16(flags);
7131 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
7133 if (ret != I40E_SUCCESS) {
7134 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
7138 } while (num < total);
7146 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7147 struct i40e_macvlan_filter *filter,
7150 int ele_num, ele_buff_size;
7151 int num, actual_num, i;
7153 int ret = I40E_SUCCESS;
7154 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7155 struct i40e_aqc_remove_macvlan_element_data *req_list;
7157 if (filter == NULL || total == 0)
7158 return I40E_ERR_PARAM;
7160 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7161 ele_buff_size = hw->aq.asq_buf_size;
7163 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7164 if (req_list == NULL) {
7165 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7166 return I40E_ERR_NO_MEMORY;
7171 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7172 memset(req_list, 0, ele_buff_size);
7174 for (i = 0; i < actual_num; i++) {
7175 rte_memcpy(req_list[i].mac_addr,
7176 &filter[num + i].macaddr, ETH_ADDR_LEN);
7177 req_list[i].vlan_tag =
7178 rte_cpu_to_le_16(filter[num + i].vlan_id);
7180 switch (filter[num + i].filter_type) {
7181 case RTE_MAC_PERFECT_MATCH:
7182 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7183 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7185 case RTE_MACVLAN_PERFECT_MATCH:
7186 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7188 case RTE_MAC_HASH_MATCH:
7189 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7190 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7192 case RTE_MACVLAN_HASH_MATCH:
7193 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7196 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7197 ret = I40E_ERR_PARAM;
7200 req_list[i].flags = rte_cpu_to_le_16(flags);
7203 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7205 if (ret != I40E_SUCCESS) {
7206 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7210 } while (num < total);
7217 /* Find out specific MAC filter */
7218 static struct i40e_mac_filter *
7219 i40e_find_mac_filter(struct i40e_vsi *vsi,
7220 struct rte_ether_addr *macaddr)
7222 struct i40e_mac_filter *f;
7224 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7225 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7233 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7236 uint32_t vid_idx, vid_bit;
7238 if (vlan_id > ETH_VLAN_ID_MAX)
7241 vid_idx = I40E_VFTA_IDX(vlan_id);
7242 vid_bit = I40E_VFTA_BIT(vlan_id);
7244 if (vsi->vfta[vid_idx] & vid_bit)
7251 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7252 uint16_t vlan_id, bool on)
7254 uint32_t vid_idx, vid_bit;
7256 vid_idx = I40E_VFTA_IDX(vlan_id);
7257 vid_bit = I40E_VFTA_BIT(vlan_id);
7260 vsi->vfta[vid_idx] |= vid_bit;
7262 vsi->vfta[vid_idx] &= ~vid_bit;
7266 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7267 uint16_t vlan_id, bool on)
7269 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7270 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7273 if (vlan_id > ETH_VLAN_ID_MAX)
7276 i40e_store_vlan_filter(vsi, vlan_id, on);
7278 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7281 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7284 ret = i40e_aq_add_vlan(hw, vsi->seid,
7285 &vlan_data, 1, NULL);
7286 if (ret != I40E_SUCCESS)
7287 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7289 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7290 &vlan_data, 1, NULL);
7291 if (ret != I40E_SUCCESS)
7293 "Failed to remove vlan filter");
7298 * Find all vlan options for specific mac addr,
7299 * return with actual vlan found.
7302 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7303 struct i40e_macvlan_filter *mv_f,
7304 int num, struct rte_ether_addr *addr)
7310 * Not to use i40e_find_vlan_filter to decrease the loop time,
7311 * although the code looks complex.
7313 if (num < vsi->vlan_num)
7314 return I40E_ERR_PARAM;
7317 for (j = 0; j < I40E_VFTA_SIZE; j++) {
7319 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7320 if (vsi->vfta[j] & (1 << k)) {
7323 "vlan number doesn't match");
7324 return I40E_ERR_PARAM;
7326 rte_memcpy(&mv_f[i].macaddr,
7327 addr, ETH_ADDR_LEN);
7329 j * I40E_UINT32_BIT_SIZE + k;
7335 return I40E_SUCCESS;
7339 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7340 struct i40e_macvlan_filter *mv_f,
7345 struct i40e_mac_filter *f;
7347 if (num < vsi->mac_num)
7348 return I40E_ERR_PARAM;
7350 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7352 PMD_DRV_LOG(ERR, "buffer number not match");
7353 return I40E_ERR_PARAM;
7355 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7357 mv_f[i].vlan_id = vlan;
7358 mv_f[i].filter_type = f->mac_info.filter_type;
7362 return I40E_SUCCESS;
7366 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7369 struct i40e_mac_filter *f;
7370 struct i40e_macvlan_filter *mv_f;
7371 int ret = I40E_SUCCESS;
7373 if (vsi == NULL || vsi->mac_num == 0)
7374 return I40E_ERR_PARAM;
7376 /* Case that no vlan is set */
7377 if (vsi->vlan_num == 0)
7380 num = vsi->mac_num * vsi->vlan_num;
7382 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7384 PMD_DRV_LOG(ERR, "failed to allocate memory");
7385 return I40E_ERR_NO_MEMORY;
7389 if (vsi->vlan_num == 0) {
7390 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7391 rte_memcpy(&mv_f[i].macaddr,
7392 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7393 mv_f[i].filter_type = f->mac_info.filter_type;
7394 mv_f[i].vlan_id = 0;
7398 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7399 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7400 vsi->vlan_num, &f->mac_info.mac_addr);
7401 if (ret != I40E_SUCCESS)
7403 for (j = i; j < i + vsi->vlan_num; j++)
7404 mv_f[j].filter_type = f->mac_info.filter_type;
7409 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7417 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7419 struct i40e_macvlan_filter *mv_f;
7421 int ret = I40E_SUCCESS;
7423 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7424 return I40E_ERR_PARAM;
7426 /* If it's already set, just return */
7427 if (i40e_find_vlan_filter(vsi,vlan))
7428 return I40E_SUCCESS;
7430 mac_num = vsi->mac_num;
7433 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7434 return I40E_ERR_PARAM;
7437 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7440 PMD_DRV_LOG(ERR, "failed to allocate memory");
7441 return I40E_ERR_NO_MEMORY;
7444 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7446 if (ret != I40E_SUCCESS)
7449 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7451 if (ret != I40E_SUCCESS)
7454 i40e_set_vlan_filter(vsi, vlan, 1);
7464 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7466 struct i40e_macvlan_filter *mv_f;
7468 int ret = I40E_SUCCESS;
7471 * Vlan 0 is the generic filter for untagged packets
7472 * and can't be removed.
7474 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7475 return I40E_ERR_PARAM;
7477 /* If can't find it, just return */
7478 if (!i40e_find_vlan_filter(vsi, vlan))
7479 return I40E_ERR_PARAM;
7481 mac_num = vsi->mac_num;
7484 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7485 return I40E_ERR_PARAM;
7488 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7491 PMD_DRV_LOG(ERR, "failed to allocate memory");
7492 return I40E_ERR_NO_MEMORY;
7495 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7497 if (ret != I40E_SUCCESS)
7500 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7502 if (ret != I40E_SUCCESS)
7505 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7506 if (vsi->vlan_num == 1) {
7507 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7508 if (ret != I40E_SUCCESS)
7511 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7512 if (ret != I40E_SUCCESS)
7516 i40e_set_vlan_filter(vsi, vlan, 0);
7526 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7528 struct i40e_mac_filter *f;
7529 struct i40e_macvlan_filter *mv_f;
7530 int i, vlan_num = 0;
7531 int ret = I40E_SUCCESS;
7533 /* If it's add and we've config it, return */
7534 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7536 return I40E_SUCCESS;
7537 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7538 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7541 * If vlan_num is 0, that's the first time to add mac,
7542 * set mask for vlan_id 0.
7544 if (vsi->vlan_num == 0) {
7545 i40e_set_vlan_filter(vsi, 0, 1);
7548 vlan_num = vsi->vlan_num;
7549 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7550 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7553 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7555 PMD_DRV_LOG(ERR, "failed to allocate memory");
7556 return I40E_ERR_NO_MEMORY;
7559 for (i = 0; i < vlan_num; i++) {
7560 mv_f[i].filter_type = mac_filter->filter_type;
7561 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7565 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7566 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7567 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7568 &mac_filter->mac_addr);
7569 if (ret != I40E_SUCCESS)
7573 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7574 if (ret != I40E_SUCCESS)
7577 /* Add the mac addr into mac list */
7578 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7580 PMD_DRV_LOG(ERR, "failed to allocate memory");
7581 ret = I40E_ERR_NO_MEMORY;
7584 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7586 f->mac_info.filter_type = mac_filter->filter_type;
7587 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7598 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7600 struct i40e_mac_filter *f;
7601 struct i40e_macvlan_filter *mv_f;
7603 enum rte_mac_filter_type filter_type;
7604 int ret = I40E_SUCCESS;
7606 /* Can't find it, return an error */
7607 f = i40e_find_mac_filter(vsi, addr);
7609 return I40E_ERR_PARAM;
7611 vlan_num = vsi->vlan_num;
7612 filter_type = f->mac_info.filter_type;
7613 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7614 filter_type == RTE_MACVLAN_HASH_MATCH) {
7615 if (vlan_num == 0) {
7616 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7617 return I40E_ERR_PARAM;
7619 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7620 filter_type == RTE_MAC_HASH_MATCH)
7623 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7625 PMD_DRV_LOG(ERR, "failed to allocate memory");
7626 return I40E_ERR_NO_MEMORY;
7629 for (i = 0; i < vlan_num; i++) {
7630 mv_f[i].filter_type = filter_type;
7631 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7634 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7635 filter_type == RTE_MACVLAN_HASH_MATCH) {
7636 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7637 if (ret != I40E_SUCCESS)
7641 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7642 if (ret != I40E_SUCCESS)
7645 /* Remove the mac addr into mac list */
7646 TAILQ_REMOVE(&vsi->mac_list, f, next);
7656 /* Configure hash enable flags for RSS */
7658 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7666 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7667 if (flags & (1ULL << i))
7668 hena |= adapter->pctypes_tbl[i];
7674 /* Parse the hash enable flags */
7676 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7678 uint64_t rss_hf = 0;
7684 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7685 if (flags & adapter->pctypes_tbl[i])
7686 rss_hf |= (1ULL << i);
7693 i40e_pf_disable_rss(struct i40e_pf *pf)
7695 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7697 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7698 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7699 I40E_WRITE_FLUSH(hw);
7703 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7705 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7706 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7707 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7708 I40E_VFQF_HKEY_MAX_INDEX :
7709 I40E_PFQF_HKEY_MAX_INDEX;
7712 if (!key || key_len == 0) {
7713 PMD_DRV_LOG(DEBUG, "No key to be configured");
7715 } else if (key_len != (key_idx + 1) *
7717 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7721 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7722 struct i40e_aqc_get_set_rss_key_data *key_dw =
7723 (struct i40e_aqc_get_set_rss_key_data *)key;
7725 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7727 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7729 uint32_t *hash_key = (uint32_t *)key;
7732 if (vsi->type == I40E_VSI_SRIOV) {
7733 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7736 I40E_VFQF_HKEY1(i, vsi->user_param),
7740 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7741 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7744 I40E_WRITE_FLUSH(hw);
7751 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7753 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7754 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7758 if (!key || !key_len)
7761 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7762 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7763 (struct i40e_aqc_get_set_rss_key_data *)key);
7765 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7769 uint32_t *key_dw = (uint32_t *)key;
7772 if (vsi->type == I40E_VSI_SRIOV) {
7773 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7774 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7775 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7777 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7780 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7781 reg = I40E_PFQF_HKEY(i);
7782 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7784 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7792 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7794 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7798 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7799 rss_conf->rss_key_len);
7803 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7804 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7805 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7806 I40E_WRITE_FLUSH(hw);
7812 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7813 struct rte_eth_rss_conf *rss_conf)
7815 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7816 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7817 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7820 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7821 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7823 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7824 if (rss_hf != 0) /* Enable RSS */
7826 return 0; /* Nothing to do */
7829 if (rss_hf == 0) /* Disable RSS */
7832 return i40e_hw_rss_hash_set(pf, rss_conf);
7836 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7837 struct rte_eth_rss_conf *rss_conf)
7839 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7840 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7847 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7848 &rss_conf->rss_key_len);
7852 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7853 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7854 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7860 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7862 switch (filter_type) {
7863 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7864 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7866 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7867 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7869 case RTE_TUNNEL_FILTER_IMAC_TENID:
7870 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7872 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7873 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7875 case ETH_TUNNEL_FILTER_IMAC:
7876 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7878 case ETH_TUNNEL_FILTER_OIP:
7879 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7881 case ETH_TUNNEL_FILTER_IIP:
7882 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7885 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7892 /* Convert tunnel filter structure */
7894 i40e_tunnel_filter_convert(
7895 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7896 struct i40e_tunnel_filter *tunnel_filter)
7898 rte_ether_addr_copy((struct rte_ether_addr *)
7899 &cld_filter->element.outer_mac,
7900 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7901 rte_ether_addr_copy((struct rte_ether_addr *)
7902 &cld_filter->element.inner_mac,
7903 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7904 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7905 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7906 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7907 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7908 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7910 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7911 tunnel_filter->input.flags = cld_filter->element.flags;
7912 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7913 tunnel_filter->queue = cld_filter->element.queue_number;
7914 rte_memcpy(tunnel_filter->input.general_fields,
7915 cld_filter->general_fields,
7916 sizeof(cld_filter->general_fields));
7921 /* Check if there exists the tunnel filter */
7922 struct i40e_tunnel_filter *
7923 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7924 const struct i40e_tunnel_filter_input *input)
7928 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7932 return tunnel_rule->hash_map[ret];
7935 /* Add a tunnel filter into the SW list */
7937 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7938 struct i40e_tunnel_filter *tunnel_filter)
7940 struct i40e_tunnel_rule *rule = &pf->tunnel;
7943 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7946 "Failed to insert tunnel filter to hash table %d!",
7950 rule->hash_map[ret] = tunnel_filter;
7952 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7957 /* Delete a tunnel filter from the SW list */
7959 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7960 struct i40e_tunnel_filter_input *input)
7962 struct i40e_tunnel_rule *rule = &pf->tunnel;
7963 struct i40e_tunnel_filter *tunnel_filter;
7966 ret = rte_hash_del_key(rule->hash_table, input);
7969 "Failed to delete tunnel filter to hash table %d!",
7973 tunnel_filter = rule->hash_map[ret];
7974 rule->hash_map[ret] = NULL;
7976 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7977 rte_free(tunnel_filter);
7983 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7984 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7988 uint32_t ipv4_addr, ipv4_addr_le;
7989 uint8_t i, tun_type = 0;
7990 /* internal varialbe to convert ipv6 byte order */
7991 uint32_t convert_ipv6[4];
7993 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7994 struct i40e_vsi *vsi = pf->main_vsi;
7995 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7996 struct i40e_aqc_cloud_filters_element_bb *pfilter;
7997 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7998 struct i40e_tunnel_filter *tunnel, *node;
7999 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8001 cld_filter = rte_zmalloc("tunnel_filter",
8002 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8005 if (NULL == cld_filter) {
8006 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8009 pfilter = cld_filter;
8011 rte_ether_addr_copy(&tunnel_filter->outer_mac,
8012 (struct rte_ether_addr *)&pfilter->element.outer_mac);
8013 rte_ether_addr_copy(&tunnel_filter->inner_mac,
8014 (struct rte_ether_addr *)&pfilter->element.inner_mac);
8016 pfilter->element.inner_vlan =
8017 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8018 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
8019 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8020 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8021 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8022 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8024 sizeof(pfilter->element.ipaddr.v4.data));
8026 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8027 for (i = 0; i < 4; i++) {
8029 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
8031 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8033 sizeof(pfilter->element.ipaddr.v6.data));
8036 /* check tunneled type */
8037 switch (tunnel_filter->tunnel_type) {
8038 case RTE_TUNNEL_TYPE_VXLAN:
8039 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8041 case RTE_TUNNEL_TYPE_NVGRE:
8042 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8044 case RTE_TUNNEL_TYPE_IP_IN_GRE:
8045 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8047 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8048 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
8051 /* Other tunnel types is not supported. */
8052 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8053 rte_free(cld_filter);
8057 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8058 &pfilter->element.flags);
8060 rte_free(cld_filter);
8064 pfilter->element.flags |= rte_cpu_to_le_16(
8065 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8066 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8067 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8068 pfilter->element.queue_number =
8069 rte_cpu_to_le_16(tunnel_filter->queue_id);
8071 /* Check if there is the filter in SW list */
8072 memset(&check_filter, 0, sizeof(check_filter));
8073 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8074 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8076 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8077 rte_free(cld_filter);
8081 if (!add && !node) {
8082 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8083 rte_free(cld_filter);
8088 ret = i40e_aq_add_cloud_filters(hw,
8089 vsi->seid, &cld_filter->element, 1);
8091 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8092 rte_free(cld_filter);
8095 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8096 if (tunnel == NULL) {
8097 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8098 rte_free(cld_filter);
8102 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8103 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8107 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8108 &cld_filter->element, 1);
8110 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8111 rte_free(cld_filter);
8114 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8117 rte_free(cld_filter);
8121 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
8122 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
8123 #define I40E_TR_GENEVE_KEY_MASK 0x8
8124 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
8125 #define I40E_TR_GRE_KEY_MASK 0x400
8126 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
8127 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
8128 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
8129 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
8130 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
8131 #define I40E_DIRECTION_INGRESS_KEY 0x8000
8132 #define I40E_TR_L4_TYPE_TCP 0x2
8133 #define I40E_TR_L4_TYPE_UDP 0x4
8134 #define I40E_TR_L4_TYPE_SCTP 0x8
8137 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
8139 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8140 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8141 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8142 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8143 enum i40e_status_code status = I40E_SUCCESS;
8145 if (pf->support_multi_driver) {
8146 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8147 return I40E_NOT_SUPPORTED;
8150 memset(&filter_replace, 0,
8151 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8152 memset(&filter_replace_buf, 0,
8153 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8155 /* create L1 filter */
8156 filter_replace.old_filter_type =
8157 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8158 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8159 filter_replace.tr_bit = 0;
8161 /* Prepare the buffer, 3 entries */
8162 filter_replace_buf.data[0] =
8163 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8164 filter_replace_buf.data[0] |=
8165 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8166 filter_replace_buf.data[2] = 0xFF;
8167 filter_replace_buf.data[3] = 0xFF;
8168 filter_replace_buf.data[4] =
8169 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8170 filter_replace_buf.data[4] |=
8171 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8172 filter_replace_buf.data[7] = 0xF0;
8173 filter_replace_buf.data[8]
8174 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
8175 filter_replace_buf.data[8] |=
8176 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8177 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
8178 I40E_TR_GENEVE_KEY_MASK |
8179 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
8180 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
8181 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
8182 I40E_TR_GRE_NO_KEY_MASK) >> 8;
8184 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8185 &filter_replace_buf);
8186 if (!status && (filter_replace.old_filter_type !=
8187 filter_replace.new_filter_type))
8188 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8189 " original: 0x%x, new: 0x%x",
8191 filter_replace.old_filter_type,
8192 filter_replace.new_filter_type);
8198 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
8200 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8201 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8202 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8203 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8204 enum i40e_status_code status = I40E_SUCCESS;
8206 if (pf->support_multi_driver) {
8207 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8208 return I40E_NOT_SUPPORTED;
8212 memset(&filter_replace, 0,
8213 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8214 memset(&filter_replace_buf, 0,
8215 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8216 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8217 I40E_AQC_MIRROR_CLOUD_FILTER;
8218 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8219 filter_replace.new_filter_type =
8220 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8221 /* Prepare the buffer, 2 entries */
8222 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8223 filter_replace_buf.data[0] |=
8224 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8225 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8226 filter_replace_buf.data[4] |=
8227 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8228 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8229 &filter_replace_buf);
8232 if (filter_replace.old_filter_type !=
8233 filter_replace.new_filter_type)
8234 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8235 " original: 0x%x, new: 0x%x",
8237 filter_replace.old_filter_type,
8238 filter_replace.new_filter_type);
8241 memset(&filter_replace, 0,
8242 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8243 memset(&filter_replace_buf, 0,
8244 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8246 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8247 I40E_AQC_MIRROR_CLOUD_FILTER;
8248 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8249 filter_replace.new_filter_type =
8250 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8251 /* Prepare the buffer, 2 entries */
8252 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8253 filter_replace_buf.data[0] |=
8254 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8255 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8256 filter_replace_buf.data[4] |=
8257 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8259 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8260 &filter_replace_buf);
8261 if (!status && (filter_replace.old_filter_type !=
8262 filter_replace.new_filter_type))
8263 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8264 " original: 0x%x, new: 0x%x",
8266 filter_replace.old_filter_type,
8267 filter_replace.new_filter_type);
8272 static enum i40e_status_code
8273 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8275 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8276 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8277 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8278 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8279 enum i40e_status_code status = I40E_SUCCESS;
8281 if (pf->support_multi_driver) {
8282 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8283 return I40E_NOT_SUPPORTED;
8287 memset(&filter_replace, 0,
8288 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8289 memset(&filter_replace_buf, 0,
8290 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8291 /* create L1 filter */
8292 filter_replace.old_filter_type =
8293 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8294 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8295 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8296 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8297 /* Prepare the buffer, 2 entries */
8298 filter_replace_buf.data[0] =
8299 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8300 filter_replace_buf.data[0] |=
8301 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8302 filter_replace_buf.data[2] = 0xFF;
8303 filter_replace_buf.data[3] = 0xFF;
8304 filter_replace_buf.data[4] =
8305 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8306 filter_replace_buf.data[4] |=
8307 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8308 filter_replace_buf.data[6] = 0xFF;
8309 filter_replace_buf.data[7] = 0xFF;
8310 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8311 &filter_replace_buf);
8314 if (filter_replace.old_filter_type !=
8315 filter_replace.new_filter_type)
8316 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8317 " original: 0x%x, new: 0x%x",
8319 filter_replace.old_filter_type,
8320 filter_replace.new_filter_type);
8323 memset(&filter_replace, 0,
8324 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8325 memset(&filter_replace_buf, 0,
8326 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8327 /* create L1 filter */
8328 filter_replace.old_filter_type =
8329 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8330 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8331 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8332 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8333 /* Prepare the buffer, 2 entries */
8334 filter_replace_buf.data[0] =
8335 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8336 filter_replace_buf.data[0] |=
8337 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8338 filter_replace_buf.data[2] = 0xFF;
8339 filter_replace_buf.data[3] = 0xFF;
8340 filter_replace_buf.data[4] =
8341 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8342 filter_replace_buf.data[4] |=
8343 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8344 filter_replace_buf.data[6] = 0xFF;
8345 filter_replace_buf.data[7] = 0xFF;
8347 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8348 &filter_replace_buf);
8349 if (!status && (filter_replace.old_filter_type !=
8350 filter_replace.new_filter_type))
8351 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8352 " original: 0x%x, new: 0x%x",
8354 filter_replace.old_filter_type,
8355 filter_replace.new_filter_type);
8361 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8363 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8364 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8365 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8366 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8367 enum i40e_status_code status = I40E_SUCCESS;
8369 if (pf->support_multi_driver) {
8370 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8371 return I40E_NOT_SUPPORTED;
8375 memset(&filter_replace, 0,
8376 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8377 memset(&filter_replace_buf, 0,
8378 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8379 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8380 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8381 filter_replace.new_filter_type =
8382 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8383 /* Prepare the buffer, 2 entries */
8384 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8385 filter_replace_buf.data[0] |=
8386 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8387 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8388 filter_replace_buf.data[4] |=
8389 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8390 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8391 &filter_replace_buf);
8394 if (filter_replace.old_filter_type !=
8395 filter_replace.new_filter_type)
8396 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8397 " original: 0x%x, new: 0x%x",
8399 filter_replace.old_filter_type,
8400 filter_replace.new_filter_type);
8403 memset(&filter_replace, 0,
8404 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8405 memset(&filter_replace_buf, 0,
8406 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8407 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8408 filter_replace.old_filter_type =
8409 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8410 filter_replace.new_filter_type =
8411 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8412 /* Prepare the buffer, 2 entries */
8413 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8414 filter_replace_buf.data[0] |=
8415 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8416 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8417 filter_replace_buf.data[4] |=
8418 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8420 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8421 &filter_replace_buf);
8422 if (!status && (filter_replace.old_filter_type !=
8423 filter_replace.new_filter_type))
8424 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8425 " original: 0x%x, new: 0x%x",
8427 filter_replace.old_filter_type,
8428 filter_replace.new_filter_type);
8433 static enum i40e_status_code
8434 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8435 enum i40e_l4_port_type l4_port_type)
8437 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8438 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8439 enum i40e_status_code status = I40E_SUCCESS;
8440 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8441 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8443 if (pf->support_multi_driver) {
8444 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8445 return I40E_NOT_SUPPORTED;
8448 memset(&filter_replace, 0,
8449 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8450 memset(&filter_replace_buf, 0,
8451 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8453 /* create L1 filter */
8454 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8455 filter_replace.old_filter_type =
8456 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8457 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8458 filter_replace_buf.data[8] =
8459 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8461 filter_replace.old_filter_type =
8462 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8463 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8464 filter_replace_buf.data[8] =
8465 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8468 filter_replace.tr_bit = 0;
8469 /* Prepare the buffer, 3 entries */
8470 filter_replace_buf.data[0] =
8471 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8472 filter_replace_buf.data[0] |=
8473 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8474 filter_replace_buf.data[2] = 0x00;
8475 filter_replace_buf.data[3] =
8476 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8477 filter_replace_buf.data[4] =
8478 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8479 filter_replace_buf.data[4] |=
8480 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8481 filter_replace_buf.data[5] = 0x00;
8482 filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8483 I40E_TR_L4_TYPE_TCP |
8484 I40E_TR_L4_TYPE_SCTP;
8485 filter_replace_buf.data[7] = 0x00;
8486 filter_replace_buf.data[8] |=
8487 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8488 filter_replace_buf.data[9] = 0x00;
8489 filter_replace_buf.data[10] = 0xFF;
8490 filter_replace_buf.data[11] = 0xFF;
8492 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8493 &filter_replace_buf);
8494 if (!status && filter_replace.old_filter_type !=
8495 filter_replace.new_filter_type)
8496 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8497 " original: 0x%x, new: 0x%x",
8499 filter_replace.old_filter_type,
8500 filter_replace.new_filter_type);
8505 static enum i40e_status_code
8506 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8507 enum i40e_l4_port_type l4_port_type)
8509 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8510 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8511 enum i40e_status_code status = I40E_SUCCESS;
8512 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8513 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8515 if (pf->support_multi_driver) {
8516 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8517 return I40E_NOT_SUPPORTED;
8520 memset(&filter_replace, 0,
8521 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8522 memset(&filter_replace_buf, 0,
8523 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8525 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8526 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8527 filter_replace.new_filter_type =
8528 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8529 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8531 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8532 filter_replace.new_filter_type =
8533 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8534 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8537 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8538 filter_replace.tr_bit = 0;
8539 /* Prepare the buffer, 2 entries */
8540 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8541 filter_replace_buf.data[0] |=
8542 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8543 filter_replace_buf.data[4] |=
8544 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8545 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8546 &filter_replace_buf);
8548 if (!status && filter_replace.old_filter_type !=
8549 filter_replace.new_filter_type)
8550 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8551 " original: 0x%x, new: 0x%x",
8553 filter_replace.old_filter_type,
8554 filter_replace.new_filter_type);
8560 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8561 struct i40e_tunnel_filter_conf *tunnel_filter,
8565 uint32_t ipv4_addr, ipv4_addr_le;
8566 uint8_t i, tun_type = 0;
8567 /* internal variable to convert ipv6 byte order */
8568 uint32_t convert_ipv6[4];
8570 struct i40e_pf_vf *vf = NULL;
8571 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8572 struct i40e_vsi *vsi;
8573 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8574 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8575 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8576 struct i40e_tunnel_filter *tunnel, *node;
8577 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8579 bool big_buffer = 0;
8581 cld_filter = rte_zmalloc("tunnel_filter",
8582 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8585 if (cld_filter == NULL) {
8586 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8589 pfilter = cld_filter;
8591 rte_ether_addr_copy(&tunnel_filter->outer_mac,
8592 (struct rte_ether_addr *)&pfilter->element.outer_mac);
8593 rte_ether_addr_copy(&tunnel_filter->inner_mac,
8594 (struct rte_ether_addr *)&pfilter->element.inner_mac);
8596 pfilter->element.inner_vlan =
8597 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8598 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8599 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8600 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8601 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8602 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8604 sizeof(pfilter->element.ipaddr.v4.data));
8606 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8607 for (i = 0; i < 4; i++) {
8609 rte_cpu_to_le_32(rte_be_to_cpu_32(
8610 tunnel_filter->ip_addr.ipv6_addr[i]));
8612 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8614 sizeof(pfilter->element.ipaddr.v6.data));
8617 /* check tunneled type */
8618 switch (tunnel_filter->tunnel_type) {
8619 case I40E_TUNNEL_TYPE_VXLAN:
8620 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8622 case I40E_TUNNEL_TYPE_NVGRE:
8623 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8625 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8626 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8628 case I40E_TUNNEL_TYPE_MPLSoUDP:
8629 if (!pf->mpls_replace_flag) {
8630 i40e_replace_mpls_l1_filter(pf);
8631 i40e_replace_mpls_cloud_filter(pf);
8632 pf->mpls_replace_flag = 1;
8634 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8635 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8637 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8638 (teid_le & 0xF) << 12;
8639 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8642 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8644 case I40E_TUNNEL_TYPE_MPLSoGRE:
8645 if (!pf->mpls_replace_flag) {
8646 i40e_replace_mpls_l1_filter(pf);
8647 i40e_replace_mpls_cloud_filter(pf);
8648 pf->mpls_replace_flag = 1;
8650 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8651 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8653 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8654 (teid_le & 0xF) << 12;
8655 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8658 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8660 case I40E_TUNNEL_TYPE_GTPC:
8661 if (!pf->gtp_replace_flag) {
8662 i40e_replace_gtp_l1_filter(pf);
8663 i40e_replace_gtp_cloud_filter(pf);
8664 pf->gtp_replace_flag = 1;
8666 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8667 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8668 (teid_le >> 16) & 0xFFFF;
8669 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8671 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8675 case I40E_TUNNEL_TYPE_GTPU:
8676 if (!pf->gtp_replace_flag) {
8677 i40e_replace_gtp_l1_filter(pf);
8678 i40e_replace_gtp_cloud_filter(pf);
8679 pf->gtp_replace_flag = 1;
8681 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8682 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8683 (teid_le >> 16) & 0xFFFF;
8684 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8686 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8690 case I40E_TUNNEL_TYPE_QINQ:
8691 if (!pf->qinq_replace_flag) {
8692 ret = i40e_cloud_filter_qinq_create(pf);
8695 "QinQ tunnel filter already created.");
8696 pf->qinq_replace_flag = 1;
8698 /* Add in the General fields the values of
8699 * the Outer and Inner VLAN
8700 * Big Buffer should be set, see changes in
8701 * i40e_aq_add_cloud_filters
8703 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8704 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8707 case I40E_CLOUD_TYPE_UDP:
8708 case I40E_CLOUD_TYPE_TCP:
8709 case I40E_CLOUD_TYPE_SCTP:
8710 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8711 if (!pf->sport_replace_flag) {
8712 i40e_replace_port_l1_filter(pf,
8713 tunnel_filter->l4_port_type);
8714 i40e_replace_port_cloud_filter(pf,
8715 tunnel_filter->l4_port_type);
8716 pf->sport_replace_flag = 1;
8718 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8719 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8720 I40E_DIRECTION_INGRESS_KEY;
8722 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8723 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8724 I40E_TR_L4_TYPE_UDP;
8725 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8726 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8727 I40E_TR_L4_TYPE_TCP;
8729 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8730 I40E_TR_L4_TYPE_SCTP;
8732 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8733 (teid_le >> 16) & 0xFFFF;
8736 if (!pf->dport_replace_flag) {
8737 i40e_replace_port_l1_filter(pf,
8738 tunnel_filter->l4_port_type);
8739 i40e_replace_port_cloud_filter(pf,
8740 tunnel_filter->l4_port_type);
8741 pf->dport_replace_flag = 1;
8743 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8744 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8745 I40E_DIRECTION_INGRESS_KEY;
8747 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8748 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8749 I40E_TR_L4_TYPE_UDP;
8750 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8751 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8752 I40E_TR_L4_TYPE_TCP;
8754 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8755 I40E_TR_L4_TYPE_SCTP;
8757 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8758 (teid_le >> 16) & 0xFFFF;
8764 /* Other tunnel types is not supported. */
8765 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8766 rte_free(cld_filter);
8770 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8771 pfilter->element.flags =
8772 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8773 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8774 pfilter->element.flags =
8775 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8776 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8777 pfilter->element.flags =
8778 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8779 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8780 pfilter->element.flags =
8781 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8782 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8783 pfilter->element.flags |=
8784 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8785 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8786 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8787 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8788 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8789 pfilter->element.flags |=
8790 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8792 pfilter->element.flags |=
8793 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8795 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8796 &pfilter->element.flags);
8798 rte_free(cld_filter);
8803 pfilter->element.flags |= rte_cpu_to_le_16(
8804 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8805 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8806 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8807 pfilter->element.queue_number =
8808 rte_cpu_to_le_16(tunnel_filter->queue_id);
8810 if (!tunnel_filter->is_to_vf)
8813 if (tunnel_filter->vf_id >= pf->vf_num) {
8814 PMD_DRV_LOG(ERR, "Invalid argument.");
8815 rte_free(cld_filter);
8818 vf = &pf->vfs[tunnel_filter->vf_id];
8822 /* Check if there is the filter in SW list */
8823 memset(&check_filter, 0, sizeof(check_filter));
8824 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8825 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8826 check_filter.vf_id = tunnel_filter->vf_id;
8827 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8829 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8830 rte_free(cld_filter);
8834 if (!add && !node) {
8835 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8836 rte_free(cld_filter);
8842 ret = i40e_aq_add_cloud_filters_bb(hw,
8843 vsi->seid, cld_filter, 1);
8845 ret = i40e_aq_add_cloud_filters(hw,
8846 vsi->seid, &cld_filter->element, 1);
8848 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8849 rte_free(cld_filter);
8852 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8853 if (tunnel == NULL) {
8854 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8855 rte_free(cld_filter);
8859 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8860 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8865 ret = i40e_aq_rem_cloud_filters_bb(
8866 hw, vsi->seid, cld_filter, 1);
8868 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8869 &cld_filter->element, 1);
8871 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8872 rte_free(cld_filter);
8875 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8878 rte_free(cld_filter);
8883 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8887 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8888 if (pf->vxlan_ports[i] == port)
8896 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8899 uint8_t filter_idx = 0;
8900 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8902 idx = i40e_get_vxlan_port_idx(pf, port);
8904 /* Check if port already exists */
8906 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8910 /* Now check if there is space to add the new port */
8911 idx = i40e_get_vxlan_port_idx(pf, 0);
8914 "Maximum number of UDP ports reached, not adding port %d",
8919 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type,
8922 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8926 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8929 /* New port: add it and mark its index in the bitmap */
8930 pf->vxlan_ports[idx] = port;
8931 pf->vxlan_bitmap |= (1 << idx);
8933 if (!(pf->flags & I40E_FLAG_VXLAN))
8934 pf->flags |= I40E_FLAG_VXLAN;
8940 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8943 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8945 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8946 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8950 idx = i40e_get_vxlan_port_idx(pf, port);
8953 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8957 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8958 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8962 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8965 pf->vxlan_ports[idx] = 0;
8966 pf->vxlan_bitmap &= ~(1 << idx);
8968 if (!pf->vxlan_bitmap)
8969 pf->flags &= ~I40E_FLAG_VXLAN;
8974 /* Add UDP tunneling port */
8976 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8977 struct rte_eth_udp_tunnel *udp_tunnel)
8980 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8982 if (udp_tunnel == NULL)
8985 switch (udp_tunnel->prot_type) {
8986 case RTE_TUNNEL_TYPE_VXLAN:
8987 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8988 I40E_AQC_TUNNEL_TYPE_VXLAN);
8990 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8991 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8992 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8994 case RTE_TUNNEL_TYPE_GENEVE:
8995 case RTE_TUNNEL_TYPE_TEREDO:
8996 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
9001 PMD_DRV_LOG(ERR, "Invalid tunnel type");
9009 /* Remove UDP tunneling port */
9011 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
9012 struct rte_eth_udp_tunnel *udp_tunnel)
9015 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9017 if (udp_tunnel == NULL)
9020 switch (udp_tunnel->prot_type) {
9021 case RTE_TUNNEL_TYPE_VXLAN:
9022 case RTE_TUNNEL_TYPE_VXLAN_GPE:
9023 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
9025 case RTE_TUNNEL_TYPE_GENEVE:
9026 case RTE_TUNNEL_TYPE_TEREDO:
9027 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
9031 PMD_DRV_LOG(ERR, "Invalid tunnel type");
9039 /* Calculate the maximum number of contiguous PF queues that are configured */
9041 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
9043 struct rte_eth_dev_data *data = pf->dev_data;
9045 struct i40e_rx_queue *rxq;
9048 for (i = 0; i < pf->lan_nb_qps; i++) {
9049 rxq = data->rx_queues[i];
9050 if (rxq && rxq->q_set)
9061 i40e_pf_config_rss(struct i40e_pf *pf)
9063 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
9064 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9065 struct rte_eth_rss_conf rss_conf;
9066 uint32_t i, lut = 0;
9070 * If both VMDQ and RSS enabled, not all of PF queues are configured.
9071 * It's necessary to calculate the actual PF queues that are configured.
9073 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
9074 num = i40e_pf_calc_configured_queues_num(pf);
9076 num = pf->dev_data->nb_rx_queues;
9078 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
9079 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
9084 "No PF queues are configured to enable RSS for port %u",
9085 pf->dev_data->port_id);
9089 if (pf->adapter->rss_reta_updated == 0) {
9090 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
9093 lut = (lut << 8) | (j & ((0x1 <<
9094 hw->func_caps.rss_table_entry_width) - 1));
9096 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
9101 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
9102 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0 ||
9103 !(mq_mode & ETH_MQ_RX_RSS_FLAG)) {
9104 i40e_pf_disable_rss(pf);
9107 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
9108 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
9109 /* Random default keys */
9110 static uint32_t rss_key_default[] = {0x6b793944,
9111 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
9112 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
9113 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
9115 rss_conf.rss_key = (uint8_t *)rss_key_default;
9116 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
9120 return i40e_hw_rss_hash_set(pf, &rss_conf);
9124 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
9125 struct rte_eth_tunnel_filter_conf *filter)
9127 if (pf == NULL || filter == NULL) {
9128 PMD_DRV_LOG(ERR, "Invalid parameter");
9132 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
9133 PMD_DRV_LOG(ERR, "Invalid queue ID");
9137 if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
9138 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
9142 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
9143 (rte_is_zero_ether_addr(&filter->outer_mac))) {
9144 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
9148 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
9149 (rte_is_zero_ether_addr(&filter->inner_mac))) {
9150 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
9157 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
9158 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
9160 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
9162 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9166 if (pf->support_multi_driver) {
9167 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
9171 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
9172 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
9175 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
9176 } else if (len == 4) {
9177 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
9179 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
9184 ret = i40e_aq_debug_write_global_register(hw,
9185 I40E_GL_PRS_FVBM(2),
9189 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
9190 "with value 0x%08x",
9191 I40E_GL_PRS_FVBM(2), reg);
9195 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
9196 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
9202 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
9209 switch (cfg->cfg_type) {
9210 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
9211 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
9214 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
9222 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
9223 enum rte_filter_op filter_op,
9226 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9227 int ret = I40E_ERR_PARAM;
9229 switch (filter_op) {
9230 case RTE_ETH_FILTER_SET:
9231 ret = i40e_dev_global_config_set(hw,
9232 (struct rte_eth_global_cfg *)arg);
9235 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9243 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
9244 enum rte_filter_op filter_op,
9247 struct rte_eth_tunnel_filter_conf *filter;
9248 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9249 int ret = I40E_SUCCESS;
9251 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
9253 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
9254 return I40E_ERR_PARAM;
9256 switch (filter_op) {
9257 case RTE_ETH_FILTER_NOP:
9258 if (!(pf->flags & I40E_FLAG_VXLAN))
9259 ret = I40E_NOT_SUPPORTED;
9261 case RTE_ETH_FILTER_ADD:
9262 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
9264 case RTE_ETH_FILTER_DELETE:
9265 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
9268 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9269 ret = I40E_ERR_PARAM;
9276 /* Get the symmetric hash enable configurations per port */
9278 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
9280 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9282 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
9285 /* Set the symmetric hash enable configurations per port */
9287 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
9289 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9292 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
9294 "Symmetric hash has already been enabled");
9297 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9299 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
9301 "Symmetric hash has already been disabled");
9304 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9306 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9307 I40E_WRITE_FLUSH(hw);
9311 * Get global configurations of hash function type and symmetric hash enable
9312 * per flow type (pctype). Note that global configuration means it affects all
9313 * the ports on the same NIC.
9316 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
9317 struct rte_eth_hash_global_conf *g_cfg)
9319 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9323 memset(g_cfg, 0, sizeof(*g_cfg));
9324 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9325 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
9326 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
9328 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
9329 PMD_DRV_LOG(DEBUG, "Hash function is %s",
9330 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
9333 * As i40e supports less than 64 flow types, only first 64 bits need to
9336 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9337 g_cfg->valid_bit_mask[i] = 0ULL;
9338 g_cfg->sym_hash_enable_mask[i] = 0ULL;
9341 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
9343 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
9344 if (!adapter->pctypes_tbl[i])
9346 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9347 j < I40E_FILTER_PCTYPE_MAX; j++) {
9348 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
9349 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
9350 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
9351 g_cfg->sym_hash_enable_mask[0] |=
9362 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
9363 const struct rte_eth_hash_global_conf *g_cfg)
9366 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
9368 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
9369 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
9370 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
9371 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
9377 * As i40e supports less than 64 flow types, only first 64 bits need to
9380 mask0 = g_cfg->valid_bit_mask[0];
9381 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9383 /* Check if any unsupported flow type configured */
9384 if ((mask0 | i40e_mask) ^ i40e_mask)
9387 if (g_cfg->valid_bit_mask[i])
9395 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
9401 * Set global configurations of hash function type and symmetric hash enable
9402 * per flow type (pctype). Note any modifying global configuration will affect
9403 * all the ports on the same NIC.
9406 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9407 struct rte_eth_hash_global_conf *g_cfg)
9409 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9410 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9414 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9416 if (pf->support_multi_driver) {
9417 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9421 /* Check the input parameters */
9422 ret = i40e_hash_global_config_check(adapter, g_cfg);
9427 * As i40e supports less than 64 flow types, only first 64 bits need to
9430 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9431 if (mask0 & (1UL << i)) {
9432 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9433 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9435 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9436 j < I40E_FILTER_PCTYPE_MAX; j++) {
9437 if (adapter->pctypes_tbl[i] & (1ULL << j))
9438 i40e_write_global_rx_ctl(hw,
9445 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9446 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9448 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9450 "Hash function already set to Toeplitz");
9453 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9454 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9456 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9458 "Hash function already set to Simple XOR");
9461 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9463 /* Use the default, and keep it as it is */
9466 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9469 I40E_WRITE_FLUSH(hw);
9475 * Valid input sets for hash and flow director filters per PCTYPE
9478 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9479 enum rte_filter_type filter)
9483 static const uint64_t valid_hash_inset_table[] = {
9484 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9485 I40E_INSET_DMAC | I40E_INSET_SMAC |
9486 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9487 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9488 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9489 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9490 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9491 I40E_INSET_FLEX_PAYLOAD,
9492 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9493 I40E_INSET_DMAC | I40E_INSET_SMAC |
9494 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9495 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9496 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9497 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9498 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9499 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9500 I40E_INSET_FLEX_PAYLOAD,
9501 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9502 I40E_INSET_DMAC | I40E_INSET_SMAC |
9503 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9504 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9505 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9506 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9507 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9508 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9509 I40E_INSET_FLEX_PAYLOAD,
9510 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9511 I40E_INSET_DMAC | I40E_INSET_SMAC |
9512 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9513 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9514 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9515 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9516 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9517 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9518 I40E_INSET_FLEX_PAYLOAD,
9519 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9520 I40E_INSET_DMAC | I40E_INSET_SMAC |
9521 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9522 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9523 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9524 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9525 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9526 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9527 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9528 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9529 I40E_INSET_DMAC | I40E_INSET_SMAC |
9530 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9531 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9532 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9533 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9534 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9535 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9536 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9537 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9538 I40E_INSET_DMAC | I40E_INSET_SMAC |
9539 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9540 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9541 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9542 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9543 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9544 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9545 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9546 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9547 I40E_INSET_DMAC | I40E_INSET_SMAC |
9548 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9549 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9550 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9551 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9552 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9553 I40E_INSET_FLEX_PAYLOAD,
9554 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9555 I40E_INSET_DMAC | I40E_INSET_SMAC |
9556 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9557 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9558 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9559 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9560 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9561 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9562 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9563 I40E_INSET_DMAC | I40E_INSET_SMAC |
9564 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9565 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9566 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9567 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9568 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9569 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9570 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9571 I40E_INSET_DMAC | I40E_INSET_SMAC |
9572 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9573 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9574 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9575 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9576 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9577 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9578 I40E_INSET_FLEX_PAYLOAD,
9579 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9580 I40E_INSET_DMAC | I40E_INSET_SMAC |
9581 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9582 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9583 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9584 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9585 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9586 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9587 I40E_INSET_FLEX_PAYLOAD,
9588 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9589 I40E_INSET_DMAC | I40E_INSET_SMAC |
9590 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9591 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9592 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9593 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9594 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9595 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9596 I40E_INSET_FLEX_PAYLOAD,
9597 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9598 I40E_INSET_DMAC | I40E_INSET_SMAC |
9599 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9600 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9601 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9602 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9603 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9604 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9605 I40E_INSET_FLEX_PAYLOAD,
9606 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9607 I40E_INSET_DMAC | I40E_INSET_SMAC |
9608 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9609 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9610 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9611 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9612 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9613 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9614 I40E_INSET_FLEX_PAYLOAD,
9615 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9616 I40E_INSET_DMAC | I40E_INSET_SMAC |
9617 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9618 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9619 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9620 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9621 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9622 I40E_INSET_FLEX_PAYLOAD,
9623 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9624 I40E_INSET_DMAC | I40E_INSET_SMAC |
9625 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9626 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9627 I40E_INSET_FLEX_PAYLOAD,
9631 * Flow director supports only fields defined in
9632 * union rte_eth_fdir_flow.
9634 static const uint64_t valid_fdir_inset_table[] = {
9635 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9636 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9637 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9638 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9639 I40E_INSET_IPV4_TTL,
9640 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9641 I40E_INSET_DMAC | I40E_INSET_SMAC |
9642 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9643 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9644 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9645 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9646 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9647 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9648 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9649 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9650 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9651 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9652 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9653 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9654 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9655 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9656 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9657 I40E_INSET_DMAC | I40E_INSET_SMAC |
9658 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9659 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9660 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9661 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9662 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9663 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9664 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9665 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9666 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9667 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9668 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9669 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9670 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9671 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9673 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9674 I40E_INSET_DMAC | I40E_INSET_SMAC |
9675 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9676 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9677 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9678 I40E_INSET_IPV4_TTL,
9679 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9680 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9681 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9682 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9683 I40E_INSET_IPV6_HOP_LIMIT,
9684 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9685 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9686 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9687 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9688 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9689 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9690 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9691 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9692 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9693 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9694 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9695 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9696 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9697 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9698 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9699 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9700 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9701 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9702 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9703 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9704 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9705 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9706 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9707 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9708 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9709 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9710 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9711 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9712 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9713 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9715 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9716 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9717 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9718 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9719 I40E_INSET_IPV6_HOP_LIMIT,
9720 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9721 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9722 I40E_INSET_LAST_ETHER_TYPE,
9725 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9727 if (filter == RTE_ETH_FILTER_HASH)
9728 valid = valid_hash_inset_table[pctype];
9730 valid = valid_fdir_inset_table[pctype];
9736 * Validate if the input set is allowed for a specific PCTYPE
9739 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9740 enum rte_filter_type filter, uint64_t inset)
9744 valid = i40e_get_valid_input_set(pctype, filter);
9745 if (inset & (~valid))
9751 /* default input set fields combination per pctype */
9753 i40e_get_default_input_set(uint16_t pctype)
9755 static const uint64_t default_inset_table[] = {
9756 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9757 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9758 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9759 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9760 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9761 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9762 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9763 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9764 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9765 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9766 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9767 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9768 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9769 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9770 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9771 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9772 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9773 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9774 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9775 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9777 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9778 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9779 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9780 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9781 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9782 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9783 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9784 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9785 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9786 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9787 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9788 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9789 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9790 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9791 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9792 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9793 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9794 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9795 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9796 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9797 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9798 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9800 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9801 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9802 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9803 I40E_INSET_LAST_ETHER_TYPE,
9806 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9809 return default_inset_table[pctype];
9813 * Parse the input set from index to logical bit masks
9816 i40e_parse_input_set(uint64_t *inset,
9817 enum i40e_filter_pctype pctype,
9818 enum rte_eth_input_set_field *field,
9824 static const struct {
9825 enum rte_eth_input_set_field field;
9827 } inset_convert_table[] = {
9828 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9829 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9830 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9831 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9832 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9833 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9834 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9835 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9836 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9837 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9838 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9839 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9840 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9841 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9842 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9843 I40E_INSET_IPV6_NEXT_HDR},
9844 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9845 I40E_INSET_IPV6_HOP_LIMIT},
9846 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9847 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9848 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9849 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9850 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9851 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9852 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9853 I40E_INSET_SCTP_VT},
9854 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9855 I40E_INSET_TUNNEL_DMAC},
9856 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9857 I40E_INSET_VLAN_TUNNEL},
9858 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9859 I40E_INSET_TUNNEL_ID},
9860 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9861 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9862 I40E_INSET_FLEX_PAYLOAD_W1},
9863 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9864 I40E_INSET_FLEX_PAYLOAD_W2},
9865 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9866 I40E_INSET_FLEX_PAYLOAD_W3},
9867 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9868 I40E_INSET_FLEX_PAYLOAD_W4},
9869 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9870 I40E_INSET_FLEX_PAYLOAD_W5},
9871 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9872 I40E_INSET_FLEX_PAYLOAD_W6},
9873 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9874 I40E_INSET_FLEX_PAYLOAD_W7},
9875 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9876 I40E_INSET_FLEX_PAYLOAD_W8},
9879 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9882 /* Only one item allowed for default or all */
9884 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9885 *inset = i40e_get_default_input_set(pctype);
9887 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9888 *inset = I40E_INSET_NONE;
9893 for (i = 0, *inset = 0; i < size; i++) {
9894 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9895 if (field[i] == inset_convert_table[j].field) {
9896 *inset |= inset_convert_table[j].inset;
9901 /* It contains unsupported input set, return immediately */
9902 if (j == RTE_DIM(inset_convert_table))
9910 * Translate the input set from bit masks to register aware bit masks
9914 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9924 static const struct inset_map inset_map_common[] = {
9925 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9926 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9927 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9928 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9929 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9930 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9931 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9932 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9933 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9934 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9935 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9936 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9937 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9938 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9939 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9940 {I40E_INSET_TUNNEL_DMAC,
9941 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9942 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9943 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9944 {I40E_INSET_TUNNEL_SRC_PORT,
9945 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9946 {I40E_INSET_TUNNEL_DST_PORT,
9947 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9948 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9949 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9950 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9951 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9952 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9953 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9954 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9955 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9956 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9959 /* some different registers map in x722*/
9960 static const struct inset_map inset_map_diff_x722[] = {
9961 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9962 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9963 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9964 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9967 static const struct inset_map inset_map_diff_not_x722[] = {
9968 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9969 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9970 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9971 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9977 /* Translate input set to register aware inset */
9978 if (type == I40E_MAC_X722) {
9979 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9980 if (input & inset_map_diff_x722[i].inset)
9981 val |= inset_map_diff_x722[i].inset_reg;
9984 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9985 if (input & inset_map_diff_not_x722[i].inset)
9986 val |= inset_map_diff_not_x722[i].inset_reg;
9990 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9991 if (input & inset_map_common[i].inset)
9992 val |= inset_map_common[i].inset_reg;
9999 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
10001 uint8_t i, idx = 0;
10002 uint64_t inset_need_mask = inset;
10004 static const struct {
10007 } inset_mask_map[] = {
10008 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
10009 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
10010 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
10011 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
10012 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
10013 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
10014 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
10015 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
10018 if (!inset || !mask || !nb_elem)
10021 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
10022 /* Clear the inset bit, if no MASK is required,
10023 * for example proto + ttl
10025 if ((inset & inset_mask_map[i].inset) ==
10026 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
10027 inset_need_mask &= ~inset_mask_map[i].inset;
10028 if (!inset_need_mask)
10031 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
10032 if ((inset_need_mask & inset_mask_map[i].inset) ==
10033 inset_mask_map[i].inset) {
10034 if (idx >= nb_elem) {
10035 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
10038 mask[idx] = inset_mask_map[i].mask;
10047 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
10049 uint32_t reg = i40e_read_rx_ctl(hw, addr);
10051 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
10053 i40e_write_rx_ctl(hw, addr, val);
10054 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
10055 (uint32_t)i40e_read_rx_ctl(hw, addr));
10059 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
10061 uint32_t reg = i40e_read_rx_ctl(hw, addr);
10062 struct rte_eth_dev *dev;
10064 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
10066 i40e_write_rx_ctl(hw, addr, val);
10067 PMD_DRV_LOG(WARNING,
10068 "i40e device %s changed global register [0x%08x]."
10069 " original: 0x%08x, new: 0x%08x",
10070 dev->device->name, addr, reg,
10071 (uint32_t)i40e_read_rx_ctl(hw, addr));
10076 i40e_filter_input_set_init(struct i40e_pf *pf)
10078 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10079 enum i40e_filter_pctype pctype;
10080 uint64_t input_set, inset_reg;
10081 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10083 uint16_t flow_type;
10085 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
10086 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
10087 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
10089 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
10092 input_set = i40e_get_default_input_set(pctype);
10094 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10095 I40E_INSET_MASK_NUM_REG);
10098 if (pf->support_multi_driver && num > 0) {
10099 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
10102 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
10105 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10106 (uint32_t)(inset_reg & UINT32_MAX));
10107 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10108 (uint32_t)((inset_reg >>
10109 I40E_32_BIT_WIDTH) & UINT32_MAX));
10110 if (!pf->support_multi_driver) {
10111 i40e_check_write_global_reg(hw,
10112 I40E_GLQF_HASH_INSET(0, pctype),
10113 (uint32_t)(inset_reg & UINT32_MAX));
10114 i40e_check_write_global_reg(hw,
10115 I40E_GLQF_HASH_INSET(1, pctype),
10116 (uint32_t)((inset_reg >>
10117 I40E_32_BIT_WIDTH) & UINT32_MAX));
10119 for (i = 0; i < num; i++) {
10120 i40e_check_write_global_reg(hw,
10121 I40E_GLQF_FD_MSK(i, pctype),
10123 i40e_check_write_global_reg(hw,
10124 I40E_GLQF_HASH_MSK(i, pctype),
10127 /*clear unused mask registers of the pctype */
10128 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
10129 i40e_check_write_global_reg(hw,
10130 I40E_GLQF_FD_MSK(i, pctype),
10132 i40e_check_write_global_reg(hw,
10133 I40E_GLQF_HASH_MSK(i, pctype),
10137 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
10139 I40E_WRITE_FLUSH(hw);
10141 /* store the default input set */
10142 if (!pf->support_multi_driver)
10143 pf->hash_input_set[pctype] = input_set;
10144 pf->fdir.input_set[pctype] = input_set;
10149 i40e_hash_filter_inset_select(struct i40e_hw *hw,
10150 struct rte_eth_input_set_conf *conf)
10152 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
10153 enum i40e_filter_pctype pctype;
10154 uint64_t input_set, inset_reg = 0;
10155 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10159 PMD_DRV_LOG(ERR, "Invalid pointer");
10162 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10163 conf->op != RTE_ETH_INPUT_SET_ADD) {
10164 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10168 if (pf->support_multi_driver) {
10169 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
10173 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10174 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10175 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10179 if (hw->mac.type == I40E_MAC_X722) {
10180 /* get translated pctype value in fd pctype register */
10181 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
10182 I40E_GLQF_FD_PCTYPES((int)pctype));
10185 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10188 PMD_DRV_LOG(ERR, "Failed to parse input set");
10192 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
10193 /* get inset value in register */
10194 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
10195 inset_reg <<= I40E_32_BIT_WIDTH;
10196 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
10197 input_set |= pf->hash_input_set[pctype];
10199 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10200 I40E_INSET_MASK_NUM_REG);
10204 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10206 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
10207 (uint32_t)(inset_reg & UINT32_MAX));
10208 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
10209 (uint32_t)((inset_reg >>
10210 I40E_32_BIT_WIDTH) & UINT32_MAX));
10212 for (i = 0; i < num; i++)
10213 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10215 /*clear unused mask registers of the pctype */
10216 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10217 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10219 I40E_WRITE_FLUSH(hw);
10221 pf->hash_input_set[pctype] = input_set;
10226 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
10227 struct rte_eth_input_set_conf *conf)
10229 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10230 enum i40e_filter_pctype pctype;
10231 uint64_t input_set, inset_reg = 0;
10232 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10235 if (!hw || !conf) {
10236 PMD_DRV_LOG(ERR, "Invalid pointer");
10239 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10240 conf->op != RTE_ETH_INPUT_SET_ADD) {
10241 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10245 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10247 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10248 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10252 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10255 PMD_DRV_LOG(ERR, "Failed to parse input set");
10259 /* get inset value in register */
10260 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
10261 inset_reg <<= I40E_32_BIT_WIDTH;
10262 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
10264 /* Can not change the inset reg for flex payload for fdir,
10265 * it is done by writing I40E_PRTQF_FD_FLXINSET
10266 * in i40e_set_flex_mask_on_pctype.
10268 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
10269 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
10271 input_set |= pf->fdir.input_set[pctype];
10272 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10273 I40E_INSET_MASK_NUM_REG);
10276 if (pf->support_multi_driver && num > 0) {
10277 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10281 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10283 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10284 (uint32_t)(inset_reg & UINT32_MAX));
10285 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10286 (uint32_t)((inset_reg >>
10287 I40E_32_BIT_WIDTH) & UINT32_MAX));
10289 if (!pf->support_multi_driver) {
10290 for (i = 0; i < num; i++)
10291 i40e_check_write_global_reg(hw,
10292 I40E_GLQF_FD_MSK(i, pctype),
10294 /*clear unused mask registers of the pctype */
10295 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10296 i40e_check_write_global_reg(hw,
10297 I40E_GLQF_FD_MSK(i, pctype),
10300 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10302 I40E_WRITE_FLUSH(hw);
10304 pf->fdir.input_set[pctype] = input_set;
10309 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10313 if (!hw || !info) {
10314 PMD_DRV_LOG(ERR, "Invalid pointer");
10318 switch (info->info_type) {
10319 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10320 i40e_get_symmetric_hash_enable_per_port(hw,
10321 &(info->info.enable));
10323 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10324 ret = i40e_get_hash_filter_global_config(hw,
10325 &(info->info.global_conf));
10328 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10338 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10342 if (!hw || !info) {
10343 PMD_DRV_LOG(ERR, "Invalid pointer");
10347 switch (info->info_type) {
10348 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10349 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
10351 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10352 ret = i40e_set_hash_filter_global_config(hw,
10353 &(info->info.global_conf));
10355 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
10356 ret = i40e_hash_filter_inset_select(hw,
10357 &(info->info.input_set_conf));
10361 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10370 /* Operations for hash function */
10372 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
10373 enum rte_filter_op filter_op,
10376 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10379 switch (filter_op) {
10380 case RTE_ETH_FILTER_NOP:
10382 case RTE_ETH_FILTER_GET:
10383 ret = i40e_hash_filter_get(hw,
10384 (struct rte_eth_hash_filter_info *)arg);
10386 case RTE_ETH_FILTER_SET:
10387 ret = i40e_hash_filter_set(hw,
10388 (struct rte_eth_hash_filter_info *)arg);
10391 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
10400 /* Convert ethertype filter structure */
10402 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
10403 struct i40e_ethertype_filter *filter)
10405 rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
10406 RTE_ETHER_ADDR_LEN);
10407 filter->input.ether_type = input->ether_type;
10408 filter->flags = input->flags;
10409 filter->queue = input->queue;
10414 /* Check if there exists the ehtertype filter */
10415 struct i40e_ethertype_filter *
10416 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10417 const struct i40e_ethertype_filter_input *input)
10421 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10425 return ethertype_rule->hash_map[ret];
10428 /* Add ethertype filter in SW list */
10430 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10431 struct i40e_ethertype_filter *filter)
10433 struct i40e_ethertype_rule *rule = &pf->ethertype;
10436 ret = rte_hash_add_key(rule->hash_table, &filter->input);
10439 "Failed to insert ethertype filter"
10440 " to hash table %d!",
10444 rule->hash_map[ret] = filter;
10446 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10451 /* Delete ethertype filter in SW list */
10453 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10454 struct i40e_ethertype_filter_input *input)
10456 struct i40e_ethertype_rule *rule = &pf->ethertype;
10457 struct i40e_ethertype_filter *filter;
10460 ret = rte_hash_del_key(rule->hash_table, input);
10463 "Failed to delete ethertype filter"
10464 " to hash table %d!",
10468 filter = rule->hash_map[ret];
10469 rule->hash_map[ret] = NULL;
10471 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10478 * Configure ethertype filter, which can director packet by filtering
10479 * with mac address and ether_type or only ether_type
10482 i40e_ethertype_filter_set(struct i40e_pf *pf,
10483 struct rte_eth_ethertype_filter *filter,
10486 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10487 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10488 struct i40e_ethertype_filter *ethertype_filter, *node;
10489 struct i40e_ethertype_filter check_filter;
10490 struct i40e_control_filter_stats stats;
10491 uint16_t flags = 0;
10494 if (filter->queue >= pf->dev_data->nb_rx_queues) {
10495 PMD_DRV_LOG(ERR, "Invalid queue ID");
10498 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10499 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10501 "unsupported ether_type(0x%04x) in control packet filter.",
10502 filter->ether_type);
10505 if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10506 PMD_DRV_LOG(WARNING,
10507 "filter vlan ether_type in first tag is not supported.");
10509 /* Check if there is the filter in SW list */
10510 memset(&check_filter, 0, sizeof(check_filter));
10511 i40e_ethertype_filter_convert(filter, &check_filter);
10512 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10513 &check_filter.input);
10515 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10519 if (!add && !node) {
10520 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10524 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10525 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10526 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10527 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10528 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10530 memset(&stats, 0, sizeof(stats));
10531 ret = i40e_aq_add_rem_control_packet_filter(hw,
10532 filter->mac_addr.addr_bytes,
10533 filter->ether_type, flags,
10534 pf->main_vsi->seid,
10535 filter->queue, add, &stats, NULL);
10538 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10539 ret, stats.mac_etype_used, stats.etype_used,
10540 stats.mac_etype_free, stats.etype_free);
10544 /* Add or delete a filter in SW list */
10546 ethertype_filter = rte_zmalloc("ethertype_filter",
10547 sizeof(*ethertype_filter), 0);
10548 if (ethertype_filter == NULL) {
10549 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10553 rte_memcpy(ethertype_filter, &check_filter,
10554 sizeof(check_filter));
10555 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10557 rte_free(ethertype_filter);
10559 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10566 * Handle operations for ethertype filter.
10569 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10570 enum rte_filter_op filter_op,
10573 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10576 if (filter_op == RTE_ETH_FILTER_NOP)
10580 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10585 switch (filter_op) {
10586 case RTE_ETH_FILTER_ADD:
10587 ret = i40e_ethertype_filter_set(pf,
10588 (struct rte_eth_ethertype_filter *)arg,
10591 case RTE_ETH_FILTER_DELETE:
10592 ret = i40e_ethertype_filter_set(pf,
10593 (struct rte_eth_ethertype_filter *)arg,
10597 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10605 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10606 enum rte_filter_type filter_type,
10607 enum rte_filter_op filter_op,
10615 switch (filter_type) {
10616 case RTE_ETH_FILTER_NONE:
10617 /* For global configuration */
10618 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10620 case RTE_ETH_FILTER_HASH:
10621 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10623 case RTE_ETH_FILTER_MACVLAN:
10624 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10626 case RTE_ETH_FILTER_ETHERTYPE:
10627 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10629 case RTE_ETH_FILTER_TUNNEL:
10630 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10632 case RTE_ETH_FILTER_FDIR:
10633 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10635 case RTE_ETH_FILTER_GENERIC:
10636 if (filter_op != RTE_ETH_FILTER_GET)
10638 *(const void **)arg = &i40e_flow_ops;
10641 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10651 * Check and enable Extended Tag.
10652 * Enabling Extended Tag is important for 40G performance.
10655 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10657 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10661 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10664 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10668 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10669 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10674 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10677 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10681 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10682 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10685 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10686 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10689 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10696 * As some registers wouldn't be reset unless a global hardware reset,
10697 * hardware initialization is needed to put those registers into an
10698 * expected initial state.
10701 i40e_hw_init(struct rte_eth_dev *dev)
10703 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10705 i40e_enable_extended_tag(dev);
10707 /* clear the PF Queue Filter control register */
10708 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10710 /* Disable symmetric hash per port */
10711 i40e_set_symmetric_hash_enable_per_port(hw, 0);
10715 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10716 * however this function will return only one highest pctype index,
10717 * which is not quite correct. This is known problem of i40e driver
10718 * and needs to be fixed later.
10720 enum i40e_filter_pctype
10721 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10724 uint64_t pctype_mask;
10726 if (flow_type < I40E_FLOW_TYPE_MAX) {
10727 pctype_mask = adapter->pctypes_tbl[flow_type];
10728 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10729 if (pctype_mask & (1ULL << i))
10730 return (enum i40e_filter_pctype)i;
10733 return I40E_FILTER_PCTYPE_INVALID;
10737 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10738 enum i40e_filter_pctype pctype)
10741 uint64_t pctype_mask = 1ULL << pctype;
10743 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10745 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10749 return RTE_ETH_FLOW_UNKNOWN;
10753 * On X710, performance number is far from the expectation on recent firmware
10754 * versions; on XL710, performance number is also far from the expectation on
10755 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10756 * mode is enabled and port MAC address is equal to the packet destination MAC
10757 * address. The fix for this issue may not be integrated in the following
10758 * firmware version. So the workaround in software driver is needed. It needs
10759 * to modify the initial values of 3 internal only registers for both X710 and
10760 * XL710. Note that the values for X710 or XL710 could be different, and the
10761 * workaround can be removed when it is fixed in firmware in the future.
10764 /* For both X710 and XL710 */
10765 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10766 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10767 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10769 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10770 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10773 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10774 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10777 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10779 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10780 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10783 * GL_SWR_PM_UP_THR:
10784 * The value is not impacted from the link speed, its value is set according
10785 * to the total number of ports for a better pipe-monitor configuration.
10788 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10790 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10791 .device_id = (dev), \
10792 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10794 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10795 .device_id = (dev), \
10796 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10798 static const struct {
10799 uint16_t device_id;
10801 } swr_pm_table[] = {
10802 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10803 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10804 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10805 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10806 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10808 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10809 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10810 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10811 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10812 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10813 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10814 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10818 if (value == NULL) {
10819 PMD_DRV_LOG(ERR, "value is NULL");
10823 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10824 if (hw->device_id == swr_pm_table[i].device_id) {
10825 *value = swr_pm_table[i].val;
10827 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10829 hw->device_id, *value);
10838 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10840 enum i40e_status_code status;
10841 struct i40e_aq_get_phy_abilities_resp phy_ab;
10842 int ret = -ENOTSUP;
10845 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10849 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10852 rte_delay_us(100000);
10854 status = i40e_aq_get_phy_capabilities(hw, false,
10855 true, &phy_ab, NULL);
10863 i40e_configure_registers(struct i40e_hw *hw)
10869 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10870 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10871 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10877 for (i = 0; i < RTE_DIM(reg_table); i++) {
10878 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10879 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10881 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10882 else /* For X710/XL710/XXV710 */
10883 if (hw->aq.fw_maj_ver < 6)
10885 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10888 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10891 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10892 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10894 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10895 else /* For X710/XL710/XXV710 */
10897 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10900 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10903 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10904 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10905 "GL_SWR_PM_UP_THR value fixup",
10910 reg_table[i].val = cfg_val;
10913 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10916 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10917 reg_table[i].addr);
10920 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10921 reg_table[i].addr, reg);
10922 if (reg == reg_table[i].val)
10925 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10926 reg_table[i].val, NULL);
10929 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10930 reg_table[i].val, reg_table[i].addr);
10933 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10934 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10938 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10939 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10940 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10942 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10947 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10948 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10952 /* Configure for double VLAN RX stripping */
10953 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10954 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10955 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10956 ret = i40e_aq_debug_write_register(hw,
10957 I40E_VSI_TSR(vsi->vsi_id),
10960 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10962 return I40E_ERR_CONFIG;
10966 /* Configure for double VLAN TX insertion */
10967 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10968 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10969 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10970 ret = i40e_aq_debug_write_register(hw,
10971 I40E_VSI_L2TAGSTXVALID(
10972 vsi->vsi_id), reg, NULL);
10975 "Failed to update VSI_L2TAGSTXVALID[%d]",
10977 return I40E_ERR_CONFIG;
10985 * i40e_aq_add_mirror_rule
10986 * @hw: pointer to the hardware structure
10987 * @seid: VEB seid to add mirror rule to
10988 * @dst_id: destination vsi seid
10989 * @entries: Buffer which contains the entities to be mirrored
10990 * @count: number of entities contained in the buffer
10991 * @rule_id:the rule_id of the rule to be added
10993 * Add a mirror rule for a given veb.
10996 static enum i40e_status_code
10997 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10998 uint16_t seid, uint16_t dst_id,
10999 uint16_t rule_type, uint16_t *entries,
11000 uint16_t count, uint16_t *rule_id)
11002 struct i40e_aq_desc desc;
11003 struct i40e_aqc_add_delete_mirror_rule cmd;
11004 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
11005 (struct i40e_aqc_add_delete_mirror_rule_completion *)
11008 enum i40e_status_code status;
11010 i40e_fill_default_direct_cmd_desc(&desc,
11011 i40e_aqc_opc_add_mirror_rule);
11012 memset(&cmd, 0, sizeof(cmd));
11014 buff_len = sizeof(uint16_t) * count;
11015 desc.datalen = rte_cpu_to_le_16(buff_len);
11017 desc.flags |= rte_cpu_to_le_16(
11018 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
11019 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
11020 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
11021 cmd.num_entries = rte_cpu_to_le_16(count);
11022 cmd.seid = rte_cpu_to_le_16(seid);
11023 cmd.destination = rte_cpu_to_le_16(dst_id);
11025 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
11026 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
11028 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
11029 hw->aq.asq_last_status, resp->rule_id,
11030 resp->mirror_rules_used, resp->mirror_rules_free);
11031 *rule_id = rte_le_to_cpu_16(resp->rule_id);
11037 * i40e_aq_del_mirror_rule
11038 * @hw: pointer to the hardware structure
11039 * @seid: VEB seid to add mirror rule to
11040 * @entries: Buffer which contains the entities to be mirrored
11041 * @count: number of entities contained in the buffer
11042 * @rule_id:the rule_id of the rule to be delete
11044 * Delete a mirror rule for a given veb.
11047 static enum i40e_status_code
11048 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
11049 uint16_t seid, uint16_t rule_type, uint16_t *entries,
11050 uint16_t count, uint16_t rule_id)
11052 struct i40e_aq_desc desc;
11053 struct i40e_aqc_add_delete_mirror_rule cmd;
11054 uint16_t buff_len = 0;
11055 enum i40e_status_code status;
11058 i40e_fill_default_direct_cmd_desc(&desc,
11059 i40e_aqc_opc_delete_mirror_rule);
11060 memset(&cmd, 0, sizeof(cmd));
11061 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
11062 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
11064 cmd.num_entries = count;
11065 buff_len = sizeof(uint16_t) * count;
11066 desc.datalen = rte_cpu_to_le_16(buff_len);
11067 buff = (void *)entries;
11069 /* rule id is filled in destination field for deleting mirror rule */
11070 cmd.destination = rte_cpu_to_le_16(rule_id);
11072 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
11073 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
11074 cmd.seid = rte_cpu_to_le_16(seid);
11076 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
11077 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
11083 * i40e_mirror_rule_set
11084 * @dev: pointer to the hardware structure
11085 * @mirror_conf: mirror rule info
11086 * @sw_id: mirror rule's sw_id
11087 * @on: enable/disable
11089 * set a mirror rule.
11093 i40e_mirror_rule_set(struct rte_eth_dev *dev,
11094 struct rte_eth_mirror_conf *mirror_conf,
11095 uint8_t sw_id, uint8_t on)
11097 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11098 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11099 struct i40e_mirror_rule *it, *mirr_rule = NULL;
11100 struct i40e_mirror_rule *parent = NULL;
11101 uint16_t seid, dst_seid, rule_id;
11105 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
11107 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
11109 "mirror rule can not be configured without veb or vfs.");
11112 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
11113 PMD_DRV_LOG(ERR, "mirror table is full.");
11116 if (mirror_conf->dst_pool > pf->vf_num) {
11117 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
11118 mirror_conf->dst_pool);
11122 seid = pf->main_vsi->veb->seid;
11124 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11125 if (sw_id <= it->index) {
11131 if (mirr_rule && sw_id == mirr_rule->index) {
11133 PMD_DRV_LOG(ERR, "mirror rule exists.");
11136 ret = i40e_aq_del_mirror_rule(hw, seid,
11137 mirr_rule->rule_type,
11138 mirr_rule->entries,
11139 mirr_rule->num_entries, mirr_rule->id);
11142 "failed to remove mirror rule: ret = %d, aq_err = %d.",
11143 ret, hw->aq.asq_last_status);
11146 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11147 rte_free(mirr_rule);
11148 pf->nb_mirror_rule--;
11152 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11156 mirr_rule = rte_zmalloc("i40e_mirror_rule",
11157 sizeof(struct i40e_mirror_rule) , 0);
11159 PMD_DRV_LOG(ERR, "failed to allocate memory");
11160 return I40E_ERR_NO_MEMORY;
11162 switch (mirror_conf->rule_type) {
11163 case ETH_MIRROR_VLAN:
11164 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
11165 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
11166 mirr_rule->entries[j] =
11167 mirror_conf->vlan.vlan_id[i];
11172 PMD_DRV_LOG(ERR, "vlan is not specified.");
11173 rte_free(mirr_rule);
11176 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
11178 case ETH_MIRROR_VIRTUAL_POOL_UP:
11179 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
11180 /* check if the specified pool bit is out of range */
11181 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
11182 PMD_DRV_LOG(ERR, "pool mask is out of range.");
11183 rte_free(mirr_rule);
11186 for (i = 0, j = 0; i < pf->vf_num; i++) {
11187 if (mirror_conf->pool_mask & (1ULL << i)) {
11188 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
11192 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
11193 /* add pf vsi to entries */
11194 mirr_rule->entries[j] = pf->main_vsi_seid;
11198 PMD_DRV_LOG(ERR, "pool is not specified.");
11199 rte_free(mirr_rule);
11202 /* egress and ingress in aq commands means from switch but not port */
11203 mirr_rule->rule_type =
11204 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
11205 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
11206 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
11208 case ETH_MIRROR_UPLINK_PORT:
11209 /* egress and ingress in aq commands means from switch but not port*/
11210 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
11212 case ETH_MIRROR_DOWNLINK_PORT:
11213 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
11216 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
11217 mirror_conf->rule_type);
11218 rte_free(mirr_rule);
11222 /* If the dst_pool is equal to vf_num, consider it as PF */
11223 if (mirror_conf->dst_pool == pf->vf_num)
11224 dst_seid = pf->main_vsi_seid;
11226 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
11228 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
11229 mirr_rule->rule_type, mirr_rule->entries,
11233 "failed to add mirror rule: ret = %d, aq_err = %d.",
11234 ret, hw->aq.asq_last_status);
11235 rte_free(mirr_rule);
11239 mirr_rule->index = sw_id;
11240 mirr_rule->num_entries = j;
11241 mirr_rule->id = rule_id;
11242 mirr_rule->dst_vsi_seid = dst_seid;
11245 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
11247 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
11249 pf->nb_mirror_rule++;
11254 * i40e_mirror_rule_reset
11255 * @dev: pointer to the device
11256 * @sw_id: mirror rule's sw_id
11258 * reset a mirror rule.
11262 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
11264 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11265 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11266 struct i40e_mirror_rule *it, *mirr_rule = NULL;
11270 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
11272 seid = pf->main_vsi->veb->seid;
11274 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11275 if (sw_id == it->index) {
11281 ret = i40e_aq_del_mirror_rule(hw, seid,
11282 mirr_rule->rule_type,
11283 mirr_rule->entries,
11284 mirr_rule->num_entries, mirr_rule->id);
11287 "failed to remove mirror rule: status = %d, aq_err = %d.",
11288 ret, hw->aq.asq_last_status);
11291 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11292 rte_free(mirr_rule);
11293 pf->nb_mirror_rule--;
11295 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11302 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
11304 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11305 uint64_t systim_cycles;
11307 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
11308 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
11311 return systim_cycles;
11315 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
11317 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11318 uint64_t rx_tstamp;
11320 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
11321 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
11328 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
11330 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11331 uint64_t tx_tstamp;
11333 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
11334 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
11341 i40e_start_timecounters(struct rte_eth_dev *dev)
11343 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11344 struct i40e_adapter *adapter = dev->data->dev_private;
11345 struct rte_eth_link link;
11346 uint32_t tsync_inc_l;
11347 uint32_t tsync_inc_h;
11349 /* Get current link speed. */
11350 i40e_dev_link_update(dev, 1);
11351 rte_eth_linkstatus_get(dev, &link);
11353 switch (link.link_speed) {
11354 case ETH_SPEED_NUM_40G:
11355 case ETH_SPEED_NUM_25G:
11356 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
11357 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
11359 case ETH_SPEED_NUM_10G:
11360 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
11361 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
11363 case ETH_SPEED_NUM_1G:
11364 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
11365 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
11372 /* Set the timesync increment value. */
11373 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
11374 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
11376 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
11377 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11378 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11380 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11381 adapter->systime_tc.cc_shift = 0;
11382 adapter->systime_tc.nsec_mask = 0;
11384 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11385 adapter->rx_tstamp_tc.cc_shift = 0;
11386 adapter->rx_tstamp_tc.nsec_mask = 0;
11388 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11389 adapter->tx_tstamp_tc.cc_shift = 0;
11390 adapter->tx_tstamp_tc.nsec_mask = 0;
11394 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
11396 struct i40e_adapter *adapter = dev->data->dev_private;
11398 adapter->systime_tc.nsec += delta;
11399 adapter->rx_tstamp_tc.nsec += delta;
11400 adapter->tx_tstamp_tc.nsec += delta;
11406 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
11409 struct i40e_adapter *adapter = dev->data->dev_private;
11411 ns = rte_timespec_to_ns(ts);
11413 /* Set the timecounters to a new value. */
11414 adapter->systime_tc.nsec = ns;
11415 adapter->rx_tstamp_tc.nsec = ns;
11416 adapter->tx_tstamp_tc.nsec = ns;
11422 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11424 uint64_t ns, systime_cycles;
11425 struct i40e_adapter *adapter = dev->data->dev_private;
11427 systime_cycles = i40e_read_systime_cyclecounter(dev);
11428 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11429 *ts = rte_ns_to_timespec(ns);
11435 i40e_timesync_enable(struct rte_eth_dev *dev)
11437 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11438 uint32_t tsync_ctl_l;
11439 uint32_t tsync_ctl_h;
11441 /* Stop the timesync system time. */
11442 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11443 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11444 /* Reset the timesync system time value. */
11445 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11446 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11448 i40e_start_timecounters(dev);
11450 /* Clear timesync registers. */
11451 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11452 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11453 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11454 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11455 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11456 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11458 /* Enable timestamping of PTP packets. */
11459 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11460 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11462 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11463 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11464 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11466 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11467 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11473 i40e_timesync_disable(struct rte_eth_dev *dev)
11475 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11476 uint32_t tsync_ctl_l;
11477 uint32_t tsync_ctl_h;
11479 /* Disable timestamping of transmitted PTP packets. */
11480 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11481 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11483 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11484 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11486 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11487 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11489 /* Reset the timesync increment value. */
11490 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11491 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11497 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11498 struct timespec *timestamp, uint32_t flags)
11500 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11501 struct i40e_adapter *adapter = dev->data->dev_private;
11502 uint32_t sync_status;
11503 uint32_t index = flags & 0x03;
11504 uint64_t rx_tstamp_cycles;
11507 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11508 if ((sync_status & (1 << index)) == 0)
11511 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11512 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11513 *timestamp = rte_ns_to_timespec(ns);
11519 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11520 struct timespec *timestamp)
11522 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11523 struct i40e_adapter *adapter = dev->data->dev_private;
11524 uint32_t sync_status;
11525 uint64_t tx_tstamp_cycles;
11528 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11529 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11532 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11533 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11534 *timestamp = rte_ns_to_timespec(ns);
11540 * i40e_parse_dcb_configure - parse dcb configure from user
11541 * @dev: the device being configured
11542 * @dcb_cfg: pointer of the result of parse
11543 * @*tc_map: bit map of enabled traffic classes
11545 * Returns 0 on success, negative value on failure
11548 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11549 struct i40e_dcbx_config *dcb_cfg,
11552 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11553 uint8_t i, tc_bw, bw_lf;
11555 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11557 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11558 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11559 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11563 /* assume each tc has the same bw */
11564 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11565 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11566 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11567 /* to ensure the sum of tcbw is equal to 100 */
11568 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11569 for (i = 0; i < bw_lf; i++)
11570 dcb_cfg->etscfg.tcbwtable[i]++;
11572 /* assume each tc has the same Transmission Selection Algorithm */
11573 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11574 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11576 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11577 dcb_cfg->etscfg.prioritytable[i] =
11578 dcb_rx_conf->dcb_tc[i];
11580 /* FW needs one App to configure HW */
11581 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11582 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11583 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11584 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11586 if (dcb_rx_conf->nb_tcs == 0)
11587 *tc_map = 1; /* tc0 only */
11589 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11591 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11592 dcb_cfg->pfc.willing = 0;
11593 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11594 dcb_cfg->pfc.pfcenable = *tc_map;
11600 static enum i40e_status_code
11601 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11602 struct i40e_aqc_vsi_properties_data *info,
11603 uint8_t enabled_tcmap)
11605 enum i40e_status_code ret;
11606 int i, total_tc = 0;
11607 uint16_t qpnum_per_tc, bsf, qp_idx;
11608 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11609 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11610 uint16_t used_queues;
11612 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11613 if (ret != I40E_SUCCESS)
11616 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11617 if (enabled_tcmap & (1 << i))
11622 vsi->enabled_tc = enabled_tcmap;
11624 /* different VSI has different queues assigned */
11625 if (vsi->type == I40E_VSI_MAIN)
11626 used_queues = dev_data->nb_rx_queues -
11627 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11628 else if (vsi->type == I40E_VSI_VMDQ2)
11629 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11631 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11632 return I40E_ERR_NO_AVAILABLE_VSI;
11635 qpnum_per_tc = used_queues / total_tc;
11636 /* Number of queues per enabled TC */
11637 if (qpnum_per_tc == 0) {
11638 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11639 return I40E_ERR_INVALID_QP_ID;
11641 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11642 I40E_MAX_Q_PER_TC);
11643 bsf = rte_bsf32(qpnum_per_tc);
11646 * Configure TC and queue mapping parameters, for enabled TC,
11647 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11648 * default queue will serve it.
11651 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11652 if (vsi->enabled_tc & (1 << i)) {
11653 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11654 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11655 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11656 qp_idx += qpnum_per_tc;
11658 info->tc_mapping[i] = 0;
11661 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11662 if (vsi->type == I40E_VSI_SRIOV) {
11663 info->mapping_flags |=
11664 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11665 for (i = 0; i < vsi->nb_qps; i++)
11666 info->queue_mapping[i] =
11667 rte_cpu_to_le_16(vsi->base_queue + i);
11669 info->mapping_flags |=
11670 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11671 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11673 info->valid_sections |=
11674 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11676 return I40E_SUCCESS;
11680 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11681 * @veb: VEB to be configured
11682 * @tc_map: enabled TC bitmap
11684 * Returns 0 on success, negative value on failure
11686 static enum i40e_status_code
11687 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11689 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11690 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11691 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11692 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11693 enum i40e_status_code ret = I40E_SUCCESS;
11697 /* Check if enabled_tc is same as existing or new TCs */
11698 if (veb->enabled_tc == tc_map)
11701 /* configure tc bandwidth */
11702 memset(&veb_bw, 0, sizeof(veb_bw));
11703 veb_bw.tc_valid_bits = tc_map;
11704 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11705 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11706 if (tc_map & BIT_ULL(i))
11707 veb_bw.tc_bw_share_credits[i] = 1;
11709 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11713 "AQ command Config switch_comp BW allocation per TC failed = %d",
11714 hw->aq.asq_last_status);
11718 memset(&ets_query, 0, sizeof(ets_query));
11719 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11721 if (ret != I40E_SUCCESS) {
11723 "Failed to get switch_comp ETS configuration %u",
11724 hw->aq.asq_last_status);
11727 memset(&bw_query, 0, sizeof(bw_query));
11728 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11730 if (ret != I40E_SUCCESS) {
11732 "Failed to get switch_comp bandwidth configuration %u",
11733 hw->aq.asq_last_status);
11737 /* store and print out BW info */
11738 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11739 veb->bw_info.bw_max = ets_query.tc_bw_max;
11740 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11741 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11742 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11743 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11744 I40E_16_BIT_WIDTH);
11745 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11746 veb->bw_info.bw_ets_share_credits[i] =
11747 bw_query.tc_bw_share_credits[i];
11748 veb->bw_info.bw_ets_credits[i] =
11749 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11750 /* 4 bits per TC, 4th bit is reserved */
11751 veb->bw_info.bw_ets_max[i] =
11752 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11753 RTE_LEN2MASK(3, uint8_t));
11754 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11755 veb->bw_info.bw_ets_share_credits[i]);
11756 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11757 veb->bw_info.bw_ets_credits[i]);
11758 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11759 veb->bw_info.bw_ets_max[i]);
11762 veb->enabled_tc = tc_map;
11769 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11770 * @vsi: VSI to be configured
11771 * @tc_map: enabled TC bitmap
11773 * Returns 0 on success, negative value on failure
11775 static enum i40e_status_code
11776 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11778 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11779 struct i40e_vsi_context ctxt;
11780 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11781 enum i40e_status_code ret = I40E_SUCCESS;
11784 /* Check if enabled_tc is same as existing or new TCs */
11785 if (vsi->enabled_tc == tc_map)
11788 /* configure tc bandwidth */
11789 memset(&bw_data, 0, sizeof(bw_data));
11790 bw_data.tc_valid_bits = tc_map;
11791 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11792 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11793 if (tc_map & BIT_ULL(i))
11794 bw_data.tc_bw_credits[i] = 1;
11796 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11799 "AQ command Config VSI BW allocation per TC failed = %d",
11800 hw->aq.asq_last_status);
11803 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11804 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11806 /* Update Queue Pairs Mapping for currently enabled UPs */
11807 ctxt.seid = vsi->seid;
11808 ctxt.pf_num = hw->pf_id;
11810 ctxt.uplink_seid = vsi->uplink_seid;
11811 ctxt.info = vsi->info;
11813 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11817 /* Update the VSI after updating the VSI queue-mapping information */
11818 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11820 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11821 hw->aq.asq_last_status);
11824 /* update the local VSI info with updated queue map */
11825 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11826 sizeof(vsi->info.tc_mapping));
11827 rte_memcpy(&vsi->info.queue_mapping,
11828 &ctxt.info.queue_mapping,
11829 sizeof(vsi->info.queue_mapping));
11830 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11831 vsi->info.valid_sections = 0;
11833 /* query and update current VSI BW information */
11834 ret = i40e_vsi_get_bw_config(vsi);
11837 "Failed updating vsi bw info, err %s aq_err %s",
11838 i40e_stat_str(hw, ret),
11839 i40e_aq_str(hw, hw->aq.asq_last_status));
11843 vsi->enabled_tc = tc_map;
11850 * i40e_dcb_hw_configure - program the dcb setting to hw
11851 * @pf: pf the configuration is taken on
11852 * @new_cfg: new configuration
11853 * @tc_map: enabled TC bitmap
11855 * Returns 0 on success, negative value on failure
11857 static enum i40e_status_code
11858 i40e_dcb_hw_configure(struct i40e_pf *pf,
11859 struct i40e_dcbx_config *new_cfg,
11862 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11863 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11864 struct i40e_vsi *main_vsi = pf->main_vsi;
11865 struct i40e_vsi_list *vsi_list;
11866 enum i40e_status_code ret;
11870 /* Use the FW API if FW > v4.4*/
11871 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11872 (hw->aq.fw_maj_ver >= 5))) {
11874 "FW < v4.4, can not use FW LLDP API to configure DCB");
11875 return I40E_ERR_FIRMWARE_API_VERSION;
11878 /* Check if need reconfiguration */
11879 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11880 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11881 return I40E_SUCCESS;
11884 /* Copy the new config to the current config */
11885 *old_cfg = *new_cfg;
11886 old_cfg->etsrec = old_cfg->etscfg;
11887 ret = i40e_set_dcb_config(hw);
11889 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11890 i40e_stat_str(hw, ret),
11891 i40e_aq_str(hw, hw->aq.asq_last_status));
11894 /* set receive Arbiter to RR mode and ETS scheme by default */
11895 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11896 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11897 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11898 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11899 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11900 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11901 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11902 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11903 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11904 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11905 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11906 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11907 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11909 /* get local mib to check whether it is configured correctly */
11911 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11912 /* Get Local DCB Config */
11913 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11914 &hw->local_dcbx_config);
11916 /* if Veb is created, need to update TC of it at first */
11917 if (main_vsi->veb) {
11918 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11920 PMD_INIT_LOG(WARNING,
11921 "Failed configuring TC for VEB seid=%d",
11922 main_vsi->veb->seid);
11924 /* Update each VSI */
11925 i40e_vsi_config_tc(main_vsi, tc_map);
11926 if (main_vsi->veb) {
11927 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11928 /* Beside main VSI and VMDQ VSIs, only enable default
11929 * TC for other VSIs
11931 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11932 ret = i40e_vsi_config_tc(vsi_list->vsi,
11935 ret = i40e_vsi_config_tc(vsi_list->vsi,
11936 I40E_DEFAULT_TCMAP);
11938 PMD_INIT_LOG(WARNING,
11939 "Failed configuring TC for VSI seid=%d",
11940 vsi_list->vsi->seid);
11944 return I40E_SUCCESS;
11948 * i40e_dcb_init_configure - initial dcb config
11949 * @dev: device being configured
11950 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11952 * Returns 0 on success, negative value on failure
11955 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11957 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11958 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11961 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11962 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11966 /* DCB initialization:
11967 * Update DCB configuration from the Firmware and configure
11968 * LLDP MIB change event.
11970 if (sw_dcb == TRUE) {
11971 /* Stopping lldp is necessary for DPDK, but it will cause
11972 * DCB init failed. For i40e_init_dcb(), the prerequisite
11973 * for successful initialization of DCB is that LLDP is
11974 * enabled. So it is needed to start lldp before DCB init
11975 * and stop it after initialization.
11977 ret = i40e_aq_start_lldp(hw, true, NULL);
11978 if (ret != I40E_SUCCESS)
11979 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11981 ret = i40e_init_dcb(hw, true);
11982 /* If lldp agent is stopped, the return value from
11983 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11984 * adminq status. Otherwise, it should return success.
11986 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11987 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11988 memset(&hw->local_dcbx_config, 0,
11989 sizeof(struct i40e_dcbx_config));
11990 /* set dcb default configuration */
11991 hw->local_dcbx_config.etscfg.willing = 0;
11992 hw->local_dcbx_config.etscfg.maxtcs = 0;
11993 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11994 hw->local_dcbx_config.etscfg.tsatable[0] =
11996 /* all UPs mapping to TC0 */
11997 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11998 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11999 hw->local_dcbx_config.etsrec =
12000 hw->local_dcbx_config.etscfg;
12001 hw->local_dcbx_config.pfc.willing = 0;
12002 hw->local_dcbx_config.pfc.pfccap =
12003 I40E_MAX_TRAFFIC_CLASS;
12004 /* FW needs one App to configure HW */
12005 hw->local_dcbx_config.numapps = 1;
12006 hw->local_dcbx_config.app[0].selector =
12007 I40E_APP_SEL_ETHTYPE;
12008 hw->local_dcbx_config.app[0].priority = 3;
12009 hw->local_dcbx_config.app[0].protocolid =
12010 I40E_APP_PROTOID_FCOE;
12011 ret = i40e_set_dcb_config(hw);
12014 "default dcb config fails. err = %d, aq_err = %d.",
12015 ret, hw->aq.asq_last_status);
12020 "DCB initialization in FW fails, err = %d, aq_err = %d.",
12021 ret, hw->aq.asq_last_status);
12025 if (i40e_need_stop_lldp(dev)) {
12026 ret = i40e_aq_stop_lldp(hw, true, true, NULL);
12027 if (ret != I40E_SUCCESS)
12028 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
12031 ret = i40e_aq_start_lldp(hw, true, NULL);
12032 if (ret != I40E_SUCCESS)
12033 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
12035 ret = i40e_init_dcb(hw, true);
12037 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
12039 "HW doesn't support DCBX offload.");
12044 "DCBX configuration failed, err = %d, aq_err = %d.",
12045 ret, hw->aq.asq_last_status);
12053 * i40e_dcb_setup - setup dcb related config
12054 * @dev: device being configured
12056 * Returns 0 on success, negative value on failure
12059 i40e_dcb_setup(struct rte_eth_dev *dev)
12061 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12062 struct i40e_dcbx_config dcb_cfg;
12063 uint8_t tc_map = 0;
12066 if ((pf->flags & I40E_FLAG_DCB) == 0) {
12067 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
12071 if (pf->vf_num != 0)
12072 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
12074 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
12076 PMD_INIT_LOG(ERR, "invalid dcb config");
12079 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
12081 PMD_INIT_LOG(ERR, "dcb sw configure fails");
12089 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
12090 struct rte_eth_dcb_info *dcb_info)
12092 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12093 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12094 struct i40e_vsi *vsi = pf->main_vsi;
12095 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
12096 uint16_t bsf, tc_mapping;
12099 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
12100 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
12102 dcb_info->nb_tcs = 1;
12103 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
12104 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
12105 for (i = 0; i < dcb_info->nb_tcs; i++)
12106 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
12108 /* get queue mapping if vmdq is disabled */
12109 if (!pf->nb_cfg_vmdq_vsi) {
12110 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12111 if (!(vsi->enabled_tc & (1 << i)))
12113 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
12114 dcb_info->tc_queue.tc_rxq[j][i].base =
12115 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
12116 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
12117 dcb_info->tc_queue.tc_txq[j][i].base =
12118 dcb_info->tc_queue.tc_rxq[j][i].base;
12119 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
12120 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
12121 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
12122 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
12123 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
12128 /* get queue mapping if vmdq is enabled */
12130 vsi = pf->vmdq[j].vsi;
12131 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12132 if (!(vsi->enabled_tc & (1 << i)))
12134 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
12135 dcb_info->tc_queue.tc_rxq[j][i].base =
12136 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
12137 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
12138 dcb_info->tc_queue.tc_txq[j][i].base =
12139 dcb_info->tc_queue.tc_rxq[j][i].base;
12140 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
12141 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
12142 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
12143 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
12144 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
12147 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
12152 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
12154 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12155 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12156 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12157 uint16_t msix_intr;
12159 msix_intr = intr_handle->intr_vec[queue_id];
12160 if (msix_intr == I40E_MISC_VEC_ID)
12161 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12162 I40E_PFINT_DYN_CTL0_INTENA_MASK |
12163 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
12164 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12167 I40E_PFINT_DYN_CTLN(msix_intr -
12168 I40E_RX_VEC_START),
12169 I40E_PFINT_DYN_CTLN_INTENA_MASK |
12170 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
12171 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12173 I40E_WRITE_FLUSH(hw);
12174 rte_intr_ack(&pci_dev->intr_handle);
12180 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
12182 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12183 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12184 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12185 uint16_t msix_intr;
12187 msix_intr = intr_handle->intr_vec[queue_id];
12188 if (msix_intr == I40E_MISC_VEC_ID)
12189 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12190 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12193 I40E_PFINT_DYN_CTLN(msix_intr -
12194 I40E_RX_VEC_START),
12195 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12196 I40E_WRITE_FLUSH(hw);
12202 * This function is used to check if the register is valid.
12203 * Below is the valid registers list for X722 only:
12207 * 0x208e00--0x209000
12208 * 0x20be00--0x20c000
12209 * 0x263c00--0x264000
12210 * 0x265c00--0x266000
12212 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
12214 if ((type != I40E_MAC_X722) &&
12215 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
12216 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
12217 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
12218 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
12219 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
12220 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
12221 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
12227 static int i40e_get_regs(struct rte_eth_dev *dev,
12228 struct rte_dev_reg_info *regs)
12230 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12231 uint32_t *ptr_data = regs->data;
12232 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
12233 const struct i40e_reg_info *reg_info;
12235 if (ptr_data == NULL) {
12236 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
12237 regs->width = sizeof(uint32_t);
12241 /* The first few registers have to be read using AQ operations */
12243 while (i40e_regs_adminq[reg_idx].name) {
12244 reg_info = &i40e_regs_adminq[reg_idx++];
12245 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12247 arr_idx2 <= reg_info->count2;
12249 reg_offset = arr_idx * reg_info->stride1 +
12250 arr_idx2 * reg_info->stride2;
12251 reg_offset += reg_info->base_addr;
12252 ptr_data[reg_offset >> 2] =
12253 i40e_read_rx_ctl(hw, reg_offset);
12257 /* The remaining registers can be read using primitives */
12259 while (i40e_regs_others[reg_idx].name) {
12260 reg_info = &i40e_regs_others[reg_idx++];
12261 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12263 arr_idx2 <= reg_info->count2;
12265 reg_offset = arr_idx * reg_info->stride1 +
12266 arr_idx2 * reg_info->stride2;
12267 reg_offset += reg_info->base_addr;
12268 if (!i40e_valid_regs(hw->mac.type, reg_offset))
12269 ptr_data[reg_offset >> 2] = 0;
12271 ptr_data[reg_offset >> 2] =
12272 I40E_READ_REG(hw, reg_offset);
12279 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
12281 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12283 /* Convert word count to byte count */
12284 return hw->nvm.sr_size << 1;
12287 static int i40e_get_eeprom(struct rte_eth_dev *dev,
12288 struct rte_dev_eeprom_info *eeprom)
12290 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12291 uint16_t *data = eeprom->data;
12292 uint16_t offset, length, cnt_words;
12295 offset = eeprom->offset >> 1;
12296 length = eeprom->length >> 1;
12297 cnt_words = length;
12299 if (offset > hw->nvm.sr_size ||
12300 offset + length > hw->nvm.sr_size) {
12301 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
12305 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
12307 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
12308 if (ret_code != I40E_SUCCESS || cnt_words != length) {
12309 PMD_DRV_LOG(ERR, "EEPROM read failed.");
12316 static int i40e_get_module_info(struct rte_eth_dev *dev,
12317 struct rte_eth_dev_module_info *modinfo)
12319 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12320 uint32_t sff8472_comp = 0;
12321 uint32_t sff8472_swap = 0;
12322 uint32_t sff8636_rev = 0;
12323 i40e_status status;
12326 /* Check if firmware supports reading module EEPROM. */
12327 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
12329 "Module EEPROM memory read not supported. "
12330 "Please update the NVM image.\n");
12334 status = i40e_update_link_info(hw);
12338 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
12340 "Cannot read module EEPROM memory. "
12341 "No module connected.\n");
12345 type = hw->phy.link_info.module_type[0];
12348 case I40E_MODULE_TYPE_SFP:
12349 status = i40e_aq_get_phy_register(hw,
12350 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12351 I40E_I2C_EEPROM_DEV_ADDR, 1,
12352 I40E_MODULE_SFF_8472_COMP,
12353 &sff8472_comp, NULL);
12357 status = i40e_aq_get_phy_register(hw,
12358 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12359 I40E_I2C_EEPROM_DEV_ADDR, 1,
12360 I40E_MODULE_SFF_8472_SWAP,
12361 &sff8472_swap, NULL);
12365 /* Check if the module requires address swap to access
12366 * the other EEPROM memory page.
12368 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
12369 PMD_DRV_LOG(WARNING,
12370 "Module address swap to access "
12371 "page 0xA2 is not supported.\n");
12372 modinfo->type = RTE_ETH_MODULE_SFF_8079;
12373 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12374 } else if (sff8472_comp == 0x00) {
12375 /* Module is not SFF-8472 compliant */
12376 modinfo->type = RTE_ETH_MODULE_SFF_8079;
12377 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12379 modinfo->type = RTE_ETH_MODULE_SFF_8472;
12380 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
12383 case I40E_MODULE_TYPE_QSFP_PLUS:
12384 /* Read from memory page 0. */
12385 status = i40e_aq_get_phy_register(hw,
12386 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12388 I40E_MODULE_REVISION_ADDR,
12389 &sff8636_rev, NULL);
12392 /* Determine revision compliance byte */
12393 if (sff8636_rev > 0x02) {
12394 /* Module is SFF-8636 compliant */
12395 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12396 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12398 modinfo->type = RTE_ETH_MODULE_SFF_8436;
12399 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12402 case I40E_MODULE_TYPE_QSFP28:
12403 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12404 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12407 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
12413 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
12414 struct rte_dev_eeprom_info *info)
12416 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12417 bool is_sfp = false;
12418 i40e_status status;
12420 uint32_t value = 0;
12423 if (!info || !info->length || !info->data)
12426 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12430 for (i = 0; i < info->length; i++) {
12431 u32 offset = i + info->offset;
12432 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12434 /* Check if we need to access the other memory page */
12436 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12437 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12438 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12441 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12442 /* Compute memory page number and offset. */
12443 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12447 status = i40e_aq_get_phy_register(hw,
12448 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12449 addr, 1, offset, &value, NULL);
12452 data[i] = (uint8_t)value;
12457 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12458 struct rte_ether_addr *mac_addr)
12460 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12461 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12462 struct i40e_vsi *vsi = pf->main_vsi;
12463 struct i40e_mac_filter_info mac_filter;
12464 struct i40e_mac_filter *f;
12467 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12468 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12472 TAILQ_FOREACH(f, &vsi->mac_list, next) {
12473 if (rte_is_same_ether_addr(&pf->dev_addr,
12474 &f->mac_info.mac_addr))
12479 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12483 mac_filter = f->mac_info;
12484 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12485 if (ret != I40E_SUCCESS) {
12486 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12489 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12490 ret = i40e_vsi_add_mac(vsi, &mac_filter);
12491 if (ret != I40E_SUCCESS) {
12492 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12495 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12497 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12498 mac_addr->addr_bytes, NULL);
12499 if (ret != I40E_SUCCESS) {
12500 PMD_DRV_LOG(ERR, "Failed to change mac");
12508 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12510 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12511 struct rte_eth_dev_data *dev_data = pf->dev_data;
12512 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12515 /* check if mtu is within the allowed range */
12516 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12519 /* mtu setting is forbidden if port is start */
12520 if (dev_data->dev_started) {
12521 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12522 dev_data->port_id);
12526 if (frame_size > RTE_ETHER_MAX_LEN)
12527 dev_data->dev_conf.rxmode.offloads |=
12528 DEV_RX_OFFLOAD_JUMBO_FRAME;
12530 dev_data->dev_conf.rxmode.offloads &=
12531 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12533 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12538 /* Restore ethertype filter */
12540 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12542 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12543 struct i40e_ethertype_filter_list
12544 *ethertype_list = &pf->ethertype.ethertype_list;
12545 struct i40e_ethertype_filter *f;
12546 struct i40e_control_filter_stats stats;
12549 TAILQ_FOREACH(f, ethertype_list, rules) {
12551 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12552 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12553 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12554 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12555 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12557 memset(&stats, 0, sizeof(stats));
12558 i40e_aq_add_rem_control_packet_filter(hw,
12559 f->input.mac_addr.addr_bytes,
12560 f->input.ether_type,
12561 flags, pf->main_vsi->seid,
12562 f->queue, 1, &stats, NULL);
12564 PMD_DRV_LOG(INFO, "Ethertype filter:"
12565 " mac_etype_used = %u, etype_used = %u,"
12566 " mac_etype_free = %u, etype_free = %u",
12567 stats.mac_etype_used, stats.etype_used,
12568 stats.mac_etype_free, stats.etype_free);
12571 /* Restore tunnel filter */
12573 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12575 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12576 struct i40e_vsi *vsi;
12577 struct i40e_pf_vf *vf;
12578 struct i40e_tunnel_filter_list
12579 *tunnel_list = &pf->tunnel.tunnel_list;
12580 struct i40e_tunnel_filter *f;
12581 struct i40e_aqc_cloud_filters_element_bb cld_filter;
12582 bool big_buffer = 0;
12584 TAILQ_FOREACH(f, tunnel_list, rules) {
12586 vsi = pf->main_vsi;
12588 vf = &pf->vfs[f->vf_id];
12591 memset(&cld_filter, 0, sizeof(cld_filter));
12592 rte_ether_addr_copy((struct rte_ether_addr *)
12593 &f->input.outer_mac,
12594 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12595 rte_ether_addr_copy((struct rte_ether_addr *)
12596 &f->input.inner_mac,
12597 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12598 cld_filter.element.inner_vlan = f->input.inner_vlan;
12599 cld_filter.element.flags = f->input.flags;
12600 cld_filter.element.tenant_id = f->input.tenant_id;
12601 cld_filter.element.queue_number = f->queue;
12602 rte_memcpy(cld_filter.general_fields,
12603 f->input.general_fields,
12604 sizeof(f->input.general_fields));
12606 if (((f->input.flags &
12607 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12608 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12610 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12611 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12613 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12614 I40E_AQC_ADD_CLOUD_FILTER_0X10))
12618 i40e_aq_add_cloud_filters_bb(hw,
12619 vsi->seid, &cld_filter, 1);
12621 i40e_aq_add_cloud_filters(hw, vsi->seid,
12622 &cld_filter.element, 1);
12626 /* Restore RSS filter */
12628 i40e_rss_filter_restore(struct i40e_pf *pf)
12630 struct i40e_rss_conf_list *list = &pf->rss_config_list;
12631 struct i40e_rss_filter *filter;
12633 TAILQ_FOREACH(filter, list, next) {
12634 i40e_config_rss_filter(pf, &filter->rss_filter_info, TRUE);
12639 i40e_filter_restore(struct i40e_pf *pf)
12641 i40e_ethertype_filter_restore(pf);
12642 i40e_tunnel_filter_restore(pf);
12643 i40e_fdir_filter_restore(pf);
12644 i40e_rss_filter_restore(pf);
12648 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12650 if (strcmp(dev->device->driver->name, drv->driver.name))
12657 is_i40e_supported(struct rte_eth_dev *dev)
12659 return is_device_supported(dev, &rte_i40e_pmd);
12662 struct i40e_customized_pctype*
12663 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12667 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12668 if (pf->customized_pctype[i].index == index)
12669 return &pf->customized_pctype[i];
12675 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12676 uint32_t pkg_size, uint32_t proto_num,
12677 struct rte_pmd_i40e_proto_info *proto,
12678 enum rte_pmd_i40e_package_op op)
12680 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12681 uint32_t pctype_num;
12682 struct rte_pmd_i40e_ptype_info *pctype;
12683 uint32_t buff_size;
12684 struct i40e_customized_pctype *new_pctype = NULL;
12686 uint8_t pctype_value;
12691 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12692 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12693 PMD_DRV_LOG(ERR, "Unsupported operation.");
12697 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12698 (uint8_t *)&pctype_num, sizeof(pctype_num),
12699 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12701 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12705 PMD_DRV_LOG(INFO, "No new pctype added");
12709 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12710 pctype = rte_zmalloc("new_pctype", buff_size, 0);
12712 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12715 /* get information about new pctype list */
12716 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12717 (uint8_t *)pctype, buff_size,
12718 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12720 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12725 /* Update customized pctype. */
12726 for (i = 0; i < pctype_num; i++) {
12727 pctype_value = pctype[i].ptype_id;
12728 memset(name, 0, sizeof(name));
12729 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12730 proto_id = pctype[i].protocols[j];
12731 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12733 for (n = 0; n < proto_num; n++) {
12734 if (proto[n].proto_id != proto_id)
12736 strlcat(name, proto[n].name, sizeof(name));
12737 strlcat(name, "_", sizeof(name));
12741 name[strlen(name) - 1] = '\0';
12742 PMD_DRV_LOG(INFO, "name = %s\n", name);
12743 if (!strcmp(name, "GTPC"))
12745 i40e_find_customized_pctype(pf,
12746 I40E_CUSTOMIZED_GTPC);
12747 else if (!strcmp(name, "GTPU_IPV4"))
12749 i40e_find_customized_pctype(pf,
12750 I40E_CUSTOMIZED_GTPU_IPV4);
12751 else if (!strcmp(name, "GTPU_IPV6"))
12753 i40e_find_customized_pctype(pf,
12754 I40E_CUSTOMIZED_GTPU_IPV6);
12755 else if (!strcmp(name, "GTPU"))
12757 i40e_find_customized_pctype(pf,
12758 I40E_CUSTOMIZED_GTPU);
12759 else if (!strcmp(name, "IPV4_L2TPV3"))
12761 i40e_find_customized_pctype(pf,
12762 I40E_CUSTOMIZED_IPV4_L2TPV3);
12763 else if (!strcmp(name, "IPV6_L2TPV3"))
12765 i40e_find_customized_pctype(pf,
12766 I40E_CUSTOMIZED_IPV6_L2TPV3);
12767 else if (!strcmp(name, "IPV4_ESP"))
12769 i40e_find_customized_pctype(pf,
12770 I40E_CUSTOMIZED_ESP_IPV4);
12771 else if (!strcmp(name, "IPV6_ESP"))
12773 i40e_find_customized_pctype(pf,
12774 I40E_CUSTOMIZED_ESP_IPV6);
12775 else if (!strcmp(name, "IPV4_UDP_ESP"))
12777 i40e_find_customized_pctype(pf,
12778 I40E_CUSTOMIZED_ESP_IPV4_UDP);
12779 else if (!strcmp(name, "IPV6_UDP_ESP"))
12781 i40e_find_customized_pctype(pf,
12782 I40E_CUSTOMIZED_ESP_IPV6_UDP);
12783 else if (!strcmp(name, "IPV4_AH"))
12785 i40e_find_customized_pctype(pf,
12786 I40E_CUSTOMIZED_AH_IPV4);
12787 else if (!strcmp(name, "IPV6_AH"))
12789 i40e_find_customized_pctype(pf,
12790 I40E_CUSTOMIZED_AH_IPV6);
12792 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12793 new_pctype->pctype = pctype_value;
12794 new_pctype->valid = true;
12796 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12797 new_pctype->valid = false;
12807 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12808 uint32_t pkg_size, uint32_t proto_num,
12809 struct rte_pmd_i40e_proto_info *proto,
12810 enum rte_pmd_i40e_package_op op)
12812 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12813 uint16_t port_id = dev->data->port_id;
12814 uint32_t ptype_num;
12815 struct rte_pmd_i40e_ptype_info *ptype;
12816 uint32_t buff_size;
12818 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12823 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12824 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12825 PMD_DRV_LOG(ERR, "Unsupported operation.");
12829 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12830 rte_pmd_i40e_ptype_mapping_reset(port_id);
12834 /* get information about new ptype num */
12835 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12836 (uint8_t *)&ptype_num, sizeof(ptype_num),
12837 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12839 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12843 PMD_DRV_LOG(INFO, "No new ptype added");
12847 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12848 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12850 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12854 /* get information about new ptype list */
12855 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12856 (uint8_t *)ptype, buff_size,
12857 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12859 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12864 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12865 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12866 if (!ptype_mapping) {
12867 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12872 /* Update ptype mapping table. */
12873 for (i = 0; i < ptype_num; i++) {
12874 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12875 ptype_mapping[i].sw_ptype = 0;
12877 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12878 proto_id = ptype[i].protocols[j];
12879 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12881 for (n = 0; n < proto_num; n++) {
12882 if (proto[n].proto_id != proto_id)
12884 memset(name, 0, sizeof(name));
12885 strcpy(name, proto[n].name);
12886 PMD_DRV_LOG(INFO, "name = %s\n", name);
12887 if (!strncasecmp(name, "PPPOE", 5))
12888 ptype_mapping[i].sw_ptype |=
12889 RTE_PTYPE_L2_ETHER_PPPOE;
12890 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12892 ptype_mapping[i].sw_ptype |=
12893 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12894 ptype_mapping[i].sw_ptype |=
12896 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12898 ptype_mapping[i].sw_ptype |=
12899 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12900 ptype_mapping[i].sw_ptype |=
12901 RTE_PTYPE_INNER_L4_FRAG;
12902 } else if (!strncasecmp(name, "OIPV4", 5)) {
12903 ptype_mapping[i].sw_ptype |=
12904 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12906 } else if (!strncasecmp(name, "IPV4", 4) &&
12908 ptype_mapping[i].sw_ptype |=
12909 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12910 else if (!strncasecmp(name, "IPV4", 4) &&
12912 ptype_mapping[i].sw_ptype |=
12913 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12914 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12916 ptype_mapping[i].sw_ptype |=
12917 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12918 ptype_mapping[i].sw_ptype |=
12920 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12922 ptype_mapping[i].sw_ptype |=
12923 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12924 ptype_mapping[i].sw_ptype |=
12925 RTE_PTYPE_INNER_L4_FRAG;
12926 } else if (!strncasecmp(name, "OIPV6", 5)) {
12927 ptype_mapping[i].sw_ptype |=
12928 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12930 } else if (!strncasecmp(name, "IPV6", 4) &&
12932 ptype_mapping[i].sw_ptype |=
12933 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12934 else if (!strncasecmp(name, "IPV6", 4) &&
12936 ptype_mapping[i].sw_ptype |=
12937 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12938 else if (!strncasecmp(name, "UDP", 3) &&
12940 ptype_mapping[i].sw_ptype |=
12942 else if (!strncasecmp(name, "UDP", 3) &&
12944 ptype_mapping[i].sw_ptype |=
12945 RTE_PTYPE_INNER_L4_UDP;
12946 else if (!strncasecmp(name, "TCP", 3) &&
12948 ptype_mapping[i].sw_ptype |=
12950 else if (!strncasecmp(name, "TCP", 3) &&
12952 ptype_mapping[i].sw_ptype |=
12953 RTE_PTYPE_INNER_L4_TCP;
12954 else if (!strncasecmp(name, "SCTP", 4) &&
12956 ptype_mapping[i].sw_ptype |=
12958 else if (!strncasecmp(name, "SCTP", 4) &&
12960 ptype_mapping[i].sw_ptype |=
12961 RTE_PTYPE_INNER_L4_SCTP;
12962 else if ((!strncasecmp(name, "ICMP", 4) ||
12963 !strncasecmp(name, "ICMPV6", 6)) &&
12965 ptype_mapping[i].sw_ptype |=
12967 else if ((!strncasecmp(name, "ICMP", 4) ||
12968 !strncasecmp(name, "ICMPV6", 6)) &&
12970 ptype_mapping[i].sw_ptype |=
12971 RTE_PTYPE_INNER_L4_ICMP;
12972 else if (!strncasecmp(name, "GTPC", 4)) {
12973 ptype_mapping[i].sw_ptype |=
12974 RTE_PTYPE_TUNNEL_GTPC;
12976 } else if (!strncasecmp(name, "GTPU", 4)) {
12977 ptype_mapping[i].sw_ptype |=
12978 RTE_PTYPE_TUNNEL_GTPU;
12980 } else if (!strncasecmp(name, "ESP", 3)) {
12981 ptype_mapping[i].sw_ptype |=
12982 RTE_PTYPE_TUNNEL_ESP;
12984 } else if (!strncasecmp(name, "GRENAT", 6)) {
12985 ptype_mapping[i].sw_ptype |=
12986 RTE_PTYPE_TUNNEL_GRENAT;
12988 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12989 !strncasecmp(name, "L2TPV2", 6) ||
12990 !strncasecmp(name, "L2TPV3", 6)) {
12991 ptype_mapping[i].sw_ptype |=
12992 RTE_PTYPE_TUNNEL_L2TP;
13001 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
13004 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
13006 rte_free(ptype_mapping);
13012 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
13013 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
13015 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
13016 uint32_t proto_num;
13017 struct rte_pmd_i40e_proto_info *proto;
13018 uint32_t buff_size;
13022 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
13023 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
13024 PMD_DRV_LOG(ERR, "Unsupported operation.");
13028 /* get information about protocol number */
13029 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
13030 (uint8_t *)&proto_num, sizeof(proto_num),
13031 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
13033 PMD_DRV_LOG(ERR, "Failed to get protocol number");
13037 PMD_DRV_LOG(INFO, "No new protocol added");
13041 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
13042 proto = rte_zmalloc("new_proto", buff_size, 0);
13044 PMD_DRV_LOG(ERR, "Failed to allocate memory");
13048 /* get information about protocol list */
13049 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
13050 (uint8_t *)proto, buff_size,
13051 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
13053 PMD_DRV_LOG(ERR, "Failed to get protocol list");
13058 /* Check if GTP is supported. */
13059 for (i = 0; i < proto_num; i++) {
13060 if (!strncmp(proto[i].name, "GTP", 3)) {
13061 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
13062 pf->gtp_support = true;
13064 pf->gtp_support = false;
13069 /* Check if ESP is supported. */
13070 for (i = 0; i < proto_num; i++) {
13071 if (!strncmp(proto[i].name, "ESP", 3)) {
13072 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
13073 pf->esp_support = true;
13075 pf->esp_support = false;
13080 /* Update customized pctype info */
13081 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
13082 proto_num, proto, op);
13084 PMD_DRV_LOG(INFO, "No pctype is updated.");
13086 /* Update customized ptype info */
13087 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
13088 proto_num, proto, op);
13090 PMD_DRV_LOG(INFO, "No ptype is updated.");
13095 /* Create a QinQ cloud filter
13097 * The Fortville NIC has limited resources for tunnel filters,
13098 * so we can only reuse existing filters.
13100 * In step 1 we define which Field Vector fields can be used for
13102 * As we do not have the inner tag defined as a field,
13103 * we have to define it first, by reusing one of L1 entries.
13105 * In step 2 we are replacing one of existing filter types with
13106 * a new one for QinQ.
13107 * As we reusing L1 and replacing L2, some of the default filter
13108 * types will disappear,which depends on L1 and L2 entries we reuse.
13110 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
13112 * 1. Create L1 filter of outer vlan (12b) which will be in use
13113 * later when we define the cloud filter.
13114 * a. Valid_flags.replace_cloud = 0
13115 * b. Old_filter = 10 (Stag_Inner_Vlan)
13116 * c. New_filter = 0x10
13117 * d. TR bit = 0xff (optional, not used here)
13118 * e. Buffer – 2 entries:
13119 * i. Byte 0 = 8 (outer vlan FV index).
13121 * Byte 2-3 = 0x0fff
13122 * ii. Byte 0 = 37 (inner vlan FV index).
13124 * Byte 2-3 = 0x0fff
13127 * 2. Create cloud filter using two L1 filters entries: stag and
13128 * new filter(outer vlan+ inner vlan)
13129 * a. Valid_flags.replace_cloud = 1
13130 * b. Old_filter = 1 (instead of outer IP)
13131 * c. New_filter = 0x10
13132 * d. Buffer – 2 entries:
13133 * i. Byte 0 = 0x80 | 7 (valid | Stag).
13134 * Byte 1-3 = 0 (rsv)
13135 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
13136 * Byte 9-11 = 0 (rsv)
13139 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
13141 int ret = -ENOTSUP;
13142 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
13143 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
13144 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13145 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
13147 if (pf->support_multi_driver) {
13148 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
13153 memset(&filter_replace, 0,
13154 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13155 memset(&filter_replace_buf, 0,
13156 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13158 /* create L1 filter */
13159 filter_replace.old_filter_type =
13160 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
13161 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13162 filter_replace.tr_bit = 0;
13164 /* Prepare the buffer, 2 entries */
13165 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
13166 filter_replace_buf.data[0] |=
13167 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13168 /* Field Vector 12b mask */
13169 filter_replace_buf.data[2] = 0xff;
13170 filter_replace_buf.data[3] = 0x0f;
13171 filter_replace_buf.data[4] =
13172 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
13173 filter_replace_buf.data[4] |=
13174 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13175 /* Field Vector 12b mask */
13176 filter_replace_buf.data[6] = 0xff;
13177 filter_replace_buf.data[7] = 0x0f;
13178 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13179 &filter_replace_buf);
13180 if (ret != I40E_SUCCESS)
13183 if (filter_replace.old_filter_type !=
13184 filter_replace.new_filter_type)
13185 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
13186 " original: 0x%x, new: 0x%x",
13188 filter_replace.old_filter_type,
13189 filter_replace.new_filter_type);
13191 /* Apply the second L2 cloud filter */
13192 memset(&filter_replace, 0,
13193 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13194 memset(&filter_replace_buf, 0,
13195 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13197 /* create L2 filter, input for L2 filter will be L1 filter */
13198 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
13199 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
13200 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13202 /* Prepare the buffer, 2 entries */
13203 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
13204 filter_replace_buf.data[0] |=
13205 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13206 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13207 filter_replace_buf.data[4] |=
13208 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13209 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13210 &filter_replace_buf);
13211 if (!ret && (filter_replace.old_filter_type !=
13212 filter_replace.new_filter_type))
13213 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
13214 " original: 0x%x, new: 0x%x",
13216 filter_replace.old_filter_type,
13217 filter_replace.new_filter_type);
13223 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
13224 const struct rte_flow_action_rss *in)
13226 if (in->key_len > RTE_DIM(out->key) ||
13227 in->queue_num > RTE_DIM(out->queue))
13229 if (!in->key && in->key_len)
13231 out->conf = (struct rte_flow_action_rss){
13233 .level = in->level,
13234 .types = in->types,
13235 .key_len = in->key_len,
13236 .queue_num = in->queue_num,
13237 .queue = memcpy(out->queue, in->queue,
13238 sizeof(*in->queue) * in->queue_num),
13241 out->conf.key = memcpy(out->key, in->key, in->key_len);
13245 /* Write HENA register to enable hash */
13247 i40e_rss_hash_set(struct i40e_pf *pf, struct i40e_rte_flow_rss_conf *rss_conf)
13249 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13250 uint8_t *key = (void *)(uintptr_t)rss_conf->conf.key;
13254 ret = i40e_set_rss_key(pf->main_vsi, key,
13255 rss_conf->conf.key_len);
13259 hena = i40e_config_hena(pf->adapter, rss_conf->conf.types);
13260 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
13261 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
13262 I40E_WRITE_FLUSH(hw);
13267 /* Configure hash input set */
13269 i40e_rss_conf_hash_inset(struct i40e_pf *pf, uint64_t types)
13271 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13272 struct rte_eth_input_set_conf conf;
13277 static const struct {
13279 enum rte_eth_input_set_field field;
13280 } inset_match_table[] = {
13281 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_SRC_ONLY,
13282 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13283 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_DST_ONLY,
13284 RTE_ETH_INPUT_SET_L3_DST_IP4},
13285 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_SRC_ONLY,
13286 RTE_ETH_INPUT_SET_UNKNOWN},
13287 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_DST_ONLY,
13288 RTE_ETH_INPUT_SET_UNKNOWN},
13290 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_SRC_ONLY,
13291 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13292 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_DST_ONLY,
13293 RTE_ETH_INPUT_SET_L3_DST_IP4},
13294 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_SRC_ONLY,
13295 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13296 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_DST_ONLY,
13297 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13299 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_SRC_ONLY,
13300 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13301 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_DST_ONLY,
13302 RTE_ETH_INPUT_SET_L3_DST_IP4},
13303 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_SRC_ONLY,
13304 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13305 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_DST_ONLY,
13306 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13308 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_SRC_ONLY,
13309 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13310 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_DST_ONLY,
13311 RTE_ETH_INPUT_SET_L3_DST_IP4},
13312 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_SRC_ONLY,
13313 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13314 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_DST_ONLY,
13315 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13317 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_SRC_ONLY,
13318 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13319 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_DST_ONLY,
13320 RTE_ETH_INPUT_SET_L3_DST_IP4},
13321 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_SRC_ONLY,
13322 RTE_ETH_INPUT_SET_UNKNOWN},
13323 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_DST_ONLY,
13324 RTE_ETH_INPUT_SET_UNKNOWN},
13326 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_SRC_ONLY,
13327 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13328 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_DST_ONLY,
13329 RTE_ETH_INPUT_SET_L3_DST_IP6},
13330 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_SRC_ONLY,
13331 RTE_ETH_INPUT_SET_UNKNOWN},
13332 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_DST_ONLY,
13333 RTE_ETH_INPUT_SET_UNKNOWN},
13335 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_SRC_ONLY,
13336 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13337 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_DST_ONLY,
13338 RTE_ETH_INPUT_SET_L3_DST_IP6},
13339 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_SRC_ONLY,
13340 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13341 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_DST_ONLY,
13342 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13344 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_SRC_ONLY,
13345 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13346 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_DST_ONLY,
13347 RTE_ETH_INPUT_SET_L3_DST_IP6},
13348 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_SRC_ONLY,
13349 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13350 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_DST_ONLY,
13351 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13353 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_SRC_ONLY,
13354 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13355 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_DST_ONLY,
13356 RTE_ETH_INPUT_SET_L3_DST_IP6},
13357 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_SRC_ONLY,
13358 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13359 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_DST_ONLY,
13360 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13362 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_SRC_ONLY,
13363 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13364 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_DST_ONLY,
13365 RTE_ETH_INPUT_SET_L3_DST_IP6},
13366 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_SRC_ONLY,
13367 RTE_ETH_INPUT_SET_UNKNOWN},
13368 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_DST_ONLY,
13369 RTE_ETH_INPUT_SET_UNKNOWN},
13372 mask0 = types & pf->adapter->flow_types_mask;
13373 conf.op = RTE_ETH_INPUT_SET_SELECT;
13374 conf.inset_size = 0;
13375 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < RTE_ETH_FLOW_MAX; i++) {
13376 if (mask0 & (1ULL << i)) {
13377 conf.flow_type = i;
13382 for (j = 0; j < RTE_DIM(inset_match_table); j++) {
13383 if ((types & inset_match_table[j].type) ==
13384 inset_match_table[j].type) {
13385 if (inset_match_table[j].field ==
13386 RTE_ETH_INPUT_SET_UNKNOWN)
13389 conf.field[conf.inset_size] =
13390 inset_match_table[j].field;
13395 if (conf.inset_size) {
13396 ret = i40e_hash_filter_inset_select(hw, &conf);
13404 /* Look up the conflicted rule then mark it as invalid */
13406 i40e_rss_mark_invalid_rule(struct i40e_pf *pf,
13407 struct i40e_rte_flow_rss_conf *conf)
13409 struct i40e_rss_filter *rss_item;
13410 uint64_t rss_inset;
13412 /* Clear input set bits before comparing the pctype */
13413 rss_inset = ~(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY |
13414 ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY);
13416 /* Look up the conflicted rule then mark it as invalid */
13417 TAILQ_FOREACH(rss_item, &pf->rss_config_list, next) {
13418 if (!rss_item->rss_filter_info.valid)
13421 if (conf->conf.queue_num &&
13422 rss_item->rss_filter_info.conf.queue_num)
13423 rss_item->rss_filter_info.valid = false;
13425 if (conf->conf.types &&
13426 (rss_item->rss_filter_info.conf.types &
13428 (conf->conf.types & rss_inset))
13429 rss_item->rss_filter_info.valid = false;
13431 if (conf->conf.func ==
13432 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
13433 rss_item->rss_filter_info.conf.func ==
13434 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13435 rss_item->rss_filter_info.valid = false;
13439 /* Configure RSS hash function */
13441 i40e_rss_config_hash_function(struct i40e_pf *pf,
13442 struct i40e_rte_flow_rss_conf *conf)
13444 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13449 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13450 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13451 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
13452 PMD_DRV_LOG(DEBUG, "Hash function already set to Simple XOR");
13453 I40E_WRITE_FLUSH(hw);
13454 i40e_rss_mark_invalid_rule(pf, conf);
13458 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
13460 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13461 I40E_WRITE_FLUSH(hw);
13462 i40e_rss_mark_invalid_rule(pf, conf);
13463 } else if (conf->conf.func ==
13464 RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13465 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13467 i40e_set_symmetric_hash_enable_per_port(hw, 1);
13468 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13469 if (mask0 & (1UL << i))
13473 if (i == UINT64_BIT)
13476 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13477 j < I40E_FILTER_PCTYPE_MAX; j++) {
13478 if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13479 i40e_write_global_rx_ctl(hw,
13481 I40E_GLQF_HSYM_SYMH_ENA_MASK);
13488 /* Enable RSS according to the configuration */
13490 i40e_rss_enable_hash(struct i40e_pf *pf,
13491 struct i40e_rte_flow_rss_conf *conf)
13493 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13494 struct i40e_rte_flow_rss_conf rss_conf;
13496 if (!(conf->conf.types & pf->adapter->flow_types_mask))
13499 memset(&rss_conf, 0, sizeof(rss_conf));
13500 rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13502 /* Configure hash input set */
13503 if (i40e_rss_conf_hash_inset(pf, conf->conf.types))
13506 if (rss_conf.conf.key == NULL || rss_conf.conf.key_len <
13507 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
13508 /* Random default keys */
13509 static uint32_t rss_key_default[] = {0x6b793944,
13510 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
13511 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
13512 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
13514 rss_conf.conf.key = (uint8_t *)rss_key_default;
13515 rss_conf.conf.key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
13518 "No valid RSS key config for i40e, using default\n");
13521 rss_conf.conf.types |= rss_info->conf.types;
13522 i40e_rss_hash_set(pf, &rss_conf);
13524 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ)
13525 i40e_rss_config_hash_function(pf, conf);
13527 i40e_rss_mark_invalid_rule(pf, conf);
13532 /* Configure RSS queue region */
13534 i40e_rss_config_queue_region(struct i40e_pf *pf,
13535 struct i40e_rte_flow_rss_conf *conf)
13537 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13542 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13543 * It's necessary to calculate the actual PF queues that are configured.
13545 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13546 num = i40e_pf_calc_configured_queues_num(pf);
13548 num = pf->dev_data->nb_rx_queues;
13550 num = RTE_MIN(num, conf->conf.queue_num);
13551 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13556 "No PF queues are configured to enable RSS for port %u",
13557 pf->dev_data->port_id);
13561 /* Fill in redirection table */
13562 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13565 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
13566 hw->func_caps.rss_table_entry_width) - 1));
13568 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13571 i40e_rss_mark_invalid_rule(pf, conf);
13576 /* Configure RSS hash function to default */
13578 i40e_rss_clear_hash_function(struct i40e_pf *pf,
13579 struct i40e_rte_flow_rss_conf *conf)
13581 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13586 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13587 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13588 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
13590 "Hash function already set to Toeplitz");
13591 I40E_WRITE_FLUSH(hw);
13595 reg |= I40E_GLQF_CTL_HTOEP_MASK;
13597 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13598 I40E_WRITE_FLUSH(hw);
13599 } else if (conf->conf.func ==
13600 RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13601 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13603 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13604 if (mask0 & (1UL << i))
13608 if (i == UINT64_BIT)
13611 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13612 j < I40E_FILTER_PCTYPE_MAX; j++) {
13613 if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13614 i40e_write_global_rx_ctl(hw,
13623 /* Disable RSS hash and configure default input set */
13625 i40e_rss_disable_hash(struct i40e_pf *pf,
13626 struct i40e_rte_flow_rss_conf *conf)
13628 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13629 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13630 struct i40e_rte_flow_rss_conf rss_conf;
13633 memset(&rss_conf, 0, sizeof(rss_conf));
13634 rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13636 /* Disable RSS hash */
13637 rss_conf.conf.types = rss_info->conf.types & ~(conf->conf.types);
13638 i40e_rss_hash_set(pf, &rss_conf);
13640 for (i = RTE_ETH_FLOW_IPV4; i <= RTE_ETH_FLOW_L2_PAYLOAD; i++) {
13641 if (!(pf->adapter->flow_types_mask & (1ULL << i)) ||
13642 !(conf->conf.types & (1ULL << i)))
13645 /* Configure default input set */
13646 struct rte_eth_input_set_conf input_conf = {
13647 .op = RTE_ETH_INPUT_SET_SELECT,
13651 input_conf.field[0] = RTE_ETH_INPUT_SET_DEFAULT;
13652 i40e_hash_filter_inset_select(hw, &input_conf);
13655 rss_info->conf.types = rss_conf.conf.types;
13657 i40e_rss_clear_hash_function(pf, conf);
13662 /* Configure RSS queue region to default */
13664 i40e_rss_clear_queue_region(struct i40e_pf *pf)
13666 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13667 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13668 uint16_t queue[I40E_MAX_Q_PER_TC];
13669 uint32_t num_rxq, i;
13673 num_rxq = RTE_MIN(pf->dev_data->nb_rx_queues, I40E_MAX_Q_PER_TC);
13675 for (j = 0; j < num_rxq; j++)
13678 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13679 * It's necessary to calculate the actual PF queues that are configured.
13681 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13682 num = i40e_pf_calc_configured_queues_num(pf);
13684 num = pf->dev_data->nb_rx_queues;
13686 num = RTE_MIN(num, num_rxq);
13687 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13692 "No PF queues are configured to enable RSS for port %u",
13693 pf->dev_data->port_id);
13697 /* Fill in redirection table */
13698 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13701 lut = (lut << 8) | (queue[j] & ((0x1 <<
13702 hw->func_caps.rss_table_entry_width) - 1));
13704 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13707 rss_info->conf.queue_num = 0;
13708 memset(&rss_info->conf.queue, 0, sizeof(uint16_t));
13714 i40e_config_rss_filter(struct i40e_pf *pf,
13715 struct i40e_rte_flow_rss_conf *conf, bool add)
13717 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13718 struct rte_flow_action_rss update_conf = rss_info->conf;
13722 if (conf->conf.queue_num) {
13723 /* Configure RSS queue region */
13724 ret = i40e_rss_config_queue_region(pf, conf);
13728 update_conf.queue_num = conf->conf.queue_num;
13729 update_conf.queue = conf->conf.queue;
13730 } else if (conf->conf.func ==
13731 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13732 /* Configure hash function */
13733 ret = i40e_rss_config_hash_function(pf, conf);
13737 update_conf.func = conf->conf.func;
13739 /* Configure hash enable and input set */
13740 ret = i40e_rss_enable_hash(pf, conf);
13744 update_conf.types |= conf->conf.types;
13745 update_conf.key = conf->conf.key;
13746 update_conf.key_len = conf->conf.key_len;
13749 /* Update RSS info in pf */
13750 if (i40e_rss_conf_init(rss_info, &update_conf))
13756 if (conf->conf.queue_num)
13757 i40e_rss_clear_queue_region(pf);
13758 else if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13759 i40e_rss_clear_hash_function(pf, conf);
13761 i40e_rss_disable_hash(pf, conf);
13767 RTE_LOG_REGISTER(i40e_logtype_init, pmd.net.i40e.init, NOTICE);
13768 RTE_LOG_REGISTER(i40e_logtype_driver, pmd.net.i40e.driver, NOTICE);
13769 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
13770 RTE_LOG_REGISTER(i40e_logtype_rx, pmd.net.i40e.rx, DEBUG);
13772 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
13773 RTE_LOG_REGISTER(i40e_logtype_tx, pmd.net.i40e.tx, DEBUG);
13775 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
13776 RTE_LOG_REGISTER(i40e_logtype_tx_free, pmd.net.i40e.tx_free, DEBUG);
13779 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
13780 ETH_I40E_FLOATING_VEB_ARG "=1"
13781 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
13782 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
13783 ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
13784 ETH_I40E_USE_LATEST_VEC "=0|1");