1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Intel Corporation
13 #include <sys/queue.h>
15 #include <rte_string_fns.h>
16 #include <rte_memzone.h>
18 #include <rte_malloc.h>
19 #include <rte_ether.h>
20 #include <ethdev_driver.h>
29 #include "iavf_rxtx.h"
30 #include "rte_pmd_iavf.h"
32 /* Offset of mbuf dynamic field for protocol extraction's metadata */
33 int rte_pmd_ifd_dynfield_proto_xtr_metadata_offs = -1;
35 /* Mask of mbuf dynamic flags for protocol extraction's type */
36 uint64_t rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
37 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
38 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
39 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
40 uint64_t rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
41 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
44 iavf_proto_xtr_type_to_rxdid(uint8_t flex_type)
46 static uint8_t rxdid_map[] = {
47 [IAVF_PROTO_XTR_NONE] = IAVF_RXDID_COMMS_OVS_1,
48 [IAVF_PROTO_XTR_VLAN] = IAVF_RXDID_COMMS_AUX_VLAN,
49 [IAVF_PROTO_XTR_IPV4] = IAVF_RXDID_COMMS_AUX_IPV4,
50 [IAVF_PROTO_XTR_IPV6] = IAVF_RXDID_COMMS_AUX_IPV6,
51 [IAVF_PROTO_XTR_IPV6_FLOW] = IAVF_RXDID_COMMS_AUX_IPV6_FLOW,
52 [IAVF_PROTO_XTR_TCP] = IAVF_RXDID_COMMS_AUX_TCP,
53 [IAVF_PROTO_XTR_IP_OFFSET] = IAVF_RXDID_COMMS_AUX_IP_OFFSET,
56 return flex_type < RTE_DIM(rxdid_map) ?
57 rxdid_map[flex_type] : IAVF_RXDID_COMMS_OVS_1;
61 iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
63 struct iavf_rx_queue *rxq = rx_queue;
64 volatile union iavf_rx_desc *rxdp;
68 rxdp = &rxq->rx_ring[desc];
69 /* watch for changes in status bit */
70 pmc->addr = &rxdp->wb.qword1.status_error_len;
73 * we expect the DD bit to be set to 1 if this descriptor was already
76 pmc->val = rte_cpu_to_le_64(1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
77 pmc->mask = rte_cpu_to_le_64(1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
79 /* registers are 64-bit */
80 pmc->size = sizeof(uint64_t);
86 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
88 /* The following constraints must be satisfied:
89 * thresh < rxq->nb_rx_desc
91 if (thresh >= nb_desc) {
92 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
100 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
101 uint16_t tx_free_thresh)
103 /* TX descriptors will have their RS bit set after tx_rs_thresh
104 * descriptors have been used. The TX descriptor ring will be cleaned
105 * after tx_free_thresh descriptors are used or if the number of
106 * descriptors required to transmit a packet is greater than the
107 * number of free TX descriptors.
109 * The following constraints must be satisfied:
110 * - tx_rs_thresh must be less than the size of the ring minus 2.
111 * - tx_free_thresh must be less than the size of the ring minus 3.
112 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
113 * - tx_rs_thresh must be a divisor of the ring size.
115 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
116 * race condition, hence the maximum threshold constraints. When set
117 * to zero use default values.
119 if (tx_rs_thresh >= (nb_desc - 2)) {
120 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
121 "number of TX descriptors (%u) minus 2",
122 tx_rs_thresh, nb_desc);
125 if (tx_free_thresh >= (nb_desc - 3)) {
126 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
127 "number of TX descriptors (%u) minus 3.",
128 tx_free_thresh, nb_desc);
131 if (tx_rs_thresh > tx_free_thresh) {
132 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
133 "equal to tx_free_thresh (%u).",
134 tx_rs_thresh, tx_free_thresh);
137 if ((nb_desc % tx_rs_thresh) != 0) {
138 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
139 "number of TX descriptors (%u).",
140 tx_rs_thresh, nb_desc);
148 check_rx_vec_allow(struct iavf_rx_queue *rxq)
150 if (rxq->rx_free_thresh >= IAVF_VPMD_RX_MAX_BURST &&
151 rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
152 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
156 PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
161 check_tx_vec_allow(struct iavf_tx_queue *txq)
163 if (!(txq->offloads & IAVF_NO_VECTOR_FLAGS) &&
164 txq->rs_thresh >= IAVF_VPMD_TX_MAX_BURST &&
165 txq->rs_thresh <= IAVF_VPMD_TX_MAX_FREE_BUF) {
166 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
169 PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
174 check_rx_bulk_allow(struct iavf_rx_queue *rxq)
178 if (!(rxq->rx_free_thresh >= IAVF_RX_MAX_BURST)) {
179 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
180 "rxq->rx_free_thresh=%d, "
181 "IAVF_RX_MAX_BURST=%d",
182 rxq->rx_free_thresh, IAVF_RX_MAX_BURST);
184 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
185 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
186 "rxq->nb_rx_desc=%d, "
187 "rxq->rx_free_thresh=%d",
188 rxq->nb_rx_desc, rxq->rx_free_thresh);
195 reset_rx_queue(struct iavf_rx_queue *rxq)
203 len = rxq->nb_rx_desc + IAVF_RX_MAX_BURST;
205 for (i = 0; i < len * sizeof(union iavf_rx_desc); i++)
206 ((volatile char *)rxq->rx_ring)[i] = 0;
208 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
210 for (i = 0; i < IAVF_RX_MAX_BURST; i++)
211 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
214 rxq->rx_nb_avail = 0;
215 rxq->rx_next_avail = 0;
216 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
220 rxq->pkt_first_seg = NULL;
221 rxq->pkt_last_seg = NULL;
223 rxq->rxrearm_start = 0;
227 reset_tx_queue(struct iavf_tx_queue *txq)
229 struct iavf_tx_entry *txe;
234 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
239 size = sizeof(struct iavf_tx_desc) * txq->nb_tx_desc;
240 for (i = 0; i < size; i++)
241 ((volatile char *)txq->tx_ring)[i] = 0;
243 prev = (uint16_t)(txq->nb_tx_desc - 1);
244 for (i = 0; i < txq->nb_tx_desc; i++) {
245 txq->tx_ring[i].cmd_type_offset_bsz =
246 rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
249 txe[prev].next_id = i;
256 txq->last_desc_cleaned = txq->nb_tx_desc - 1;
257 txq->nb_free = txq->nb_tx_desc - 1;
259 txq->next_dd = txq->rs_thresh - 1;
260 txq->next_rs = txq->rs_thresh - 1;
264 alloc_rxq_mbufs(struct iavf_rx_queue *rxq)
266 volatile union iavf_rx_desc *rxd;
267 struct rte_mbuf *mbuf = NULL;
271 for (i = 0; i < rxq->nb_rx_desc; i++) {
272 mbuf = rte_mbuf_raw_alloc(rxq->mp);
273 if (unlikely(!mbuf)) {
274 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
278 rte_mbuf_refcnt_set(mbuf, 1);
280 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
282 mbuf->port = rxq->port_id;
285 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
287 rxd = &rxq->rx_ring[i];
288 rxd->read.pkt_addr = dma_addr;
289 rxd->read.hdr_addr = 0;
290 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
295 rxq->sw_ring[i] = mbuf;
302 release_rxq_mbufs(struct iavf_rx_queue *rxq)
309 for (i = 0; i < rxq->nb_rx_desc; i++) {
310 if (rxq->sw_ring[i]) {
311 rte_pktmbuf_free_seg(rxq->sw_ring[i]);
312 rxq->sw_ring[i] = NULL;
317 if (rxq->rx_nb_avail == 0)
319 for (i = 0; i < rxq->rx_nb_avail; i++) {
320 struct rte_mbuf *mbuf;
322 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
323 rte_pktmbuf_free_seg(mbuf);
325 rxq->rx_nb_avail = 0;
329 release_txq_mbufs(struct iavf_tx_queue *txq)
333 if (!txq || !txq->sw_ring) {
334 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
338 for (i = 0; i < txq->nb_tx_desc; i++) {
339 if (txq->sw_ring[i].mbuf) {
340 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
341 txq->sw_ring[i].mbuf = NULL;
346 static const struct iavf_rxq_ops def_rxq_ops = {
347 .release_mbufs = release_rxq_mbufs,
350 static const struct iavf_txq_ops def_txq_ops = {
351 .release_mbufs = release_txq_mbufs,
355 iavf_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct iavf_rx_queue *rxq,
357 volatile union iavf_rx_flex_desc *rxdp)
359 volatile struct iavf_32b_rx_flex_desc_comms_ovs *desc =
360 (volatile struct iavf_32b_rx_flex_desc_comms_ovs *)rxdp;
361 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
365 if (desc->flow_id != 0xFFFFFFFF) {
366 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
367 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
370 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
371 stat_err = rte_le_to_cpu_16(desc->status_error0);
372 if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
373 mb->ol_flags |= PKT_RX_RSS_HASH;
374 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
380 iavf_rxd_to_pkt_fields_by_comms_aux_v1(struct iavf_rx_queue *rxq,
382 volatile union iavf_rx_flex_desc *rxdp)
384 volatile struct iavf_32b_rx_flex_desc_comms *desc =
385 (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
388 stat_err = rte_le_to_cpu_16(desc->status_error0);
389 if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
390 mb->ol_flags |= PKT_RX_RSS_HASH;
391 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
394 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
395 if (desc->flow_id != 0xFFFFFFFF) {
396 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
397 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
400 if (rxq->xtr_ol_flag) {
401 uint32_t metadata = 0;
403 stat_err = rte_le_to_cpu_16(desc->status_error1);
405 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
406 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
408 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
410 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
413 mb->ol_flags |= rxq->xtr_ol_flag;
415 *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
422 iavf_rxd_to_pkt_fields_by_comms_aux_v2(struct iavf_rx_queue *rxq,
424 volatile union iavf_rx_flex_desc *rxdp)
426 volatile struct iavf_32b_rx_flex_desc_comms *desc =
427 (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
430 stat_err = rte_le_to_cpu_16(desc->status_error0);
431 if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
432 mb->ol_flags |= PKT_RX_RSS_HASH;
433 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
436 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
437 if (desc->flow_id != 0xFFFFFFFF) {
438 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
439 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
442 if (rxq->xtr_ol_flag) {
443 uint32_t metadata = 0;
445 if (desc->flex_ts.flex.aux0 != 0xFFFF)
446 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
447 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
448 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
451 mb->ol_flags |= rxq->xtr_ol_flag;
453 *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
460 iavf_select_rxd_to_pkt_fields_handler(struct iavf_rx_queue *rxq, uint32_t rxdid)
463 case IAVF_RXDID_COMMS_AUX_VLAN:
464 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
465 rxq->rxd_to_pkt_fields =
466 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
468 case IAVF_RXDID_COMMS_AUX_IPV4:
469 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
470 rxq->rxd_to_pkt_fields =
471 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
473 case IAVF_RXDID_COMMS_AUX_IPV6:
474 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
475 rxq->rxd_to_pkt_fields =
476 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
478 case IAVF_RXDID_COMMS_AUX_IPV6_FLOW:
480 rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
481 rxq->rxd_to_pkt_fields =
482 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
484 case IAVF_RXDID_COMMS_AUX_TCP:
485 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
486 rxq->rxd_to_pkt_fields =
487 iavf_rxd_to_pkt_fields_by_comms_aux_v1;
489 case IAVF_RXDID_COMMS_AUX_IP_OFFSET:
491 rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
492 rxq->rxd_to_pkt_fields =
493 iavf_rxd_to_pkt_fields_by_comms_aux_v2;
495 case IAVF_RXDID_COMMS_OVS_1:
496 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
499 /* update this according to the RXDID for FLEX_DESC_NONE */
500 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
504 if (!rte_pmd_ifd_dynf_proto_xtr_metadata_avail())
505 rxq->xtr_ol_flag = 0;
509 iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
510 uint16_t nb_desc, unsigned int socket_id,
511 const struct rte_eth_rxconf *rx_conf,
512 struct rte_mempool *mp)
514 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
515 struct iavf_adapter *ad =
516 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
517 struct iavf_info *vf =
518 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
519 struct iavf_vsi *vsi = &vf->vsi;
520 struct iavf_rx_queue *rxq;
521 const struct rte_memzone *mz;
525 uint16_t rx_free_thresh;
527 PMD_INIT_FUNC_TRACE();
529 if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
530 nb_desc > IAVF_MAX_RING_DESC ||
531 nb_desc < IAVF_MIN_RING_DESC) {
532 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
537 /* Check free threshold */
538 rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
539 IAVF_DEFAULT_RX_FREE_THRESH :
540 rx_conf->rx_free_thresh;
541 if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
544 /* Free memory if needed */
545 if (dev->data->rx_queues[queue_idx]) {
546 iavf_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
547 dev->data->rx_queues[queue_idx] = NULL;
550 /* Allocate the rx queue data structure */
551 rxq = rte_zmalloc_socket("iavf rxq",
552 sizeof(struct iavf_rx_queue),
556 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
557 "rx queue data structure");
561 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
562 proto_xtr = vf->proto_xtr ? vf->proto_xtr[queue_idx] :
564 rxq->rxdid = iavf_proto_xtr_type_to_rxdid(proto_xtr);
565 rxq->proto_xtr = proto_xtr;
567 rxq->rxdid = IAVF_RXDID_LEGACY_1;
568 rxq->proto_xtr = IAVF_PROTO_XTR_NONE;
571 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
572 struct virtchnl_vlan_supported_caps *stripping_support =
573 &vf->vlan_v2_caps.offloads.stripping_support;
574 uint32_t stripping_cap;
576 if (stripping_support->outer)
577 stripping_cap = stripping_support->outer;
579 stripping_cap = stripping_support->inner;
581 if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
582 rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
583 else if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2_2)
584 rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2;
586 rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
589 iavf_select_rxd_to_pkt_fields_handler(rxq, rxq->rxdid);
592 rxq->nb_rx_desc = nb_desc;
593 rxq->rx_free_thresh = rx_free_thresh;
594 rxq->queue_id = queue_idx;
595 rxq->port_id = dev->data->port_id;
596 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
600 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
601 rxq->crc_len = RTE_ETHER_CRC_LEN;
605 len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
606 rxq->rx_buf_len = RTE_ALIGN(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
608 /* Allocate the software ring. */
609 len = nb_desc + IAVF_RX_MAX_BURST;
611 rte_zmalloc_socket("iavf rx sw ring",
612 sizeof(struct rte_mbuf *) * len,
616 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
621 /* Allocate the maximun number of RX ring hardware descriptor with
622 * a liitle more to support bulk allocate.
624 len = IAVF_MAX_RING_DESC + IAVF_RX_MAX_BURST;
625 ring_size = RTE_ALIGN(len * sizeof(union iavf_rx_desc),
627 mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
628 ring_size, IAVF_RING_BASE_ALIGN,
631 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
632 rte_free(rxq->sw_ring);
636 /* Zero all the descriptors in the ring. */
637 memset(mz->addr, 0, ring_size);
638 rxq->rx_ring_phys_addr = mz->iova;
639 rxq->rx_ring = (union iavf_rx_desc *)mz->addr;
644 dev->data->rx_queues[queue_idx] = rxq;
645 rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
646 rxq->ops = &def_rxq_ops;
648 if (check_rx_bulk_allow(rxq) == true) {
649 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
650 "satisfied. Rx Burst Bulk Alloc function will be "
651 "used on port=%d, queue=%d.",
652 rxq->port_id, rxq->queue_id);
654 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
655 "not satisfied, Scattered Rx is requested "
656 "on port=%d, queue=%d.",
657 rxq->port_id, rxq->queue_id);
658 ad->rx_bulk_alloc_allowed = false;
661 if (check_rx_vec_allow(rxq) == false)
662 ad->rx_vec_allowed = false;
668 iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
671 unsigned int socket_id,
672 const struct rte_eth_txconf *tx_conf)
674 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
675 struct iavf_info *vf =
676 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
677 struct iavf_tx_queue *txq;
678 const struct rte_memzone *mz;
680 uint16_t tx_rs_thresh, tx_free_thresh;
683 PMD_INIT_FUNC_TRACE();
685 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
687 if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
688 nb_desc > IAVF_MAX_RING_DESC ||
689 nb_desc < IAVF_MIN_RING_DESC) {
690 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
695 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
696 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
697 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
698 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
699 check_tx_thresh(nb_desc, tx_rs_thresh, tx_rs_thresh);
701 /* Free memory if needed. */
702 if (dev->data->tx_queues[queue_idx]) {
703 iavf_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
704 dev->data->tx_queues[queue_idx] = NULL;
707 /* Allocate the TX queue data structure. */
708 txq = rte_zmalloc_socket("iavf txq",
709 sizeof(struct iavf_tx_queue),
713 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
714 "tx queue structure");
718 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
719 struct virtchnl_vlan_supported_caps *insertion_support =
720 &vf->vlan_v2_caps.offloads.insertion_support;
721 uint32_t insertion_cap;
723 if (insertion_support->outer)
724 insertion_cap = insertion_support->outer;
726 insertion_cap = insertion_support->inner;
728 if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
729 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
730 else if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2)
731 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2;
733 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
736 txq->nb_tx_desc = nb_desc;
737 txq->rs_thresh = tx_rs_thresh;
738 txq->free_thresh = tx_free_thresh;
739 txq->queue_id = queue_idx;
740 txq->port_id = dev->data->port_id;
741 txq->offloads = offloads;
742 txq->tx_deferred_start = tx_conf->tx_deferred_start;
744 /* Allocate software ring */
746 rte_zmalloc_socket("iavf tx sw ring",
747 sizeof(struct iavf_tx_entry) * nb_desc,
751 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
756 /* Allocate TX hardware ring descriptors. */
757 ring_size = sizeof(struct iavf_tx_desc) * IAVF_MAX_RING_DESC;
758 ring_size = RTE_ALIGN(ring_size, IAVF_DMA_MEM_ALIGN);
759 mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
760 ring_size, IAVF_RING_BASE_ALIGN,
763 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
764 rte_free(txq->sw_ring);
768 txq->tx_ring_phys_addr = mz->iova;
769 txq->tx_ring = (struct iavf_tx_desc *)mz->addr;
774 dev->data->tx_queues[queue_idx] = txq;
775 txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(queue_idx);
776 txq->ops = &def_txq_ops;
778 if (check_tx_vec_allow(txq) == false) {
779 struct iavf_adapter *ad =
780 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
781 ad->tx_vec_allowed = false;
788 iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
790 struct iavf_adapter *adapter =
791 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
792 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
793 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
794 struct iavf_rx_queue *rxq;
797 PMD_DRV_FUNC_TRACE();
799 if (rx_queue_id >= dev->data->nb_rx_queues)
802 rxq = dev->data->rx_queues[rx_queue_id];
804 err = alloc_rxq_mbufs(rxq);
806 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
812 /* Init the RX tail register. */
813 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
814 IAVF_WRITE_FLUSH(hw);
816 /* Ready to switch the queue on */
818 err = iavf_switch_queue(adapter, rx_queue_id, true, true);
820 err = iavf_switch_queue_lv(adapter, rx_queue_id, true, true);
823 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
826 dev->data->rx_queue_state[rx_queue_id] =
827 RTE_ETH_QUEUE_STATE_STARTED;
833 iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
835 struct iavf_adapter *adapter =
836 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
837 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
838 struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
839 struct iavf_tx_queue *txq;
842 PMD_DRV_FUNC_TRACE();
844 if (tx_queue_id >= dev->data->nb_tx_queues)
847 txq = dev->data->tx_queues[tx_queue_id];
849 /* Init the RX tail register. */
850 IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
851 IAVF_WRITE_FLUSH(hw);
853 /* Ready to switch the queue on */
855 err = iavf_switch_queue(adapter, tx_queue_id, false, true);
857 err = iavf_switch_queue_lv(adapter, tx_queue_id, false, true);
860 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
863 dev->data->tx_queue_state[tx_queue_id] =
864 RTE_ETH_QUEUE_STATE_STARTED;
870 iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
872 struct iavf_adapter *adapter =
873 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
874 struct iavf_rx_queue *rxq;
877 PMD_DRV_FUNC_TRACE();
879 if (rx_queue_id >= dev->data->nb_rx_queues)
882 err = iavf_switch_queue(adapter, rx_queue_id, true, false);
884 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
889 rxq = dev->data->rx_queues[rx_queue_id];
890 rxq->ops->release_mbufs(rxq);
892 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
898 iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
900 struct iavf_adapter *adapter =
901 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
902 struct iavf_tx_queue *txq;
905 PMD_DRV_FUNC_TRACE();
907 if (tx_queue_id >= dev->data->nb_tx_queues)
910 err = iavf_switch_queue(adapter, tx_queue_id, false, false);
912 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
917 txq = dev->data->tx_queues[tx_queue_id];
918 txq->ops->release_mbufs(txq);
920 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
926 iavf_dev_rx_queue_release(void *rxq)
928 struct iavf_rx_queue *q = (struct iavf_rx_queue *)rxq;
933 q->ops->release_mbufs(q);
934 rte_free(q->sw_ring);
935 rte_memzone_free(q->mz);
940 iavf_dev_tx_queue_release(void *txq)
942 struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
947 q->ops->release_mbufs(q);
948 rte_free(q->sw_ring);
949 rte_memzone_free(q->mz);
954 iavf_stop_queues(struct rte_eth_dev *dev)
956 struct iavf_adapter *adapter =
957 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
958 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
959 struct iavf_rx_queue *rxq;
960 struct iavf_tx_queue *txq;
963 /* Stop All queues */
964 if (!vf->lv_enabled) {
965 ret = iavf_disable_queues(adapter);
967 PMD_DRV_LOG(WARNING, "Fail to stop queues");
969 ret = iavf_disable_queues_lv(adapter);
971 PMD_DRV_LOG(WARNING, "Fail to stop queues for large VF");
975 PMD_DRV_LOG(WARNING, "Fail to stop queues");
977 for (i = 0; i < dev->data->nb_tx_queues; i++) {
978 txq = dev->data->tx_queues[i];
981 txq->ops->release_mbufs(txq);
983 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
985 for (i = 0; i < dev->data->nb_rx_queues; i++) {
986 rxq = dev->data->rx_queues[i];
989 rxq->ops->release_mbufs(rxq);
991 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
995 #define IAVF_RX_FLEX_ERR0_BITS \
996 ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) | \
997 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) | \
998 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) | \
999 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1000 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1001 (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1004 iavf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union iavf_rx_desc *rxdp)
1006 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1007 (1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
1008 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1010 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
1017 iavf_flex_rxd_to_vlan_tci(struct rte_mbuf *mb,
1018 volatile union iavf_rx_flex_desc *rxdp,
1021 uint16_t vlan_tci = 0;
1023 if (rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1 &&
1024 rte_le_to_cpu_64(rxdp->wb.status_error0) &
1025 (1 << IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S))
1026 vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag1);
1028 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1029 if (rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2 &&
1030 rte_le_to_cpu_16(rxdp->wb.status_error1) &
1031 (1 << IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S))
1032 vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1036 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1037 mb->vlan_tci = vlan_tci;
1041 /* Translate the rx descriptor status and error fields to pkt flags */
1042 static inline uint64_t
1043 iavf_rxd_to_pkt_flags(uint64_t qword)
1046 uint64_t error_bits = (qword >> IAVF_RXD_QW1_ERROR_SHIFT);
1048 #define IAVF_RX_ERR_BITS 0x3f
1050 /* Check if RSS_HASH */
1051 flags = (((qword >> IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
1052 IAVF_RX_DESC_FLTSTAT_RSS_HASH) ==
1053 IAVF_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
1055 /* Check if FDIR Match */
1056 flags |= (qword & (1 << IAVF_RX_DESC_STATUS_FLM_SHIFT) ?
1059 if (likely((error_bits & IAVF_RX_ERR_BITS) == 0)) {
1060 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1064 if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_IPE_SHIFT)))
1065 flags |= PKT_RX_IP_CKSUM_BAD;
1067 flags |= PKT_RX_IP_CKSUM_GOOD;
1069 if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_L4E_SHIFT)))
1070 flags |= PKT_RX_L4_CKSUM_BAD;
1072 flags |= PKT_RX_L4_CKSUM_GOOD;
1074 /* TODO: Oversize error bit is not processed here */
1079 static inline uint64_t
1080 iavf_rxd_build_fdir(volatile union iavf_rx_desc *rxdp, struct rte_mbuf *mb)
1083 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1086 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
1087 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
1088 IAVF_RX_DESC_EXT_STATUS_FLEXBH_MASK;
1090 if (flexbh == IAVF_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
1092 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
1093 flags |= PKT_RX_FDIR_ID;
1097 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
1098 flags |= PKT_RX_FDIR_ID;
1103 #define IAVF_RX_FLEX_ERR0_BITS \
1104 ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) | \
1105 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) | \
1106 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) | \
1107 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1108 (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1109 (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1111 /* Rx L3/L4 checksum */
1112 static inline uint64_t
1113 iavf_flex_rxd_error_to_pkt_flags(uint16_t stat_err0)
1117 /* check if HW has decoded the packet and checksum */
1118 if (unlikely(!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1121 if (likely(!(stat_err0 & IAVF_RX_FLEX_ERR0_BITS))) {
1122 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1126 if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1127 flags |= PKT_RX_IP_CKSUM_BAD;
1129 flags |= PKT_RX_IP_CKSUM_GOOD;
1131 if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1132 flags |= PKT_RX_L4_CKSUM_BAD;
1134 flags |= PKT_RX_L4_CKSUM_GOOD;
1136 if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1137 flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
1142 /* If the number of free RX descriptors is greater than the RX free
1143 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1144 * register. Update the RDT with the value of the last processed RX
1145 * descriptor minus 1, to guarantee that the RDT register is never
1146 * equal to the RDH register, which creates a "full" ring situation
1147 * from the hardware point of view.
1150 iavf_update_rx_tail(struct iavf_rx_queue *rxq, uint16_t nb_hold, uint16_t rx_id)
1152 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1154 if (nb_hold > rxq->rx_free_thresh) {
1156 "port_id=%u queue_id=%u rx_tail=%u nb_hold=%u",
1157 rxq->port_id, rxq->queue_id, rx_id, nb_hold);
1158 rx_id = (uint16_t)((rx_id == 0) ?
1159 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1160 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1163 rxq->nb_rx_hold = nb_hold;
1166 /* implement recv_pkts */
1168 iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1170 volatile union iavf_rx_desc *rx_ring;
1171 volatile union iavf_rx_desc *rxdp;
1172 struct iavf_rx_queue *rxq;
1173 union iavf_rx_desc rxd;
1174 struct rte_mbuf *rxe;
1175 struct rte_eth_dev *dev;
1176 struct rte_mbuf *rxm;
1177 struct rte_mbuf *nmb;
1181 uint16_t rx_packet_len;
1182 uint16_t rx_id, nb_hold;
1185 const uint32_t *ptype_tbl;
1190 rx_id = rxq->rx_tail;
1191 rx_ring = rxq->rx_ring;
1192 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1194 while (nb_rx < nb_pkts) {
1195 rxdp = &rx_ring[rx_id];
1196 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1197 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1198 IAVF_RXD_QW1_STATUS_SHIFT;
1200 /* Check the DD bit first */
1201 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1203 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1205 nmb = rte_mbuf_raw_alloc(rxq->mp);
1206 if (unlikely(!nmb)) {
1207 dev = &rte_eth_devices[rxq->port_id];
1208 dev->data->rx_mbuf_alloc_failed++;
1209 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1210 "queue_id=%u", rxq->port_id, rxq->queue_id);
1216 rxe = rxq->sw_ring[rx_id];
1218 if (unlikely(rx_id == rxq->nb_rx_desc))
1221 /* Prefetch next mbuf */
1222 rte_prefetch0(rxq->sw_ring[rx_id]);
1224 /* When next RX descriptor is on a cache line boundary,
1225 * prefetch the next 4 RX descriptors and next 8 pointers
1228 if ((rx_id & 0x3) == 0) {
1229 rte_prefetch0(&rx_ring[rx_id]);
1230 rte_prefetch0(rxq->sw_ring[rx_id]);
1234 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1235 rxdp->read.hdr_addr = 0;
1236 rxdp->read.pkt_addr = dma_addr;
1238 rx_packet_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1239 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1241 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1242 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1245 rxm->pkt_len = rx_packet_len;
1246 rxm->data_len = rx_packet_len;
1247 rxm->port = rxq->port_id;
1249 iavf_rxd_to_vlan_tci(rxm, &rxd);
1250 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1252 ptype_tbl[(uint8_t)((qword1 &
1253 IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1255 if (pkt_flags & PKT_RX_RSS_HASH)
1257 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1259 if (pkt_flags & PKT_RX_FDIR)
1260 pkt_flags |= iavf_rxd_build_fdir(&rxd, rxm);
1262 rxm->ol_flags |= pkt_flags;
1264 rx_pkts[nb_rx++] = rxm;
1266 rxq->rx_tail = rx_id;
1268 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1273 /* implement recv_pkts for flexible Rx descriptor */
1275 iavf_recv_pkts_flex_rxd(void *rx_queue,
1276 struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1278 volatile union iavf_rx_desc *rx_ring;
1279 volatile union iavf_rx_flex_desc *rxdp;
1280 struct iavf_rx_queue *rxq;
1281 union iavf_rx_flex_desc rxd;
1282 struct rte_mbuf *rxe;
1283 struct rte_eth_dev *dev;
1284 struct rte_mbuf *rxm;
1285 struct rte_mbuf *nmb;
1287 uint16_t rx_stat_err0;
1288 uint16_t rx_packet_len;
1289 uint16_t rx_id, nb_hold;
1292 const uint32_t *ptype_tbl;
1297 rx_id = rxq->rx_tail;
1298 rx_ring = rxq->rx_ring;
1299 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1301 while (nb_rx < nb_pkts) {
1302 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1303 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1305 /* Check the DD bit first */
1306 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1308 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1310 nmb = rte_mbuf_raw_alloc(rxq->mp);
1311 if (unlikely(!nmb)) {
1312 dev = &rte_eth_devices[rxq->port_id];
1313 dev->data->rx_mbuf_alloc_failed++;
1314 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1315 "queue_id=%u", rxq->port_id, rxq->queue_id);
1321 rxe = rxq->sw_ring[rx_id];
1323 if (unlikely(rx_id == rxq->nb_rx_desc))
1326 /* Prefetch next mbuf */
1327 rte_prefetch0(rxq->sw_ring[rx_id]);
1329 /* When next RX descriptor is on a cache line boundary,
1330 * prefetch the next 4 RX descriptors and next 8 pointers
1333 if ((rx_id & 0x3) == 0) {
1334 rte_prefetch0(&rx_ring[rx_id]);
1335 rte_prefetch0(rxq->sw_ring[rx_id]);
1339 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1340 rxdp->read.hdr_addr = 0;
1341 rxdp->read.pkt_addr = dma_addr;
1343 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1344 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1346 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1347 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1350 rxm->pkt_len = rx_packet_len;
1351 rxm->data_len = rx_packet_len;
1352 rxm->port = rxq->port_id;
1354 rxm->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1355 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1356 iavf_flex_rxd_to_vlan_tci(rxm, &rxd, rxq->rx_flags);
1357 rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
1358 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1359 rxm->ol_flags |= pkt_flags;
1361 rx_pkts[nb_rx++] = rxm;
1363 rxq->rx_tail = rx_id;
1365 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1370 /* implement recv_scattered_pkts for flexible Rx descriptor */
1372 iavf_recv_scattered_pkts_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1375 struct iavf_rx_queue *rxq = rx_queue;
1376 union iavf_rx_flex_desc rxd;
1377 struct rte_mbuf *rxe;
1378 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1379 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1380 struct rte_mbuf *nmb, *rxm;
1381 uint16_t rx_id = rxq->rx_tail;
1382 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1383 struct rte_eth_dev *dev;
1384 uint16_t rx_stat_err0;
1388 volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1389 volatile union iavf_rx_flex_desc *rxdp;
1390 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1392 while (nb_rx < nb_pkts) {
1393 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1394 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1396 /* Check the DD bit */
1397 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1399 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1401 nmb = rte_mbuf_raw_alloc(rxq->mp);
1402 if (unlikely(!nmb)) {
1403 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1404 "queue_id=%u", rxq->port_id, rxq->queue_id);
1405 dev = &rte_eth_devices[rxq->port_id];
1406 dev->data->rx_mbuf_alloc_failed++;
1412 rxe = rxq->sw_ring[rx_id];
1414 if (rx_id == rxq->nb_rx_desc)
1417 /* Prefetch next mbuf */
1418 rte_prefetch0(rxq->sw_ring[rx_id]);
1420 /* When next RX descriptor is on a cache line boundary,
1421 * prefetch the next 4 RX descriptors and next 8 pointers
1424 if ((rx_id & 0x3) == 0) {
1425 rte_prefetch0(&rx_ring[rx_id]);
1426 rte_prefetch0(rxq->sw_ring[rx_id]);
1431 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1433 /* Set data buffer address and data length of the mbuf */
1434 rxdp->read.hdr_addr = 0;
1435 rxdp->read.pkt_addr = dma_addr;
1436 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1437 IAVF_RX_FLX_DESC_PKT_LEN_M;
1438 rxm->data_len = rx_packet_len;
1439 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1441 /* If this is the first buffer of the received packet, set the
1442 * pointer to the first mbuf of the packet and initialize its
1443 * context. Otherwise, update the total length and the number
1444 * of segments of the current scattered packet, and update the
1445 * pointer to the last mbuf of the current packet.
1449 first_seg->nb_segs = 1;
1450 first_seg->pkt_len = rx_packet_len;
1452 first_seg->pkt_len =
1453 (uint16_t)(first_seg->pkt_len +
1455 first_seg->nb_segs++;
1456 last_seg->next = rxm;
1459 /* If this is not the last buffer of the received packet,
1460 * update the pointer to the last mbuf of the current scattered
1461 * packet and continue to parse the RX ring.
1463 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_EOF_S))) {
1468 /* This is the last buffer of the received packet. If the CRC
1469 * is not stripped by the hardware:
1470 * - Subtract the CRC length from the total packet length.
1471 * - If the last buffer only contains the whole CRC or a part
1472 * of it, free the mbuf associated to the last buffer. If part
1473 * of the CRC is also contained in the previous mbuf, subtract
1474 * the length of that CRC part from the data length of the
1478 if (unlikely(rxq->crc_len > 0)) {
1479 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1480 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1481 rte_pktmbuf_free_seg(rxm);
1482 first_seg->nb_segs--;
1483 last_seg->data_len =
1484 (uint16_t)(last_seg->data_len -
1485 (RTE_ETHER_CRC_LEN - rx_packet_len));
1486 last_seg->next = NULL;
1488 rxm->data_len = (uint16_t)(rx_packet_len -
1493 first_seg->port = rxq->port_id;
1494 first_seg->ol_flags = 0;
1495 first_seg->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1496 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1497 iavf_flex_rxd_to_vlan_tci(first_seg, &rxd, rxq->rx_flags);
1498 rxq->rxd_to_pkt_fields(rxq, first_seg, &rxd);
1499 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1501 first_seg->ol_flags |= pkt_flags;
1503 /* Prefetch data of first segment, if configured to do so. */
1504 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1505 first_seg->data_off));
1506 rx_pkts[nb_rx++] = first_seg;
1510 /* Record index of the next RX descriptor to probe. */
1511 rxq->rx_tail = rx_id;
1512 rxq->pkt_first_seg = first_seg;
1513 rxq->pkt_last_seg = last_seg;
1515 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1520 /* implement recv_scattered_pkts */
1522 iavf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1525 struct iavf_rx_queue *rxq = rx_queue;
1526 union iavf_rx_desc rxd;
1527 struct rte_mbuf *rxe;
1528 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1529 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1530 struct rte_mbuf *nmb, *rxm;
1531 uint16_t rx_id = rxq->rx_tail;
1532 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1533 struct rte_eth_dev *dev;
1539 volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1540 volatile union iavf_rx_desc *rxdp;
1541 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1543 while (nb_rx < nb_pkts) {
1544 rxdp = &rx_ring[rx_id];
1545 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1546 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1547 IAVF_RXD_QW1_STATUS_SHIFT;
1549 /* Check the DD bit */
1550 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1552 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1554 nmb = rte_mbuf_raw_alloc(rxq->mp);
1555 if (unlikely(!nmb)) {
1556 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1557 "queue_id=%u", rxq->port_id, rxq->queue_id);
1558 dev = &rte_eth_devices[rxq->port_id];
1559 dev->data->rx_mbuf_alloc_failed++;
1565 rxe = rxq->sw_ring[rx_id];
1567 if (rx_id == rxq->nb_rx_desc)
1570 /* Prefetch next mbuf */
1571 rte_prefetch0(rxq->sw_ring[rx_id]);
1573 /* When next RX descriptor is on a cache line boundary,
1574 * prefetch the next 4 RX descriptors and next 8 pointers
1577 if ((rx_id & 0x3) == 0) {
1578 rte_prefetch0(&rx_ring[rx_id]);
1579 rte_prefetch0(rxq->sw_ring[rx_id]);
1584 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1586 /* Set data buffer address and data length of the mbuf */
1587 rxdp->read.hdr_addr = 0;
1588 rxdp->read.pkt_addr = dma_addr;
1589 rx_packet_len = (qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1590 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
1591 rxm->data_len = rx_packet_len;
1592 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1594 /* If this is the first buffer of the received packet, set the
1595 * pointer to the first mbuf of the packet and initialize its
1596 * context. Otherwise, update the total length and the number
1597 * of segments of the current scattered packet, and update the
1598 * pointer to the last mbuf of the current packet.
1602 first_seg->nb_segs = 1;
1603 first_seg->pkt_len = rx_packet_len;
1605 first_seg->pkt_len =
1606 (uint16_t)(first_seg->pkt_len +
1608 first_seg->nb_segs++;
1609 last_seg->next = rxm;
1612 /* If this is not the last buffer of the received packet,
1613 * update the pointer to the last mbuf of the current scattered
1614 * packet and continue to parse the RX ring.
1616 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT))) {
1621 /* This is the last buffer of the received packet. If the CRC
1622 * is not stripped by the hardware:
1623 * - Subtract the CRC length from the total packet length.
1624 * - If the last buffer only contains the whole CRC or a part
1625 * of it, free the mbuf associated to the last buffer. If part
1626 * of the CRC is also contained in the previous mbuf, subtract
1627 * the length of that CRC part from the data length of the
1631 if (unlikely(rxq->crc_len > 0)) {
1632 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1633 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1634 rte_pktmbuf_free_seg(rxm);
1635 first_seg->nb_segs--;
1636 last_seg->data_len =
1637 (uint16_t)(last_seg->data_len -
1638 (RTE_ETHER_CRC_LEN - rx_packet_len));
1639 last_seg->next = NULL;
1641 rxm->data_len = (uint16_t)(rx_packet_len -
1645 first_seg->port = rxq->port_id;
1646 first_seg->ol_flags = 0;
1647 iavf_rxd_to_vlan_tci(first_seg, &rxd);
1648 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1649 first_seg->packet_type =
1650 ptype_tbl[(uint8_t)((qword1 &
1651 IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1653 if (pkt_flags & PKT_RX_RSS_HASH)
1654 first_seg->hash.rss =
1655 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1657 if (pkt_flags & PKT_RX_FDIR)
1658 pkt_flags |= iavf_rxd_build_fdir(&rxd, first_seg);
1660 first_seg->ol_flags |= pkt_flags;
1662 /* Prefetch data of first segment, if configured to do so. */
1663 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1664 first_seg->data_off));
1665 rx_pkts[nb_rx++] = first_seg;
1669 /* Record index of the next RX descriptor to probe. */
1670 rxq->rx_tail = rx_id;
1671 rxq->pkt_first_seg = first_seg;
1672 rxq->pkt_last_seg = last_seg;
1674 iavf_update_rx_tail(rxq, nb_hold, rx_id);
1679 #define IAVF_LOOK_AHEAD 8
1681 iavf_rx_scan_hw_ring_flex_rxd(struct iavf_rx_queue *rxq)
1683 volatile union iavf_rx_flex_desc *rxdp;
1684 struct rte_mbuf **rxep;
1685 struct rte_mbuf *mb;
1688 int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1689 int32_t i, j, nb_rx = 0;
1691 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1693 rxdp = (volatile union iavf_rx_flex_desc *)&rxq->rx_ring[rxq->rx_tail];
1694 rxep = &rxq->sw_ring[rxq->rx_tail];
1696 stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1698 /* Make sure there is at least 1 packet to receive */
1699 if (!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1702 /* Scan LOOK_AHEAD descriptors at a time to determine which
1703 * descriptors reference packets that are ready to be received.
1705 for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1706 rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1707 /* Read desc statuses backwards to avoid race condition */
1708 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--)
1709 s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1713 /* Compute how many status bits were set */
1714 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1715 nb_dd += s[j] & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S);
1719 /* Translate descriptor info to mbuf parameters */
1720 for (j = 0; j < nb_dd; j++) {
1721 IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1723 i * IAVF_LOOK_AHEAD + j);
1726 pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1727 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1728 mb->data_len = pkt_len;
1729 mb->pkt_len = pkt_len;
1732 mb->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1733 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1734 iavf_flex_rxd_to_vlan_tci(mb, &rxdp[j], rxq->rx_flags);
1735 rxq->rxd_to_pkt_fields(rxq, mb, &rxdp[j]);
1736 stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1737 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(stat_err0);
1739 mb->ol_flags |= pkt_flags;
1742 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1743 rxq->rx_stage[i + j] = rxep[j];
1745 if (nb_dd != IAVF_LOOK_AHEAD)
1749 /* Clear software ring entries */
1750 for (i = 0; i < nb_rx; i++)
1751 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1757 iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
1759 volatile union iavf_rx_desc *rxdp;
1760 struct rte_mbuf **rxep;
1761 struct rte_mbuf *mb;
1765 int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1766 int32_t i, j, nb_rx = 0;
1768 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1770 rxdp = &rxq->rx_ring[rxq->rx_tail];
1771 rxep = &rxq->sw_ring[rxq->rx_tail];
1773 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1774 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1775 IAVF_RXD_QW1_STATUS_SHIFT;
1777 /* Make sure there is at least 1 packet to receive */
1778 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1781 /* Scan LOOK_AHEAD descriptors at a time to determine which
1782 * descriptors reference packets that are ready to be received.
1784 for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1785 rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1786 /* Read desc statuses backwards to avoid race condition */
1787 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--) {
1788 qword1 = rte_le_to_cpu_64(
1789 rxdp[j].wb.qword1.status_error_len);
1790 s[j] = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1791 IAVF_RXD_QW1_STATUS_SHIFT;
1796 /* Compute how many status bits were set */
1797 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1798 nb_dd += s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
1802 /* Translate descriptor info to mbuf parameters */
1803 for (j = 0; j < nb_dd; j++) {
1804 IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1805 rxq->rx_tail + i * IAVF_LOOK_AHEAD + j);
1808 qword1 = rte_le_to_cpu_64
1809 (rxdp[j].wb.qword1.status_error_len);
1810 pkt_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1811 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1812 mb->data_len = pkt_len;
1813 mb->pkt_len = pkt_len;
1815 iavf_rxd_to_vlan_tci(mb, &rxdp[j]);
1816 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1818 ptype_tbl[(uint8_t)((qword1 &
1819 IAVF_RXD_QW1_PTYPE_MASK) >>
1820 IAVF_RXD_QW1_PTYPE_SHIFT)];
1822 if (pkt_flags & PKT_RX_RSS_HASH)
1823 mb->hash.rss = rte_le_to_cpu_32(
1824 rxdp[j].wb.qword0.hi_dword.rss);
1826 if (pkt_flags & PKT_RX_FDIR)
1827 pkt_flags |= iavf_rxd_build_fdir(&rxdp[j], mb);
1829 mb->ol_flags |= pkt_flags;
1832 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1833 rxq->rx_stage[i + j] = rxep[j];
1835 if (nb_dd != IAVF_LOOK_AHEAD)
1839 /* Clear software ring entries */
1840 for (i = 0; i < nb_rx; i++)
1841 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1846 static inline uint16_t
1847 iavf_rx_fill_from_stage(struct iavf_rx_queue *rxq,
1848 struct rte_mbuf **rx_pkts,
1852 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1854 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1856 for (i = 0; i < nb_pkts; i++)
1857 rx_pkts[i] = stage[i];
1859 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1860 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1866 iavf_rx_alloc_bufs(struct iavf_rx_queue *rxq)
1868 volatile union iavf_rx_desc *rxdp;
1869 struct rte_mbuf **rxep;
1870 struct rte_mbuf *mb;
1871 uint16_t alloc_idx, i;
1875 /* Allocate buffers in bulk */
1876 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1877 (rxq->rx_free_thresh - 1));
1878 rxep = &rxq->sw_ring[alloc_idx];
1879 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1880 rxq->rx_free_thresh);
1881 if (unlikely(diag != 0)) {
1882 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1886 rxdp = &rxq->rx_ring[alloc_idx];
1887 for (i = 0; i < rxq->rx_free_thresh; i++) {
1888 if (likely(i < (rxq->rx_free_thresh - 1)))
1889 /* Prefetch next mbuf */
1890 rte_prefetch0(rxep[i + 1]);
1893 rte_mbuf_refcnt_set(mb, 1);
1895 mb->data_off = RTE_PKTMBUF_HEADROOM;
1897 mb->port = rxq->port_id;
1898 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1899 rxdp[i].read.hdr_addr = 0;
1900 rxdp[i].read.pkt_addr = dma_addr;
1903 /* Update rx tail register */
1905 IAVF_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
1907 rxq->rx_free_trigger =
1908 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1909 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1910 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1915 static inline uint16_t
1916 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1918 struct iavf_rx_queue *rxq = (struct iavf_rx_queue *)rx_queue;
1924 if (rxq->rx_nb_avail)
1925 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1927 if (rxq->rxdid >= IAVF_RXDID_FLEX_NIC && rxq->rxdid <= IAVF_RXDID_LAST)
1928 nb_rx = (uint16_t)iavf_rx_scan_hw_ring_flex_rxd(rxq);
1930 nb_rx = (uint16_t)iavf_rx_scan_hw_ring(rxq);
1931 rxq->rx_next_avail = 0;
1932 rxq->rx_nb_avail = nb_rx;
1933 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1935 if (rxq->rx_tail > rxq->rx_free_trigger) {
1936 if (iavf_rx_alloc_bufs(rxq) != 0) {
1939 /* TODO: count rx_mbuf_alloc_failed here */
1941 rxq->rx_nb_avail = 0;
1942 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1943 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1944 rxq->sw_ring[j] = rxq->rx_stage[i];
1950 if (rxq->rx_tail >= rxq->nb_rx_desc)
1953 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
1954 rxq->port_id, rxq->queue_id,
1955 rxq->rx_tail, nb_rx);
1957 if (rxq->rx_nb_avail)
1958 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1964 iavf_recv_pkts_bulk_alloc(void *rx_queue,
1965 struct rte_mbuf **rx_pkts,
1968 uint16_t nb_rx = 0, n, count;
1970 if (unlikely(nb_pkts == 0))
1973 if (likely(nb_pkts <= IAVF_RX_MAX_BURST))
1974 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1977 n = RTE_MIN(nb_pkts, IAVF_RX_MAX_BURST);
1978 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1979 nb_rx = (uint16_t)(nb_rx + count);
1980 nb_pkts = (uint16_t)(nb_pkts - count);
1989 iavf_xmit_cleanup(struct iavf_tx_queue *txq)
1991 struct iavf_tx_entry *sw_ring = txq->sw_ring;
1992 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1993 uint16_t nb_tx_desc = txq->nb_tx_desc;
1994 uint16_t desc_to_clean_to;
1995 uint16_t nb_tx_to_clean;
1997 volatile struct iavf_tx_desc *txd = txq->tx_ring;
1999 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
2000 if (desc_to_clean_to >= nb_tx_desc)
2001 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2003 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2004 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
2005 rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
2006 rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE)) {
2007 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
2008 "(port=%d queue=%d)", desc_to_clean_to,
2009 txq->port_id, txq->queue_id);
2013 if (last_desc_cleaned > desc_to_clean_to)
2014 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2017 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2020 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2022 txq->last_desc_cleaned = desc_to_clean_to;
2023 txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
2028 /* Check if the context descriptor is needed for TX offloading */
2029 static inline uint16_t
2030 iavf_calc_context_desc(uint64_t flags, uint8_t vlan_flag)
2032 if (flags & PKT_TX_TCP_SEG)
2034 if (flags & PKT_TX_VLAN_PKT &&
2035 vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2)
2041 iavf_txd_enable_checksum(uint64_t ol_flags,
2043 uint32_t *td_offset,
2044 union iavf_tx_offload tx_offload)
2047 *td_offset |= (tx_offload.l2_len >> 1) <<
2048 IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
2050 /* Enable L3 checksum offloads */
2051 if (ol_flags & PKT_TX_IP_CKSUM) {
2052 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
2053 *td_offset |= (tx_offload.l3_len >> 2) <<
2054 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2055 } else if (ol_flags & PKT_TX_IPV4) {
2056 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4;
2057 *td_offset |= (tx_offload.l3_len >> 2) <<
2058 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2059 } else if (ol_flags & PKT_TX_IPV6) {
2060 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV6;
2061 *td_offset |= (tx_offload.l3_len >> 2) <<
2062 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2065 if (ol_flags & PKT_TX_TCP_SEG) {
2066 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2067 *td_offset |= (tx_offload.l4_len >> 2) <<
2068 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2072 /* Enable L4 checksum offloads */
2073 switch (ol_flags & PKT_TX_L4_MASK) {
2074 case PKT_TX_TCP_CKSUM:
2075 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2076 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2077 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2079 case PKT_TX_SCTP_CKSUM:
2080 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
2081 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2082 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2084 case PKT_TX_UDP_CKSUM:
2085 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
2086 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2087 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2094 /* set TSO context descriptor
2095 * support IP -> L4 and IP -> IP -> L4
2097 static inline uint64_t
2098 iavf_set_tso_ctx(struct rte_mbuf *mbuf, union iavf_tx_offload tx_offload)
2100 uint64_t ctx_desc = 0;
2101 uint32_t cd_cmd, hdr_len, cd_tso_len;
2103 if (!tx_offload.l4_len) {
2104 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2108 hdr_len = tx_offload.l2_len +
2112 cd_cmd = IAVF_TX_CTX_DESC_TSO;
2113 cd_tso_len = mbuf->pkt_len - hdr_len;
2114 ctx_desc |= ((uint64_t)cd_cmd << IAVF_TXD_CTX_QW1_CMD_SHIFT) |
2115 ((uint64_t)cd_tso_len << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) |
2116 ((uint64_t)mbuf->tso_segsz << IAVF_TXD_CTX_QW1_MSS_SHIFT);
2121 /* Construct the tx flags */
2122 static inline uint64_t
2123 iavf_build_ctob(uint32_t td_cmd, uint32_t td_offset, unsigned int size,
2126 return rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DATA |
2127 ((uint64_t)td_cmd << IAVF_TXD_QW1_CMD_SHIFT) |
2128 ((uint64_t)td_offset <<
2129 IAVF_TXD_QW1_OFFSET_SHIFT) |
2131 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT) |
2132 ((uint64_t)td_tag <<
2133 IAVF_TXD_QW1_L2TAG1_SHIFT));
2138 iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2140 volatile struct iavf_tx_desc *txd;
2141 volatile struct iavf_tx_desc *txr;
2142 struct iavf_tx_queue *txq;
2143 struct iavf_tx_entry *sw_ring;
2144 struct iavf_tx_entry *txe, *txn;
2145 struct rte_mbuf *tx_pkt;
2146 struct rte_mbuf *m_seg;
2157 uint64_t buf_dma_addr;
2158 uint16_t cd_l2tag2 = 0;
2159 union iavf_tx_offload tx_offload = {0};
2162 sw_ring = txq->sw_ring;
2164 tx_id = txq->tx_tail;
2165 txe = &sw_ring[tx_id];
2167 /* Check if the descriptor ring needs to be cleaned. */
2168 if (txq->nb_free < txq->free_thresh)
2169 (void)iavf_xmit_cleanup(txq);
2171 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2176 tx_pkt = *tx_pkts++;
2177 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
2179 ol_flags = tx_pkt->ol_flags;
2180 tx_offload.l2_len = tx_pkt->l2_len;
2181 tx_offload.l3_len = tx_pkt->l3_len;
2182 tx_offload.l4_len = tx_pkt->l4_len;
2183 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2184 /* Calculate the number of context descriptors needed. */
2185 nb_ctx = iavf_calc_context_desc(ol_flags, txq->vlan_flag);
2187 /* The number of descriptors that must be allocated for
2188 * a packet equals to the number of the segments of that
2189 * packet plus 1 context descriptor if needed.
2191 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2192 tx_last = (uint16_t)(tx_id + nb_used - 1);
2195 if (tx_last >= txq->nb_tx_desc)
2196 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2198 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u"
2199 " tx_first=%u tx_last=%u",
2200 txq->port_id, txq->queue_id, tx_id, tx_last);
2202 if (nb_used > txq->nb_free) {
2203 if (iavf_xmit_cleanup(txq)) {
2208 if (unlikely(nb_used > txq->rs_thresh)) {
2209 while (nb_used > txq->nb_free) {
2210 if (iavf_xmit_cleanup(txq)) {
2219 /* Descriptor based VLAN insertion */
2220 if (ol_flags & PKT_TX_VLAN_PKT &&
2221 txq->vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1) {
2222 td_cmd |= IAVF_TX_DESC_CMD_IL2TAG1;
2223 td_tag = tx_pkt->vlan_tci;
2226 /* According to datasheet, the bit2 is reserved and must be
2231 /* Enable checksum offloading */
2232 if (ol_flags & IAVF_TX_CKSUM_OFFLOAD_MASK)
2233 iavf_txd_enable_checksum(ol_flags, &td_cmd,
2234 &td_offset, tx_offload);
2237 /* Setup TX context descriptor if required */
2238 uint64_t cd_type_cmd_tso_mss =
2239 IAVF_TX_DESC_DTYPE_CONTEXT;
2240 volatile struct iavf_tx_context_desc *ctx_txd =
2241 (volatile struct iavf_tx_context_desc *)
2244 txn = &sw_ring[txe->next_id];
2245 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2247 rte_pktmbuf_free_seg(txe->mbuf);
2252 if (ol_flags & PKT_TX_TCP_SEG)
2253 cd_type_cmd_tso_mss |=
2254 iavf_set_tso_ctx(tx_pkt, tx_offload);
2256 if (ol_flags & PKT_TX_VLAN_PKT &&
2257 txq->vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2) {
2258 cd_type_cmd_tso_mss |= IAVF_TX_CTX_DESC_IL2TAG2
2259 << IAVF_TXD_CTX_QW1_CMD_SHIFT;
2260 cd_l2tag2 = tx_pkt->vlan_tci;
2263 ctx_txd->type_cmd_tso_mss =
2264 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2265 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2267 IAVF_DUMP_TX_DESC(txq, &txr[tx_id], tx_id);
2268 txe->last_id = tx_last;
2269 tx_id = txe->next_id;
2276 txn = &sw_ring[txe->next_id];
2279 rte_pktmbuf_free_seg(txe->mbuf);
2282 /* Setup TX Descriptor */
2283 slen = m_seg->data_len;
2284 buf_dma_addr = rte_mbuf_data_iova(m_seg);
2285 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
2286 txd->cmd_type_offset_bsz = iavf_build_ctob(td_cmd,
2291 IAVF_DUMP_TX_DESC(txq, txd, tx_id);
2292 txe->last_id = tx_last;
2293 tx_id = txe->next_id;
2295 m_seg = m_seg->next;
2298 /* The last packet data descriptor needs End Of Packet (EOP) */
2299 td_cmd |= IAVF_TX_DESC_CMD_EOP;
2300 txq->nb_used = (uint16_t)(txq->nb_used + nb_used);
2301 txq->nb_free = (uint16_t)(txq->nb_free - nb_used);
2303 if (txq->nb_used >= txq->rs_thresh) {
2304 PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
2305 "%4u (port=%d queue=%d)",
2306 tx_last, txq->port_id, txq->queue_id);
2308 td_cmd |= IAVF_TX_DESC_CMD_RS;
2310 /* Update txq RS bit counters */
2314 txd->cmd_type_offset_bsz |=
2315 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2316 IAVF_TXD_QW1_CMD_SHIFT);
2317 IAVF_DUMP_TX_DESC(txq, txd, tx_id);
2323 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
2324 txq->port_id, txq->queue_id, tx_id, nb_tx);
2326 IAVF_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
2327 txq->tx_tail = tx_id;
2332 /* TX prep functions */
2334 iavf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2341 for (i = 0; i < nb_pkts; i++) {
2343 ol_flags = m->ol_flags;
2345 /* Check condition for nb_segs > IAVF_TX_MAX_MTU_SEG. */
2346 if (!(ol_flags & PKT_TX_TCP_SEG)) {
2347 if (m->nb_segs > IAVF_TX_MAX_MTU_SEG) {
2351 } else if ((m->tso_segsz < IAVF_MIN_TSO_MSS) ||
2352 (m->tso_segsz > IAVF_MAX_TSO_MSS)) {
2353 /* MSS outside the range are considered malicious */
2358 if (ol_flags & IAVF_TX_OFFLOAD_NOTSUP_MASK) {
2359 rte_errno = ENOTSUP;
2363 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2364 ret = rte_validate_tx_offload(m);
2370 ret = rte_net_intel_cksum_prepare(m);
2380 /* choose rx function*/
2382 iavf_set_rx_function(struct rte_eth_dev *dev)
2384 struct iavf_adapter *adapter =
2385 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2386 struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2389 struct iavf_rx_queue *rxq;
2391 bool use_avx2 = false;
2392 #ifdef CC_AVX512_SUPPORT
2393 bool use_avx512 = false;
2396 if (!iavf_rx_vec_dev_check(dev) &&
2397 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2398 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2399 rxq = dev->data->rx_queues[i];
2400 (void)iavf_rxq_vec_setup(rxq);
2403 if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2404 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2405 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2407 #ifdef CC_AVX512_SUPPORT
2408 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2409 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2410 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2414 if (dev->data->scattered_rx) {
2416 "Using %sVector Scattered Rx (port %d).",
2417 use_avx2 ? "avx2 " : "",
2418 dev->data->port_id);
2419 if (vf->vf_res->vf_cap_flags &
2420 VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
2421 dev->rx_pkt_burst = use_avx2 ?
2422 iavf_recv_scattered_pkts_vec_avx2_flex_rxd :
2423 iavf_recv_scattered_pkts_vec_flex_rxd;
2424 #ifdef CC_AVX512_SUPPORT
2427 iavf_recv_scattered_pkts_vec_avx512_flex_rxd;
2430 dev->rx_pkt_burst = use_avx2 ?
2431 iavf_recv_scattered_pkts_vec_avx2 :
2432 iavf_recv_scattered_pkts_vec;
2433 #ifdef CC_AVX512_SUPPORT
2436 iavf_recv_scattered_pkts_vec_avx512;
2440 PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2441 use_avx2 ? "avx2 " : "",
2442 dev->data->port_id);
2443 if (vf->vf_res->vf_cap_flags &
2444 VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
2445 dev->rx_pkt_burst = use_avx2 ?
2446 iavf_recv_pkts_vec_avx2_flex_rxd :
2447 iavf_recv_pkts_vec_flex_rxd;
2448 #ifdef CC_AVX512_SUPPORT
2451 iavf_recv_pkts_vec_avx512_flex_rxd;
2454 dev->rx_pkt_burst = use_avx2 ?
2455 iavf_recv_pkts_vec_avx2 :
2457 #ifdef CC_AVX512_SUPPORT
2460 iavf_recv_pkts_vec_avx512;
2469 if (dev->data->scattered_rx) {
2470 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
2471 dev->data->port_id);
2472 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2473 dev->rx_pkt_burst = iavf_recv_scattered_pkts_flex_rxd;
2475 dev->rx_pkt_burst = iavf_recv_scattered_pkts;
2476 } else if (adapter->rx_bulk_alloc_allowed) {
2477 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
2478 dev->data->port_id);
2479 dev->rx_pkt_burst = iavf_recv_pkts_bulk_alloc;
2481 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
2482 dev->data->port_id);
2483 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2484 dev->rx_pkt_burst = iavf_recv_pkts_flex_rxd;
2486 dev->rx_pkt_burst = iavf_recv_pkts;
2490 /* choose tx function*/
2492 iavf_set_tx_function(struct rte_eth_dev *dev)
2495 struct iavf_tx_queue *txq;
2497 bool use_avx2 = false;
2498 #ifdef CC_AVX512_SUPPORT
2499 bool use_avx512 = false;
2502 if (!iavf_tx_vec_dev_check(dev) &&
2503 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2504 if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2505 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2506 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2508 #ifdef CC_AVX512_SUPPORT
2509 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2510 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2511 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2515 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2516 use_avx2 ? "avx2 " : "",
2517 dev->data->port_id);
2518 dev->tx_pkt_burst = use_avx2 ?
2519 iavf_xmit_pkts_vec_avx2 :
2521 #ifdef CC_AVX512_SUPPORT
2523 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512;
2525 dev->tx_pkt_prepare = NULL;
2527 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2528 txq = dev->data->tx_queues[i];
2531 #ifdef CC_AVX512_SUPPORT
2533 iavf_txq_vec_setup_avx512(txq);
2535 iavf_txq_vec_setup(txq);
2537 iavf_txq_vec_setup(txq);
2545 PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
2546 dev->data->port_id);
2547 dev->tx_pkt_burst = iavf_xmit_pkts;
2548 dev->tx_pkt_prepare = iavf_prep_pkts;
2552 iavf_tx_done_cleanup_full(struct iavf_tx_queue *txq,
2555 struct iavf_tx_entry *swr_ring = txq->sw_ring;
2556 uint16_t i, tx_last, tx_id;
2557 uint16_t nb_tx_free_last;
2558 uint16_t nb_tx_to_clean;
2561 /* Start free mbuf from the next of tx_tail */
2562 tx_last = txq->tx_tail;
2563 tx_id = swr_ring[tx_last].next_id;
2565 if (txq->nb_free == 0 && iavf_xmit_cleanup(txq))
2568 nb_tx_to_clean = txq->nb_free;
2569 nb_tx_free_last = txq->nb_free;
2571 free_cnt = txq->nb_tx_desc;
2573 /* Loop through swr_ring to count the amount of
2574 * freeable mubfs and packets.
2576 for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2577 for (i = 0; i < nb_tx_to_clean &&
2578 pkt_cnt < free_cnt &&
2579 tx_id != tx_last; i++) {
2580 if (swr_ring[tx_id].mbuf != NULL) {
2581 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2582 swr_ring[tx_id].mbuf = NULL;
2585 * last segment in the packet,
2586 * increment packet count
2588 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2591 tx_id = swr_ring[tx_id].next_id;
2594 if (txq->rs_thresh > txq->nb_tx_desc -
2595 txq->nb_free || tx_id == tx_last)
2598 if (pkt_cnt < free_cnt) {
2599 if (iavf_xmit_cleanup(txq))
2602 nb_tx_to_clean = txq->nb_free - nb_tx_free_last;
2603 nb_tx_free_last = txq->nb_free;
2607 return (int)pkt_cnt;
2611 iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt)
2613 struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
2615 return iavf_tx_done_cleanup_full(q, free_cnt);
2619 iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2620 struct rte_eth_rxq_info *qinfo)
2622 struct iavf_rx_queue *rxq;
2624 rxq = dev->data->rx_queues[queue_id];
2626 qinfo->mp = rxq->mp;
2627 qinfo->scattered_rx = dev->data->scattered_rx;
2628 qinfo->nb_desc = rxq->nb_rx_desc;
2630 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2631 qinfo->conf.rx_drop_en = true;
2632 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2636 iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2637 struct rte_eth_txq_info *qinfo)
2639 struct iavf_tx_queue *txq;
2641 txq = dev->data->tx_queues[queue_id];
2643 qinfo->nb_desc = txq->nb_tx_desc;
2645 qinfo->conf.tx_free_thresh = txq->free_thresh;
2646 qinfo->conf.tx_rs_thresh = txq->rs_thresh;
2647 qinfo->conf.offloads = txq->offloads;
2648 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2651 /* Get the number of used descriptors of a rx queue */
2653 iavf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id)
2655 #define IAVF_RXQ_SCAN_INTERVAL 4
2656 volatile union iavf_rx_desc *rxdp;
2657 struct iavf_rx_queue *rxq;
2660 rxq = dev->data->rx_queues[queue_id];
2661 rxdp = &rxq->rx_ring[rxq->rx_tail];
2663 while ((desc < rxq->nb_rx_desc) &&
2664 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2665 IAVF_RXD_QW1_STATUS_MASK) >> IAVF_RXD_QW1_STATUS_SHIFT) &
2666 (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) {
2667 /* Check the DD bit of a rx descriptor of each 4 in a group,
2668 * to avoid checking too frequently and downgrading performance
2671 desc += IAVF_RXQ_SCAN_INTERVAL;
2672 rxdp += IAVF_RXQ_SCAN_INTERVAL;
2673 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2674 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2675 desc - rxq->nb_rx_desc]);
2682 iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
2684 struct iavf_rx_queue *rxq = rx_queue;
2685 volatile uint64_t *status;
2689 if (unlikely(offset >= rxq->nb_rx_desc))
2692 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2693 return RTE_ETH_RX_DESC_UNAVAIL;
2695 desc = rxq->rx_tail + offset;
2696 if (desc >= rxq->nb_rx_desc)
2697 desc -= rxq->nb_rx_desc;
2699 status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2700 mask = rte_le_to_cpu_64((1ULL << IAVF_RX_DESC_STATUS_DD_SHIFT)
2701 << IAVF_RXD_QW1_STATUS_SHIFT);
2703 return RTE_ETH_RX_DESC_DONE;
2705 return RTE_ETH_RX_DESC_AVAIL;
2709 iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
2711 struct iavf_tx_queue *txq = tx_queue;
2712 volatile uint64_t *status;
2713 uint64_t mask, expect;
2716 if (unlikely(offset >= txq->nb_tx_desc))
2719 desc = txq->tx_tail + offset;
2720 /* go to next desc that has the RS bit */
2721 desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
2723 if (desc >= txq->nb_tx_desc) {
2724 desc -= txq->nb_tx_desc;
2725 if (desc >= txq->nb_tx_desc)
2726 desc -= txq->nb_tx_desc;
2729 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2730 mask = rte_le_to_cpu_64(IAVF_TXD_QW1_DTYPE_MASK);
2731 expect = rte_cpu_to_le_64(
2732 IAVF_TX_DESC_DTYPE_DESC_DONE << IAVF_TXD_QW1_DTYPE_SHIFT);
2733 if ((*status & mask) == expect)
2734 return RTE_ETH_TX_DESC_DONE;
2736 return RTE_ETH_TX_DESC_FULL;
2740 iavf_get_default_ptype_table(void)
2742 static const uint32_t ptype_tbl[IAVF_MAX_PKT_TYPE]
2743 __rte_cache_aligned = {
2746 [1] = RTE_PTYPE_L2_ETHER,
2747 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
2748 /* [3] - [5] reserved */
2749 [6] = RTE_PTYPE_L2_ETHER_LLDP,
2750 /* [7] - [10] reserved */
2751 [11] = RTE_PTYPE_L2_ETHER_ARP,
2752 /* [12] - [21] reserved */
2754 /* Non tunneled IPv4 */
2755 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2757 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2758 RTE_PTYPE_L4_NONFRAG,
2759 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2762 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2764 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2766 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2770 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2771 RTE_PTYPE_TUNNEL_IP |
2772 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2773 RTE_PTYPE_INNER_L4_FRAG,
2774 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2775 RTE_PTYPE_TUNNEL_IP |
2776 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2777 RTE_PTYPE_INNER_L4_NONFRAG,
2778 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2779 RTE_PTYPE_TUNNEL_IP |
2780 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2781 RTE_PTYPE_INNER_L4_UDP,
2783 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2784 RTE_PTYPE_TUNNEL_IP |
2785 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2786 RTE_PTYPE_INNER_L4_TCP,
2787 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2788 RTE_PTYPE_TUNNEL_IP |
2789 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2790 RTE_PTYPE_INNER_L4_SCTP,
2791 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2792 RTE_PTYPE_TUNNEL_IP |
2793 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2794 RTE_PTYPE_INNER_L4_ICMP,
2797 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2798 RTE_PTYPE_TUNNEL_IP |
2799 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2800 RTE_PTYPE_INNER_L4_FRAG,
2801 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2802 RTE_PTYPE_TUNNEL_IP |
2803 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2804 RTE_PTYPE_INNER_L4_NONFRAG,
2805 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2806 RTE_PTYPE_TUNNEL_IP |
2807 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2808 RTE_PTYPE_INNER_L4_UDP,
2810 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2811 RTE_PTYPE_TUNNEL_IP |
2812 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2813 RTE_PTYPE_INNER_L4_TCP,
2814 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2815 RTE_PTYPE_TUNNEL_IP |
2816 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2817 RTE_PTYPE_INNER_L4_SCTP,
2818 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2819 RTE_PTYPE_TUNNEL_IP |
2820 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2821 RTE_PTYPE_INNER_L4_ICMP,
2823 /* IPv4 --> GRE/Teredo/VXLAN */
2824 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2825 RTE_PTYPE_TUNNEL_GRENAT,
2827 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
2828 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2829 RTE_PTYPE_TUNNEL_GRENAT |
2830 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2831 RTE_PTYPE_INNER_L4_FRAG,
2832 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2833 RTE_PTYPE_TUNNEL_GRENAT |
2834 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2835 RTE_PTYPE_INNER_L4_NONFRAG,
2836 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2837 RTE_PTYPE_TUNNEL_GRENAT |
2838 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2839 RTE_PTYPE_INNER_L4_UDP,
2841 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2842 RTE_PTYPE_TUNNEL_GRENAT |
2843 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2844 RTE_PTYPE_INNER_L4_TCP,
2845 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2846 RTE_PTYPE_TUNNEL_GRENAT |
2847 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2848 RTE_PTYPE_INNER_L4_SCTP,
2849 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2850 RTE_PTYPE_TUNNEL_GRENAT |
2851 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2852 RTE_PTYPE_INNER_L4_ICMP,
2854 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
2855 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2856 RTE_PTYPE_TUNNEL_GRENAT |
2857 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2858 RTE_PTYPE_INNER_L4_FRAG,
2859 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2860 RTE_PTYPE_TUNNEL_GRENAT |
2861 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2862 RTE_PTYPE_INNER_L4_NONFRAG,
2863 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2864 RTE_PTYPE_TUNNEL_GRENAT |
2865 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2866 RTE_PTYPE_INNER_L4_UDP,
2868 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2869 RTE_PTYPE_TUNNEL_GRENAT |
2870 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2871 RTE_PTYPE_INNER_L4_TCP,
2872 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2873 RTE_PTYPE_TUNNEL_GRENAT |
2874 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2875 RTE_PTYPE_INNER_L4_SCTP,
2876 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2877 RTE_PTYPE_TUNNEL_GRENAT |
2878 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2879 RTE_PTYPE_INNER_L4_ICMP,
2881 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
2882 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2883 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2885 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2886 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2887 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2888 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2889 RTE_PTYPE_INNER_L4_FRAG,
2890 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2891 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2892 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2893 RTE_PTYPE_INNER_L4_NONFRAG,
2894 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2895 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2896 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2897 RTE_PTYPE_INNER_L4_UDP,
2899 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2900 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2901 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2902 RTE_PTYPE_INNER_L4_TCP,
2903 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2904 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2905 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2906 RTE_PTYPE_INNER_L4_SCTP,
2907 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2908 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2909 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2910 RTE_PTYPE_INNER_L4_ICMP,
2912 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2913 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2914 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2915 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2916 RTE_PTYPE_INNER_L4_FRAG,
2917 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2918 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2919 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2920 RTE_PTYPE_INNER_L4_NONFRAG,
2921 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2922 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2923 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2924 RTE_PTYPE_INNER_L4_UDP,
2926 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2927 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2928 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2929 RTE_PTYPE_INNER_L4_TCP,
2930 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2931 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2932 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2933 RTE_PTYPE_INNER_L4_SCTP,
2934 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2935 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2936 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2937 RTE_PTYPE_INNER_L4_ICMP,
2938 /* [73] - [87] reserved */
2940 /* Non tunneled IPv6 */
2941 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2943 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2944 RTE_PTYPE_L4_NONFRAG,
2945 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2948 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2950 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2952 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2956 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2957 RTE_PTYPE_TUNNEL_IP |
2958 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2959 RTE_PTYPE_INNER_L4_FRAG,
2960 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2961 RTE_PTYPE_TUNNEL_IP |
2962 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2963 RTE_PTYPE_INNER_L4_NONFRAG,
2964 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2965 RTE_PTYPE_TUNNEL_IP |
2966 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2967 RTE_PTYPE_INNER_L4_UDP,
2969 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2970 RTE_PTYPE_TUNNEL_IP |
2971 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2972 RTE_PTYPE_INNER_L4_TCP,
2973 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2974 RTE_PTYPE_TUNNEL_IP |
2975 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2976 RTE_PTYPE_INNER_L4_SCTP,
2977 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2978 RTE_PTYPE_TUNNEL_IP |
2979 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2980 RTE_PTYPE_INNER_L4_ICMP,
2983 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2984 RTE_PTYPE_TUNNEL_IP |
2985 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2986 RTE_PTYPE_INNER_L4_FRAG,
2987 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2988 RTE_PTYPE_TUNNEL_IP |
2989 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2990 RTE_PTYPE_INNER_L4_NONFRAG,
2991 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2992 RTE_PTYPE_TUNNEL_IP |
2993 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2994 RTE_PTYPE_INNER_L4_UDP,
2995 /* [105] reserved */
2996 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2997 RTE_PTYPE_TUNNEL_IP |
2998 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2999 RTE_PTYPE_INNER_L4_TCP,
3000 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3001 RTE_PTYPE_TUNNEL_IP |
3002 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3003 RTE_PTYPE_INNER_L4_SCTP,
3004 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3005 RTE_PTYPE_TUNNEL_IP |
3006 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3007 RTE_PTYPE_INNER_L4_ICMP,
3009 /* IPv6 --> GRE/Teredo/VXLAN */
3010 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3011 RTE_PTYPE_TUNNEL_GRENAT,
3013 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3014 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3015 RTE_PTYPE_TUNNEL_GRENAT |
3016 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3017 RTE_PTYPE_INNER_L4_FRAG,
3018 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3019 RTE_PTYPE_TUNNEL_GRENAT |
3020 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3021 RTE_PTYPE_INNER_L4_NONFRAG,
3022 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3023 RTE_PTYPE_TUNNEL_GRENAT |
3024 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3025 RTE_PTYPE_INNER_L4_UDP,
3026 /* [113] reserved */
3027 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3028 RTE_PTYPE_TUNNEL_GRENAT |
3029 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3030 RTE_PTYPE_INNER_L4_TCP,
3031 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3032 RTE_PTYPE_TUNNEL_GRENAT |
3033 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3034 RTE_PTYPE_INNER_L4_SCTP,
3035 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3036 RTE_PTYPE_TUNNEL_GRENAT |
3037 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3038 RTE_PTYPE_INNER_L4_ICMP,
3040 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3041 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3042 RTE_PTYPE_TUNNEL_GRENAT |
3043 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3044 RTE_PTYPE_INNER_L4_FRAG,
3045 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3046 RTE_PTYPE_TUNNEL_GRENAT |
3047 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3048 RTE_PTYPE_INNER_L4_NONFRAG,
3049 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3050 RTE_PTYPE_TUNNEL_GRENAT |
3051 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3052 RTE_PTYPE_INNER_L4_UDP,
3053 /* [120] reserved */
3054 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3055 RTE_PTYPE_TUNNEL_GRENAT |
3056 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3057 RTE_PTYPE_INNER_L4_TCP,
3058 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3059 RTE_PTYPE_TUNNEL_GRENAT |
3060 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3061 RTE_PTYPE_INNER_L4_SCTP,
3062 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3063 RTE_PTYPE_TUNNEL_GRENAT |
3064 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3065 RTE_PTYPE_INNER_L4_ICMP,
3067 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3068 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3069 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3071 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3072 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3073 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3074 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3075 RTE_PTYPE_INNER_L4_FRAG,
3076 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3077 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3078 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3079 RTE_PTYPE_INNER_L4_NONFRAG,
3080 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3081 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3082 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3083 RTE_PTYPE_INNER_L4_UDP,
3084 /* [128] reserved */
3085 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3086 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3087 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3088 RTE_PTYPE_INNER_L4_TCP,
3089 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3090 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3091 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3092 RTE_PTYPE_INNER_L4_SCTP,
3093 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3094 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3095 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3096 RTE_PTYPE_INNER_L4_ICMP,
3098 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3099 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3100 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3101 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3102 RTE_PTYPE_INNER_L4_FRAG,
3103 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3104 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3105 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3106 RTE_PTYPE_INNER_L4_NONFRAG,
3107 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3108 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3109 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3110 RTE_PTYPE_INNER_L4_UDP,
3111 /* [135] reserved */
3112 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3113 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3114 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3115 RTE_PTYPE_INNER_L4_TCP,
3116 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3117 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3118 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3119 RTE_PTYPE_INNER_L4_SCTP,
3120 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3121 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3122 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3123 RTE_PTYPE_INNER_L4_ICMP,
3124 /* [139] - [299] reserved */
3127 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3128 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3130 /* PPPoE --> IPv4 */
3131 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3132 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3134 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3135 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3136 RTE_PTYPE_L4_NONFRAG,
3137 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3138 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3140 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3141 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3143 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3144 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3146 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3147 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3150 /* PPPoE --> IPv6 */
3151 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3152 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3154 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3155 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3156 RTE_PTYPE_L4_NONFRAG,
3157 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3158 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3160 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3161 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3163 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3164 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3166 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3167 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3169 /* [314] - [324] reserved */
3171 /* IPv4/IPv6 --> GTPC/GTPU */
3172 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3173 RTE_PTYPE_TUNNEL_GTPC,
3174 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3175 RTE_PTYPE_TUNNEL_GTPC,
3176 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3177 RTE_PTYPE_TUNNEL_GTPC,
3178 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3179 RTE_PTYPE_TUNNEL_GTPC,
3180 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3181 RTE_PTYPE_TUNNEL_GTPU,
3182 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3183 RTE_PTYPE_TUNNEL_GTPU,
3185 /* IPv4 --> GTPU --> IPv4 */
3186 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3187 RTE_PTYPE_TUNNEL_GTPU |
3188 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3189 RTE_PTYPE_INNER_L4_FRAG,
3190 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3191 RTE_PTYPE_TUNNEL_GTPU |
3192 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3193 RTE_PTYPE_INNER_L4_NONFRAG,
3194 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3195 RTE_PTYPE_TUNNEL_GTPU |
3196 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3197 RTE_PTYPE_INNER_L4_UDP,
3198 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3199 RTE_PTYPE_TUNNEL_GTPU |
3200 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3201 RTE_PTYPE_INNER_L4_TCP,
3202 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3203 RTE_PTYPE_TUNNEL_GTPU |
3204 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3205 RTE_PTYPE_INNER_L4_ICMP,
3207 /* IPv6 --> GTPU --> IPv4 */
3208 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3209 RTE_PTYPE_TUNNEL_GTPU |
3210 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3211 RTE_PTYPE_INNER_L4_FRAG,
3212 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3213 RTE_PTYPE_TUNNEL_GTPU |
3214 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3215 RTE_PTYPE_INNER_L4_NONFRAG,
3216 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3217 RTE_PTYPE_TUNNEL_GTPU |
3218 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3219 RTE_PTYPE_INNER_L4_UDP,
3220 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3221 RTE_PTYPE_TUNNEL_GTPU |
3222 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3223 RTE_PTYPE_INNER_L4_TCP,
3224 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3225 RTE_PTYPE_TUNNEL_GTPU |
3226 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3227 RTE_PTYPE_INNER_L4_ICMP,
3229 /* IPv4 --> GTPU --> IPv6 */
3230 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3231 RTE_PTYPE_TUNNEL_GTPU |
3232 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3233 RTE_PTYPE_INNER_L4_FRAG,
3234 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3235 RTE_PTYPE_TUNNEL_GTPU |
3236 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3237 RTE_PTYPE_INNER_L4_NONFRAG,
3238 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3239 RTE_PTYPE_TUNNEL_GTPU |
3240 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3241 RTE_PTYPE_INNER_L4_UDP,
3242 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3243 RTE_PTYPE_TUNNEL_GTPU |
3244 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3245 RTE_PTYPE_INNER_L4_TCP,
3246 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3247 RTE_PTYPE_TUNNEL_GTPU |
3248 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3249 RTE_PTYPE_INNER_L4_ICMP,
3251 /* IPv6 --> GTPU --> IPv6 */
3252 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3253 RTE_PTYPE_TUNNEL_GTPU |
3254 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3255 RTE_PTYPE_INNER_L4_FRAG,
3256 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3257 RTE_PTYPE_TUNNEL_GTPU |
3258 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3259 RTE_PTYPE_INNER_L4_NONFRAG,
3260 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3261 RTE_PTYPE_TUNNEL_GTPU |
3262 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3263 RTE_PTYPE_INNER_L4_UDP,
3264 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3265 RTE_PTYPE_TUNNEL_GTPU |
3266 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3267 RTE_PTYPE_INNER_L4_TCP,
3268 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3269 RTE_PTYPE_TUNNEL_GTPU |
3270 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3271 RTE_PTYPE_INNER_L4_ICMP,
3273 /* IPv4 --> UDP ECPRI */
3274 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3276 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3278 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3280 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3282 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3284 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3286 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3288 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3290 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3292 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3295 /* IPV6 --> UDP ECPRI */
3296 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3298 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3300 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3302 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3304 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3306 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3308 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3310 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3312 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3314 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3316 /* All others reserved */