1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
8 #include <rte_kvargs.h>
10 #include <rte_ethdev_driver.h>
12 #include "base/ice_common.h"
13 #include "base/ice_adminq_cmd.h"
15 #define ICE_VLAN_TAG_SIZE 4
17 #define ICE_ADMINQ_LEN 32
18 #define ICE_SBIOQ_LEN 32
19 #define ICE_MAILBOXQ_LEN 32
20 #define ICE_ADMINQ_BUF_SZ 4096
21 #define ICE_SBIOQ_BUF_SZ 4096
22 #define ICE_MAILBOXQ_BUF_SZ 4096
23 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
24 #define ICE_MAX_Q_PER_TC 64
25 #define ICE_NUM_DESC_DEFAULT 512
26 #define ICE_BUF_SIZE_MIN 1024
27 #define ICE_FRAME_SIZE_MAX 9728
28 #define ICE_QUEUE_BASE_ADDR_UNIT 128
29 /* number of VSIs and queue default setting */
30 #define ICE_MAX_QP_NUM_PER_VF 16
31 #define ICE_DEFAULT_QP_NUM_FDIR 1
32 #define ICE_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
33 #define ICE_VFTA_SIZE (4096 / ICE_UINT32_BIT_SIZE)
34 /* Maximun number of MAC addresses */
35 #define ICE_NUM_MACADDR_MAX 64
36 /* Maximum number of VFs */
37 #define ICE_MAX_VF 128
38 #define ICE_MAX_INTR_QUEUE_NUM 256
40 #define ICE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
41 #define ICE_RX_VEC_ID RTE_INTR_VEC_RXTX_OFFSET
43 #define ICE_MAX_PKT_TYPE 1024
45 /* DDP package search path */
46 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
47 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
48 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
49 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
50 #define ICE_MAX_PKG_FILENAME_SIZE 256
52 #define MAX_ACL_ENTRIES 512
55 * vlan_id is a 12 bit number.
56 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
57 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
58 * The higher 7 bit val specifies VFTA array index.
60 #define ICE_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
61 #define ICE_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
63 /* Default TC traffic in case DCB is not enabled */
64 #define ICE_DEFAULT_TCMAP 0x1
65 #define ICE_FDIR_QUEUE_ID 0
67 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
68 #define ICE_VMDQ_POOL_BASE 1
70 #define ICE_DEFAULT_RX_FREE_THRESH 32
71 #define ICE_DEFAULT_RX_PTHRESH 8
72 #define ICE_DEFAULT_RX_HTHRESH 8
73 #define ICE_DEFAULT_RX_WTHRESH 0
75 #define ICE_DEFAULT_TX_FREE_THRESH 32
76 #define ICE_DEFAULT_TX_PTHRESH 32
77 #define ICE_DEFAULT_TX_HTHRESH 0
78 #define ICE_DEFAULT_TX_WTHRESH 0
79 #define ICE_DEFAULT_TX_RSBIT_THRESH 32
81 /* Bit shift and mask */
82 #define ICE_4_BIT_WIDTH (CHAR_BIT / 2)
83 #define ICE_4_BIT_MASK RTE_LEN2MASK(ICE_4_BIT_WIDTH, uint8_t)
84 #define ICE_8_BIT_WIDTH CHAR_BIT
85 #define ICE_8_BIT_MASK UINT8_MAX
86 #define ICE_16_BIT_WIDTH (CHAR_BIT * 2)
87 #define ICE_16_BIT_MASK UINT16_MAX
88 #define ICE_32_BIT_WIDTH (CHAR_BIT * 4)
89 #define ICE_32_BIT_MASK UINT32_MAX
90 #define ICE_40_BIT_WIDTH (CHAR_BIT * 5)
91 #define ICE_40_BIT_MASK RTE_LEN2MASK(ICE_40_BIT_WIDTH, uint64_t)
92 #define ICE_48_BIT_WIDTH (CHAR_BIT * 6)
93 #define ICE_48_BIT_MASK RTE_LEN2MASK(ICE_48_BIT_WIDTH, uint64_t)
95 #define ICE_FLAG_RSS BIT_ULL(0)
96 #define ICE_FLAG_DCB BIT_ULL(1)
97 #define ICE_FLAG_VMDQ BIT_ULL(2)
98 #define ICE_FLAG_SRIOV BIT_ULL(3)
99 #define ICE_FLAG_HEADER_SPLIT_DISABLED BIT_ULL(4)
100 #define ICE_FLAG_HEADER_SPLIT_ENABLED BIT_ULL(5)
101 #define ICE_FLAG_FDIR BIT_ULL(6)
102 #define ICE_FLAG_VXLAN BIT_ULL(7)
103 #define ICE_FLAG_RSS_AQ_CAPABLE BIT_ULL(8)
104 #define ICE_FLAG_VF_MAC_BY_PF BIT_ULL(9)
105 #define ICE_FLAG_ALL (ICE_FLAG_RSS | \
109 ICE_FLAG_HEADER_SPLIT_DISABLED | \
110 ICE_FLAG_HEADER_SPLIT_ENABLED | \
113 ICE_FLAG_RSS_AQ_CAPABLE | \
114 ICE_FLAG_VF_MAC_BY_PF)
116 #define ICE_RSS_OFFLOAD_ALL ( \
118 ETH_RSS_FRAG_IPV4 | \
119 ETH_RSS_NONFRAG_IPV4_TCP | \
120 ETH_RSS_NONFRAG_IPV4_UDP | \
121 ETH_RSS_NONFRAG_IPV4_SCTP | \
122 ETH_RSS_NONFRAG_IPV4_OTHER | \
124 ETH_RSS_FRAG_IPV6 | \
125 ETH_RSS_NONFRAG_IPV6_TCP | \
126 ETH_RSS_NONFRAG_IPV6_UDP | \
127 ETH_RSS_NONFRAG_IPV6_SCTP | \
128 ETH_RSS_NONFRAG_IPV6_OTHER | \
132 * The overhead from MTU to max frame size.
133 * Considering QinQ packet, the VLAN tag needs to be counted twice.
135 #define ICE_ETH_OVERHEAD \
136 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE * 2)
138 #define ICE_RXTX_BYTES_HIGH(bytes) ((bytes) & ~ICE_40_BIT_MASK)
139 #define ICE_RXTX_BYTES_LOW(bytes) ((bytes) & ICE_40_BIT_MASK)
141 /* Max number of flexible descriptor rxdid */
142 #define ICE_FLEX_DESC_RXDID_MAX_NUM 64
144 /* DDP package type */
146 ICE_PKG_TYPE_UNKNOWN,
147 ICE_PKG_TYPE_OS_DEFAULT,
154 * MAC filter structure
156 struct ice_mac_filter_info {
157 struct rte_ether_addr mac_addr;
160 TAILQ_HEAD(ice_mac_filter_list, ice_mac_filter);
162 /* MAC filter list structure */
163 struct ice_mac_filter {
164 TAILQ_ENTRY(ice_mac_filter) next;
165 struct ice_mac_filter_info mac_info;
169 * VLAN filter structure
171 struct ice_vlan_filter_info {
175 TAILQ_HEAD(ice_vlan_filter_list, ice_vlan_filter);
177 /* VLAN filter list structure */
178 struct ice_vlan_filter {
179 TAILQ_ENTRY(ice_vlan_filter) next;
180 struct ice_vlan_filter_info vlan_info;
184 LIST_ENTRY(pool_entry) next;
189 LIST_HEAD(res_list, pool_entry);
191 struct ice_res_pool_info {
192 uint32_t base; /* Resource start index */
193 uint32_t num_alloc; /* Allocated resource number */
194 uint32_t num_free; /* Total available resource number */
195 struct res_list alloc_list; /* Allocated resource list */
196 struct res_list free_list; /* Available resource list */
199 TAILQ_HEAD(ice_vsi_list_head, ice_vsi_list);
203 /* VSI list structure */
204 struct ice_vsi_list {
205 TAILQ_ENTRY(ice_vsi_list) list;
213 * Structure that defines a VSI, associated with a adapter.
216 struct ice_adapter *adapter; /* Backreference to associated adapter */
217 struct ice_aqc_vsi_props info; /* VSI properties */
219 * When drivers loaded, only a default main VSI exists. In case new VSI
220 * needs to add, HW needs to know the layout that VSIs are organized.
221 * Besides that, VSI isan element and can't switch packets, which needs
222 * to add new component VEB to perform switching. So, a new VSI needs
223 * to specify the the uplink VSI (Parent VSI) before created. The
224 * uplink VSI will check whether it had a VEB to switch packets. If no,
225 * it will try to create one. Then, uplink VSI will move the new VSI
226 * into its' sib_vsi_list to manage all the downlink VSI.
227 * sib_vsi_list: the VSI list that shared the same uplink VSI.
228 * parent_vsi : the uplink VSI. It's NULL for main VSI.
229 * veb : the VEB associates with the VSI.
231 struct ice_vsi_list sib_vsi_list; /* sibling vsi list */
232 struct ice_vsi *parent_vsi;
233 enum ice_vsi_type type; /* VSI types */
234 uint16_t vlan_num; /* Total VLAN number */
235 uint16_t mac_num; /* Total mac number */
236 struct ice_mac_filter_list mac_list; /* macvlan filter list */
237 struct ice_vlan_filter_list vlan_list; /* vlan filter list */
238 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
239 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
240 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
241 uint16_t base_queue; /* The first queue index of this VSI */
242 uint16_t vsi_id; /* Hardware Id */
243 uint16_t idx; /* vsi_handle: SW index in hw->vsi_ctx */
244 /* VF number to which the VSI connects, valid when VSI is VF type */
246 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
247 uint16_t nb_msix; /* The max number of msix vector */
248 uint8_t enabled_tc; /* The traffic class enabled */
249 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
250 uint8_t vlan_filter_on; /* The VLAN filter enabled */
251 /* information about rss configuration */
256 struct ice_eth_stats eth_stats_offset;
257 struct ice_eth_stats eth_stats;
259 uint64_t old_rx_bytes;
260 uint64_t old_tx_bytes;
263 enum proto_xtr_type {
271 PROTO_XTR_MAX /* The last one */
274 enum ice_fdir_tunnel_type {
275 ICE_FDIR_TUNNEL_TYPE_NONE = 0,
276 ICE_FDIR_TUNNEL_TYPE_VXLAN,
277 ICE_FDIR_TUNNEL_TYPE_GTPU,
278 ICE_FDIR_TUNNEL_TYPE_GTPU_EH,
282 TAILQ_HEAD(ice_flow_list, rte_flow);
284 struct ice_flow_parser_node;
285 TAILQ_HEAD(ice_parser_list, ice_flow_parser_node);
287 struct ice_fdir_filter_conf {
288 struct ice_fdir_fltr input;
289 enum ice_fdir_tunnel_type tunnel_type;
291 struct ice_fdir_counter *counter; /* flow specific counter context */
292 struct rte_flow_action_count act_count;
295 uint64_t outer_input_set; /* only for tunnel packets outer fields */
299 #define ICE_MAX_FDIR_FILTER_NUM (1024 * 16)
301 struct ice_fdir_fltr_pattern {
302 enum ice_fltr_ptype flow_type;
305 struct ice_fdir_v4 v4;
306 struct ice_fdir_v6 v6;
309 struct ice_fdir_udp_gtp gtpu_data;
310 struct ice_fdir_udp_gtp gtpu_mask;
312 struct ice_fdir_extra ext_data;
313 struct ice_fdir_extra ext_mask;
315 enum ice_fdir_tunnel_type tunnel_type;
318 #define ICE_FDIR_COUNTER_DEFAULT_POOL_SIZE 1
319 #define ICE_FDIR_COUNTER_MAX_POOL_SIZE 32
320 #define ICE_FDIR_COUNTERS_PER_BLOCK 256
321 #define ICE_FDIR_COUNTER_INDEX(base_idx) \
322 ((base_idx) * ICE_FDIR_COUNTERS_PER_BLOCK)
323 struct ice_fdir_counter_pool;
325 struct ice_fdir_counter {
326 TAILQ_ENTRY(ice_fdir_counter) next;
327 struct ice_fdir_counter_pool *pool;
336 TAILQ_HEAD(ice_fdir_counter_list, ice_fdir_counter);
338 struct ice_fdir_counter_pool {
339 TAILQ_ENTRY(ice_fdir_counter_pool) next;
340 struct ice_fdir_counter_list counter_list;
341 struct ice_fdir_counter counters[0];
344 TAILQ_HEAD(ice_fdir_counter_pool_list, ice_fdir_counter_pool);
346 struct ice_fdir_counter_pool_container {
347 struct ice_fdir_counter_pool_list pool_list;
348 struct ice_fdir_counter_pool *pools[ICE_FDIR_COUNTER_MAX_POOL_SIZE];
353 * A structure used to define fields of a FDIR related info.
355 struct ice_fdir_info {
356 struct ice_vsi *fdir_vsi; /* pointer to fdir VSI structure */
357 struct ice_tx_queue *txq;
358 struct ice_rx_queue *rxq;
359 void *prg_pkt; /* memory for fdir program packet */
360 uint64_t dma_addr; /* physic address of packet memory*/
361 const struct rte_memzone *mz;
362 struct ice_fdir_filter_conf conf;
364 struct ice_fdir_filter_conf **hash_map;
365 struct rte_hash *hash_table;
367 struct ice_fdir_counter_pool_container counter;
370 #define ICE_HASH_GTPU_CTX_EH_IP 0
371 #define ICE_HASH_GTPU_CTX_EH_IP_UDP 1
372 #define ICE_HASH_GTPU_CTX_EH_IP_TCP 2
373 #define ICE_HASH_GTPU_CTX_UP_IP 3
374 #define ICE_HASH_GTPU_CTX_UP_IP_UDP 4
375 #define ICE_HASH_GTPU_CTX_UP_IP_TCP 5
376 #define ICE_HASH_GTPU_CTX_DW_IP 6
377 #define ICE_HASH_GTPU_CTX_DW_IP_UDP 7
378 #define ICE_HASH_GTPU_CTX_DW_IP_TCP 8
379 #define ICE_HASH_GTPU_CTX_MAX 9
381 enum ice_rss_hash_func {
382 ICE_RSS_HASH_TOEPLITZ = 0,
383 ICE_RSS_HASH_TOEPLITZ_SYMMETRIC = 1,
384 ICE_RSS_HASH_XOR = 2,
385 ICE_RSS_HASH_JHASH = 3,
388 struct ice_rss_hash_cfg {
391 enum ice_rss_hash_func hash_func;
394 struct ice_hash_gtpu_ctx {
395 struct ice_rss_hash_cfg ctx[ICE_HASH_GTPU_CTX_MAX];
398 struct ice_hash_ctx {
399 struct ice_hash_gtpu_ctx gtpu4;
400 struct ice_hash_gtpu_ctx gtpu6;
403 struct ice_acl_conf {
404 struct ice_fdir_fltr input;
409 * A structure used to define fields of ACL related info.
411 struct ice_acl_info {
412 struct ice_acl_conf conf;
413 struct rte_bitmap *slots;
414 uint64_t hw_entry_id[MAX_ACL_ENTRIES];
418 struct ice_adapter *adapter; /* The adapter this PF associate to */
419 struct ice_vsi *main_vsi; /* pointer to main VSI structure */
420 /* Used for next free software vsi idx.
421 * To save the effort, we don't recycle the index.
422 * Suppose the indexes are more than enough.
424 uint16_t next_vsi_idx;
425 uint16_t vsis_allocated;
426 uint16_t vsis_unallocated;
427 struct ice_res_pool_info qp_pool; /*Queue pair pool */
428 struct ice_res_pool_info msix_pool; /* MSIX interrupt pool */
429 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
430 struct rte_ether_addr dev_addr; /* PF device mac address */
431 uint64_t flags; /* PF feature flags */
432 uint16_t hash_lut_size; /* The size of hash lookup table */
433 uint16_t lan_nb_qp_max;
434 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
435 uint16_t base_queue; /* The base queue pairs index in the device */
436 uint8_t *proto_xtr; /* Protocol extraction type for all queues */
437 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
438 uint16_t fdir_qp_offset;
439 struct ice_fdir_info fdir; /* flow director info */
440 struct ice_acl_info acl; /* ACL info */
441 struct ice_hash_ctx hash_ctx;
442 uint16_t hw_prof_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX];
443 uint16_t fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX];
444 struct ice_hw_port_stats stats_offset;
445 struct ice_hw_port_stats stats;
446 /* internal packet statistics, it should be excluded from the total */
447 struct ice_eth_stats internal_stats_offset;
448 struct ice_eth_stats internal_stats;
450 bool adapter_stopped;
451 struct ice_flow_list flow_list;
452 rte_spinlock_t flow_ops_lock;
453 struct ice_parser_list rss_parser_list;
454 struct ice_parser_list perm_parser_list;
455 struct ice_parser_list dist_parser_list;
457 uint64_t old_rx_bytes;
458 uint64_t old_tx_bytes;
459 uint64_t supported_rxdid; /* bitmap for supported RXDID */
462 #define ICE_MAX_QUEUE_NUM 2048
465 * Cache devargs parse result.
468 int safe_mode_support;
469 uint8_t proto_xtr_dflt;
470 int pipe_mode_support;
471 uint8_t proto_xtr[ICE_MAX_QUEUE_NUM];
475 * Structure to store private data for each PF/VF instance.
478 /* Common for both PF and VF */
480 struct rte_eth_dev *eth_dev;
482 bool rx_bulk_alloc_allowed;
485 bool tx_simple_allowed;
486 /* ptype mapping table */
487 uint32_t ptype_tbl[ICE_MAX_PKT_TYPE] __rte_cache_min_aligned;
489 struct ice_devargs devargs;
490 enum ice_pkg_type active_pkg_type; /* loaded ddp package type */
491 uint16_t fdir_ref_cnt;
494 struct ice_vsi_vlan_pvid_info {
495 uint16_t on; /* Enable or disable pvid */
497 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
499 /* Valid in case 'on' is cleared. 'tagged' will reject
500 * tagged packets, while 'untagged' will reject
509 #define ICE_DEV_TO_PCI(eth_dev) \
510 RTE_DEV_TO_PCI((eth_dev)->device)
512 /* ICE_DEV_PRIVATE_TO */
513 #define ICE_DEV_PRIVATE_TO_PF(adapter) \
514 (&((struct ice_adapter *)adapter)->pf)
515 #define ICE_DEV_PRIVATE_TO_HW(adapter) \
516 (&((struct ice_adapter *)adapter)->hw)
517 #define ICE_DEV_PRIVATE_TO_ADAPTER(adapter) \
518 ((struct ice_adapter *)adapter)
521 #define ICE_VSI_TO_HW(vsi) \
522 (&(((struct ice_vsi *)vsi)->adapter->hw))
523 #define ICE_VSI_TO_PF(vsi) \
524 (&(((struct ice_vsi *)vsi)->adapter->pf))
525 #define ICE_VSI_TO_ETH_DEV(vsi) \
526 (((struct ice_vsi *)vsi)->adapter->eth_dev)
529 #define ICE_PF_TO_HW(pf) \
530 (&(((struct ice_pf *)pf)->adapter->hw))
531 #define ICE_PF_TO_ADAPTER(pf) \
532 ((struct ice_adapter *)(pf)->adapter)
533 #define ICE_PF_TO_ETH_DEV(pf) \
534 (((struct ice_pf *)pf)->adapter->eth_dev)
536 enum ice_pkg_type ice_load_pkg_type(struct ice_hw *hw);
538 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type);
540 ice_release_vsi(struct ice_vsi *vsi);
541 void ice_vsi_enable_queues_intr(struct ice_vsi *vsi);
542 void ice_vsi_disable_queues_intr(struct ice_vsi *vsi);
543 void ice_vsi_queues_bind_intr(struct ice_vsi *vsi);
544 int ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
545 uint64_t hash_fld, uint32_t pkt_hdr, bool symm);
546 int ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
547 uint64_t hash_fld, uint32_t pkt_hdr);
550 ice_align_floor(int n)
554 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
557 #define ICE_PHY_TYPE_SUPPORT_50G(phy_type) \
558 (((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CR2) || \
559 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR2) || \
560 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR2) || \
561 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR2) || \
562 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC) || \
563 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2) || \
564 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC) || \
565 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2) || \
566 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CP) || \
567 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR) || \
568 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_FR) || \
569 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR) || \
570 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4) || \
571 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC) || \
572 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1))
574 #define ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type) \
575 (((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR4) || \
576 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR4) || \
577 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_LR4) || \
578 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR4) || \
579 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC) || \
580 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4) || \
581 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC) || \
582 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4) || \
583 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4) || \
584 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4) || \
585 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CP2) || \
586 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR2) || \
587 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_DR))
589 #define ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type) \
590 (((phy_type) & ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4) || \
591 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC) || \
592 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2) || \
593 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC) || \
594 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2))
596 #endif /* _ICE_ETHDEV_H_ */