1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
5 #ifndef _ICE_ADMINQ_CMD_H_
6 #define _ICE_ADMINQ_CMD_H_
8 /* This header file defines the Admin Queue commands, error codes and
9 * descriptor format. It is shared between Firmware and Software.
12 #define ICE_MAX_VSI 768
13 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
14 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
16 struct ice_aqc_generic {
23 /* Get version (direct 0x0001) */
24 struct ice_aqc_get_ver {
37 /* Send driver version (indirect 0x0002) */
38 struct ice_aqc_driver_ver {
48 /* Queue Shutdown (direct 0x0003) */
49 struct ice_aqc_q_shutdown {
51 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
55 /* Request resource ownership (direct 0x0008)
56 * Release resource ownership (direct 0x0009)
58 struct ice_aqc_req_res {
60 #define ICE_AQC_RES_ID_NVM 1
61 #define ICE_AQC_RES_ID_SDP 2
62 #define ICE_AQC_RES_ID_CHNG_LOCK 3
63 #define ICE_AQC_RES_ID_GLBL_LOCK 4
65 #define ICE_AQC_RES_ACCESS_READ 1
66 #define ICE_AQC_RES_ACCESS_WRITE 2
68 /* Upon successful completion, FW writes this value and driver is
69 * expected to release resource before timeout. This value is provided
73 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
74 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
75 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
76 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
77 /* For SDP: pin ID of the SDP */
79 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
81 #define ICE_AQ_RES_GLBL_SUCCESS 0
82 #define ICE_AQ_RES_GLBL_IN_PROG 1
83 #define ICE_AQ_RES_GLBL_DONE 2
87 /* Get function capabilities (indirect 0x000A)
88 * Get device capabilities (indirect 0x000B)
90 struct ice_aqc_list_caps {
99 /* Device/Function buffer entry, repeated per reported capability */
100 struct ice_aqc_list_caps_elem {
102 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
103 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8
104 #define ICE_AQC_CAPS_VSI 0x0017
105 #define ICE_AQC_CAPS_DCB 0x0018
106 #define ICE_AQC_CAPS_RSS 0x0040
107 #define ICE_AQC_CAPS_RXQS 0x0041
108 #define ICE_AQC_CAPS_TXQS 0x0042
109 #define ICE_AQC_CAPS_MSIX 0x0043
110 #define ICE_AQC_CAPS_FD 0x0045
111 #define ICE_AQC_CAPS_MAX_MTU 0x0047
115 /* Number of resources described by this capability */
117 /* Only meaningful for some types of resources */
119 /* Only meaningful for some types of resources */
125 /* Manage MAC address, read command - indirect (0x0107)
126 * This struct is also used for the response
128 struct ice_aqc_manage_mac_read {
129 __le16 flags; /* Zeroed by device driver */
130 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
131 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
132 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
133 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
134 #define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8)
135 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9)
136 #define ICE_AQC_MAN_MAC_READ_S 4
137 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
139 u8 num_addr; /* Used in response */
145 /* Response buffer format for manage MAC read command */
146 struct ice_aqc_manage_mac_read_resp {
149 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
150 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1
151 u8 mac_addr[ETH_ALEN];
154 /* Manage MAC address, write command - direct (0x0108) */
155 struct ice_aqc_manage_mac_write {
158 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
159 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
160 #define ICE_AQC_MAN_MAC_WR_S 6
161 #define ICE_AQC_MAN_MAC_WR_M (3 << ICE_AQC_MAN_MAC_WR_S)
162 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0
163 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL (BIT(0) << ICE_AQC_MAN_MAC_WR_S)
164 /* High 16 bits of MAC address in big endian order */
166 /* Low 32 bits of MAC address in big endian order */
172 /* Clear PXE Command and response (direct 0x0110) */
173 struct ice_aqc_clear_pxe {
175 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
179 /* Configure No-Drop Policy Command (direct 0x0112) */
180 struct ice_aqc_config_no_drop_policy {
182 #define ICE_AQC_FORCE_NO_DROP BIT(0)
186 /* Get switch configuration (0x0200) */
187 struct ice_aqc_get_sw_cfg {
188 /* Reserved for command and copy of request flags for response */
190 /* First desc in case of command and next_elem in case of response
191 * In case of response, if it is not zero, means all the configuration
192 * was not returned and new command shall be sent with this value in
193 * the 'first desc' field
196 /* Reserved for command, only used for response */
203 /* Each entry in the response buffer is of the following type: */
204 struct ice_aqc_get_sw_cfg_resp_elem {
205 /* VSI/Port Number */
207 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
208 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \
209 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
210 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14
211 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
212 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
213 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1
214 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2
216 /* SWID VSI/Port belongs to */
219 /* Bit 14..0 : PF/VF number VSI belongs to
220 * Bit 15 : VF indication bit
223 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
224 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \
225 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
226 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
229 /* The response buffer is as follows. Note that the length of the
230 * elements array varies with the length of the command response.
232 struct ice_aqc_get_sw_cfg_resp {
233 struct ice_aqc_get_sw_cfg_resp_elem elements[1];
236 /* These resource type defines are used for all switch resource
237 * commands where a resource type is required, such as:
238 * Get Resource Allocation command (indirect 0x0204)
239 * Allocate Resources command (indirect 0x0208)
240 * Free Resources command (indirect 0x0209)
241 * Get Allocated Resource Descriptors Command (indirect 0x020A)
243 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00
244 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01
245 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02
246 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
247 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
248 #define ICE_AQC_RES_TYPE_RECIPE 0x05
249 #define ICE_AQC_RES_TYPE_PROFILE 0x06
250 #define ICE_AQC_RES_TYPE_SWID 0x07
251 #define ICE_AQC_RES_TYPE_VSI 0x08
252 #define ICE_AQC_RES_TYPE_FLU 0x09
253 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A
254 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B
255 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C
256 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20
257 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21
258 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22
259 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23
260 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30
261 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48
262 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49
263 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50
264 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51
265 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58
266 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59
267 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
268 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
269 /* Resource types 0x62-67 are reserved for Hash profile builder */
270 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68
271 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69
273 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7)
274 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
275 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
277 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
279 #define ICE_AQC_RES_TYPE_S 0
280 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S)
282 /* Get Resource Allocation command (indirect 0x0204) */
283 struct ice_aqc_get_res_alloc {
284 __le16 resp_elem_num; /* Used in response, reserved in command */
290 /* Get Resource Allocation Response Buffer per response */
291 struct ice_aqc_get_res_resp_elem {
292 __le16 res_type; /* Types defined above cmd 0x0204 */
293 __le16 total_capacity; /* Resources available to all PF's */
294 __le16 total_function; /* Resources allocated for a PF */
295 __le16 total_shared; /* Resources allocated as shared */
296 __le16 total_free; /* Resources un-allocated/not reserved by any PF */
299 /* Buffer for Get Resource command */
300 struct ice_aqc_get_res_resp {
301 /* Number of resource entries to be calculated using
302 * datalen/sizeof(struct ice_aqc_cmd_resp)).
303 * Value of 'datalen' gets updated as part of response.
305 struct ice_aqc_get_res_resp_elem elem[1];
308 /* Allocate Resources command (indirect 0x0208)
309 * Free Resources command (indirect 0x0209)
311 struct ice_aqc_alloc_free_res_cmd {
312 __le16 num_entries; /* Number of Resource entries */
318 /* Resource descriptor */
319 struct ice_aqc_res_elem {
326 /* Buffer for Allocate/Free Resources commands */
327 struct ice_aqc_alloc_free_res_elem {
328 __le16 res_type; /* Types defined above cmd 0x0204 */
329 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8
330 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
331 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
333 struct ice_aqc_res_elem elem[1];
336 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */
337 struct ice_aqc_get_allocd_res_desc {
340 __le16 res; /* Types defined above cmd 0x0204 */
355 struct ice_aqc_get_allocd_res_desc_resp {
356 struct ice_aqc_res_elem elem[1];
359 /* Add VSI (indirect 0x0210)
360 * Update VSI (indirect 0x0211)
361 * Get VSI (indirect 0x0212)
362 * Free VSI (indirect 0x0213)
364 struct ice_aqc_add_get_update_free_vsi {
366 #define ICE_AQ_VSI_NUM_S 0
367 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
368 #define ICE_AQ_VSI_IS_VALID BIT(15)
370 #define ICE_AQ_VSI_KEEP_ALLOC 0x1
374 #define ICE_AQ_VSI_TYPE_S 0
375 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
376 #define ICE_AQ_VSI_TYPE_VF 0x0
377 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1
378 #define ICE_AQ_VSI_TYPE_PF 0x2
379 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
384 /* Response descriptor for:
385 * Add VSI (indirect 0x0210)
386 * Update VSI (indirect 0x0211)
387 * Free VSI (indirect 0x0213)
389 struct ice_aqc_add_update_free_vsi_resp {
398 struct ice_aqc_get_vsi_resp {
401 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values.
402 * These are found above in struct ice_aqc_add_get_update_free_vsi.
411 struct ice_aqc_vsi_props {
412 __le16 valid_sections;
413 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
414 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
415 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
416 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
417 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
418 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
419 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
420 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
421 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
422 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
423 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
427 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
428 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
429 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
431 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
432 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \
433 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
434 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
435 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
437 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
438 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
439 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
440 /* security section */
442 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
443 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
444 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
445 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
446 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
449 __le16 pvid; /* VLANS include priority bits */
450 u8 pvlan_reserved[2];
452 #define ICE_AQ_VSI_VLAN_MODE_S 0
453 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S)
454 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1
455 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2
456 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3
457 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2)
458 #define ICE_AQ_VSI_VLAN_EMOD_S 3
459 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
460 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S)
461 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S)
462 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S)
463 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
464 u8 pvlan_reserved2[3];
465 /* ingress egress up sections */
466 __le32 ingress_table; /* bitmap, 3 bits per up */
467 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0
468 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
469 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3
470 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
471 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6
472 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
473 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9
474 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
475 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12
476 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
477 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15
478 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
479 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18
480 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
481 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21
482 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
483 __le32 egress_table; /* same defines as for ingress table */
484 /* outer tags section */
487 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0
488 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)
489 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0
490 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1
491 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2
492 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
493 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
494 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
495 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
496 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
497 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
498 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4)
499 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)
500 u8 outer_tag_reserved;
501 /* queue mapping section */
502 __le16 mapping_flags;
503 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
504 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
505 __le16 q_mapping[16];
506 #define ICE_AQ_VSI_Q_S 0
507 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
508 __le16 tc_mapping[8];
509 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0
510 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
511 #define ICE_AQ_VSI_TC_Q_NUM_S 11
512 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
513 /* queueing option section */
515 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
516 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
517 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
518 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
519 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
520 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
521 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
522 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
523 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
524 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
525 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
526 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
527 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
529 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
530 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
531 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
533 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
534 u8 q_opt_reserved[3];
535 /* outer up section */
536 __le32 outer_up_table; /* same structure and defines as ingress tbl */
538 __le16 sect_10_reserved;
539 /* flow director section */
541 #define ICE_AQ_VSI_FD_ENABLE BIT(0)
542 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
543 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
544 __le16 max_fd_fltr_dedicated;
545 __le16 max_fd_fltr_shared;
547 #define ICE_AQ_VSI_FD_DEF_Q_S 0
548 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
549 #define ICE_AQ_VSI_FD_DEF_GRP_S 12
550 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
551 __le16 fd_report_opt;
552 #define ICE_AQ_VSI_FD_REPORT_Q_S 0
553 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
554 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
555 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
556 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
559 #define ICE_AQ_VSI_PASID_ID_S 0
560 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
561 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
565 /* Add/update mirror rule - direct (0x0260) */
566 #define ICE_AQC_RULE_ID_VALID_S 7
567 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S)
568 #define ICE_AQC_RULE_ID_S 0
569 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S)
571 /* Following defines to be used while processing caller specified mirror list
574 /* Action: Byte.bit (1.7)
575 * 0 = Remove VSI from mirror rule
576 * 1 = Add VSI to mirror rule
578 #define ICE_AQC_RULE_ACT_S 15
579 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S)
580 /* Action: 1.2:0.0 = Mirrored VSI */
581 #define ICE_AQC_RULE_MIRRORED_VSI_S 0
582 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S)
584 /* This is to be used by add/update mirror rule Admin Queue command.
585 * In case of add mirror rule - if rule ID is specified as
586 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool.
587 * If specified rule_id is valid, then it is used. If specified rule_id
588 * is in use then new mirroring rule is added.
590 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF
592 struct ice_aqc_add_update_mir_rule {
596 #define ICE_AQC_RULE_TYPE_S 0
597 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S)
598 /* VPORT ingress/egress */
599 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1
600 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2
601 /* Physical port ingress mirroring.
602 * All traffic received by this port
604 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6
605 /* Physical port egress mirroring. All traffic sent by this port */
606 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7
608 /* Number of mirrored entries.
609 * The values are in the command buffer
613 /* Destination VSI */
619 /* Delete mirror rule - direct(0x0261) */
620 struct ice_aqc_delete_mir_rule {
624 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of
625 * the PF allocated resources, otherwise it is returned to the
628 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0
629 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S)
635 /* Set/Get storm config - (direct 0x0280, 0x0281) */
636 /* This structure holds get storm configuration response and same structure
637 * is used to perform set_storm_cfg
639 struct ice_aqc_storm_cfg {
640 __le32 bcast_thresh_size;
641 __le32 mcast_thresh_size;
642 /* Bit 18:0 - Traffic upper threshold size
643 * Bit 31:19 - Reserved
645 #define ICE_AQ_THRESHOLD_S 0
646 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S)
648 __le32 storm_ctrl_ctrl;
649 /* Bit 0: MDIPW - Drop Multicast packets in previous window
650 * Bit 1: MDICW - Drop multicast packets in current window
651 * Bit 2: BDIPW - Drop broadcast packets in previous window
652 * Bit 3: BDICW - Drop broadcast packets in current window
654 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0)
655 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1)
656 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2)
657 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3)
658 /* Bit 7:5 : Reserved */
659 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The
660 * interval size for applying ingress broadcast or multicast storm
663 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8
664 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \
665 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S)
669 #define ICE_MAX_NUM_RECIPES 64
671 /* Add/Get Recipe (indirect 0x0290/0x0292)*/
672 struct ice_aqc_add_get_recipe {
673 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */
674 __le16 return_index; /* Input, used for Get cmd only */
680 struct ice_aqc_recipe_content {
682 #define ICE_AQ_RECIPE_ID_S 0
683 #define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S)
684 #define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7)
685 #define ICE_AQ_SW_ID_LKUP_IDX 0
687 #define ICE_AQ_RECIPE_LKUP_DATA_S 0
688 #define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S)
689 #define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7)
690 #define ICE_AQ_SW_ID_LKUP_MASK 0x00FF
693 #define ICE_AQ_RECIPE_RESULT_DATA_S 0
694 #define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S)
695 #define ICE_AQ_RECIPE_RESULT_EN BIT(7)
697 u8 act_ctrl_join_priority;
698 u8 act_ctrl_fwd_priority;
699 #define ICE_AQ_RECIPE_FWD_PRIORITY_S 0
700 #define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S)
702 #define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0)
703 #define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1)
704 #define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2)
705 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4
706 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S)
709 #define ICE_AQ_RECIPE_DFLT_ACT_S 0
710 #define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S)
711 #define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31)
714 struct ice_aqc_recipe_data_elem {
717 #define ICE_AQ_RECIPE_WAS_UPDATED BIT(0)
721 struct ice_aqc_recipe_content content;
725 /* This struct contains a number of entries as per the
726 * num_sub_recipes in the command
728 struct ice_aqc_add_get_recipe_data {
729 struct ice_aqc_recipe_data_elem recipe[1];
732 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */
733 struct ice_aqc_recipe_to_profile {
736 ice_declare_bitmap(recipe_assoc, ICE_MAX_NUM_RECIPES);
739 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
741 struct ice_aqc_sw_rules {
742 /* ops: add switch rules, referring the number of rules.
743 * ops: update switch rules, referring the number of filters
744 * ops: remove switch rules, referring the entry index.
745 * ops: get switch rules, referring to the number of filters.
747 __le16 num_rules_fltr_entry_index;
754 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
755 * This structures describes the lookup rules and associated actions. "index"
756 * is returned as part of a response to a successful Add command, and can be
757 * used to identify the rule for Update/Get/Remove commands.
759 struct ice_sw_rule_lkup_rx_tx {
761 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10
762 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
766 /* Bit 0:1 - Action type */
767 #define ICE_SINGLE_ACT_TYPE_S 0x00
768 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
770 /* Bit 2 - Loop back enable
773 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
774 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
776 /* Action type = 0 - Forward to VSI or VSI list */
777 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
779 #define ICE_SINGLE_ACT_VSI_ID_S 4
780 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
781 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4
782 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
783 /* This bit needs to be set if action is forward to VSI list */
784 #define ICE_SINGLE_ACT_VSI_LIST BIT(14)
785 #define ICE_SINGLE_ACT_VALID_BIT BIT(17)
786 #define ICE_SINGLE_ACT_DROP BIT(18)
788 /* Action type = 1 - Forward to Queue of Queue group */
789 #define ICE_SINGLE_ACT_TO_Q 0x1
790 #define ICE_SINGLE_ACT_Q_INDEX_S 4
791 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
792 #define ICE_SINGLE_ACT_Q_REGION_S 15
793 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
794 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
796 /* Action type = 2 - Prune */
797 #define ICE_SINGLE_ACT_PRUNE 0x2
798 #define ICE_SINGLE_ACT_EGRESS BIT(15)
799 #define ICE_SINGLE_ACT_INGRESS BIT(16)
800 #define ICE_SINGLE_ACT_PRUNET BIT(17)
801 /* Bit 18 should be set to 0 for this action */
803 /* Action type = 2 - Pointer */
804 #define ICE_SINGLE_ACT_PTR 0x2
805 #define ICE_SINGLE_ACT_PTR_VAL_S 4
806 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
807 /* Bit 18 should be set to 1 */
808 #define ICE_SINGLE_ACT_PTR_BIT BIT(18)
810 /* Action type = 3 - Other actions. Last two bits
811 * are other action identifier
813 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3
814 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
815 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
816 (0x3 << \ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
818 /* Bit 17:18 - Defines other actions */
819 /* Other action = 0 - Mirror VSI */
820 #define ICE_SINGLE_OTHER_ACT_MIRROR 0
821 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4
822 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \
823 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
825 /* Other action = 3 - Set Stat count */
826 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3
827 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4
828 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \
829 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
831 __le16 index; /* The index of the rule in the lookup table */
832 /* Length and values of the header to be matched per recipe or
840 /* Add/Update/Remove large action command/response entry
841 * "index" is returned as part of a response to a successful Add command, and
842 * can be used to identify the action for Update/Get/Remove commands.
844 struct ice_sw_rule_lg_act {
845 __le16 index; /* Index in large action table */
847 __le32 act[1]; /* array of size for actions */
848 /* Max number of large actions */
849 #define ICE_MAX_LG_ACT 4
850 /* Bit 0:1 - Action type */
851 #define ICE_LG_ACT_TYPE_S 0
852 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
854 /* Action type = 0 - Forward to VSI or VSI list */
855 #define ICE_LG_ACT_VSI_FORWARDING 0
856 #define ICE_LG_ACT_VSI_ID_S 3
857 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
858 #define ICE_LG_ACT_VSI_LIST_ID_S 3
859 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
860 /* This bit needs to be set if action is forward to VSI list */
861 #define ICE_LG_ACT_VSI_LIST BIT(13)
863 #define ICE_LG_ACT_VALID_BIT BIT(16)
865 /* Action type = 1 - Forward to Queue of Queue group */
866 #define ICE_LG_ACT_TO_Q 0x1
867 #define ICE_LG_ACT_Q_INDEX_S 3
868 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
869 #define ICE_LG_ACT_Q_REGION_S 14
870 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
871 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
873 /* Action type = 2 - Prune */
874 #define ICE_LG_ACT_PRUNE 0x2
875 #define ICE_LG_ACT_EGRESS BIT(14)
876 #define ICE_LG_ACT_INGRESS BIT(15)
877 #define ICE_LG_ACT_PRUNET BIT(16)
879 /* Action type = 3 - Mirror VSI */
880 #define ICE_LG_OTHER_ACT_MIRROR 0x3
881 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3
882 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
884 /* Action type = 5 - Generic Value */
885 #define ICE_LG_ACT_GENERIC 0x5
886 #define ICE_LG_ACT_GENERIC_VALUE_S 3
887 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
888 #define ICE_LG_ACT_GENERIC_OFFSET_S 19
889 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
890 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22
891 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
892 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7
894 /* Action = 7 - Set Stat count */
895 #define ICE_LG_ACT_STAT_COUNT 0x7
896 #define ICE_LG_ACT_STAT_COUNT_S 3
897 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
900 /* Add/Update/Remove VSI list command/response entry
901 * "index" is returned as part of a response to a successful Add command, and
902 * can be used to identify the VSI list for Update/Get/Remove commands.
904 struct ice_sw_rule_vsi_list {
905 __le16 index; /* Index of VSI/Prune list */
907 __le16 vsi[1]; /* Array of number_vsi VSI numbers */
911 /* Query VSI list command/response entry */
912 struct ice_sw_rule_vsi_list_query {
914 ice_declare_bitmap(vsi_list, ICE_MAX_VSI);
919 /* Add switch rule response:
920 * Content of return buffer is same as the input buffer. The status field and
921 * LUT index are updated as part of the response
923 struct ice_aqc_sw_rules_elem {
924 __le16 type; /* Switch rule type, one of T_... */
925 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
926 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
927 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2
928 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
929 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
930 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
931 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
934 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx;
935 struct ice_sw_rule_lg_act lg_act;
936 struct ice_sw_rule_vsi_list vsi_list;
937 struct ice_sw_rule_vsi_list_query vsi_list_query;
943 /* PFC Ignore (direct 0x0301)
944 * The command and response use the same descriptor structure
946 struct ice_aqc_pfc_ignore {
948 u8 cmd_flags; /* unused in response */
949 #define ICE_AQC_PFC_IGNORE_SET BIT(7)
950 #define ICE_AQC_PFC_IGNORE_CLEAR 0
954 /* Set PFC Mode (direct 0x0303)
955 * Query PFC Mode (direct 0x0302)
957 struct ice_aqc_set_query_pfc_mode {
959 /* For Set Command response, reserved in all other cases */
960 #define ICE_AQC_PFC_NOT_CONFIGURED 0
961 /* For Query Command response, reserved in all other cases */
962 #define ICE_AQC_DCB_DIS 0
963 #define ICE_AQC_PFC_VLAN_BASED_PFC 1
964 #define ICE_AQC_PFC_DSCP_BASED_PFC 2
968 /* Set DCB Parameters (direct 0x0306) */
969 struct ice_aqc_set_dcb_params {
970 u8 cmd_flags; /* unused in response */
971 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0)
972 u8 valid_flags; /* unused in response */
973 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0)
977 /* Get Default Topology (indirect 0x0400) */
978 struct ice_aqc_get_topo {
987 /* Update TSE (indirect 0x0403)
988 * Get TSE (indirect 0x0404)
989 * Add TSE (indirect 0x0401)
990 * Delete TSE (indirect 0x040F)
991 * Move TSE (indirect 0x0408)
992 * Suspend Nodes (indirect 0x0409)
993 * Resume Nodes (indirect 0x040A)
995 struct ice_aqc_sched_elem_cmd {
996 __le16 num_elem_req; /* Used by commands */
997 __le16 num_elem_resp; /* Used by responses */
1003 /* This is the buffer for:
1004 * Suspend Nodes (indirect 0x0409)
1005 * Resume Nodes (indirect 0x040A)
1007 struct ice_aqc_suspend_resume_elem {
1011 struct ice_aqc_txsched_move_grp_info_hdr {
1012 __le32 src_parent_teid;
1013 __le32 dest_parent_teid;
1018 struct ice_aqc_move_elem {
1019 struct ice_aqc_txsched_move_grp_info_hdr hdr;
1023 struct ice_aqc_elem_info_bw {
1024 __le16 bw_profile_idx;
1028 struct ice_aqc_txsched_elem {
1029 u8 elem_type; /* Special field, reserved for some aq calls */
1030 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
1031 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
1032 #define ICE_AQC_ELEM_TYPE_TC 0x2
1033 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
1034 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
1035 #define ICE_AQC_ELEM_TYPE_LEAF 0x5
1036 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
1038 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
1039 #define ICE_AQC_ELEM_VALID_CIR BIT(1)
1040 #define ICE_AQC_ELEM_VALID_EIR BIT(2)
1041 #define ICE_AQC_ELEM_VALID_SHARED BIT(3)
1043 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
1044 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
1045 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
1046 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4
1047 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
1048 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
1049 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \
1050 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
1051 u8 flags; /* Special field, reserved for some aq calls */
1052 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
1053 struct ice_aqc_elem_info_bw cir_bw;
1054 struct ice_aqc_elem_info_bw eir_bw;
1059 struct ice_aqc_txsched_elem_data {
1062 struct ice_aqc_txsched_elem data;
1065 struct ice_aqc_txsched_topo_grp_info_hdr {
1071 struct ice_aqc_add_elem {
1072 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1073 struct ice_aqc_txsched_elem_data generic[1];
1076 struct ice_aqc_conf_elem {
1077 struct ice_aqc_txsched_elem_data generic[1];
1080 struct ice_aqc_get_elem {
1081 struct ice_aqc_txsched_elem_data generic[1];
1084 struct ice_aqc_get_topo_elem {
1085 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1086 struct ice_aqc_txsched_elem_data
1087 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1090 struct ice_aqc_delete_elem {
1091 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1095 /* Query Port ETS (indirect 0x040E)
1097 * This indirect command is used to query port TC node configuration.
1099 struct ice_aqc_query_port_ets {
1106 struct ice_aqc_port_ets_elem {
1109 /* 3 bits for UP per TC 0-7, 4th byte reserved */
1112 __le32 port_eir_prof_id;
1113 __le32 port_cir_prof_id;
1114 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */
1115 __le32 tc_node_prio;
1116 #define ICE_TC_NODE_PRIO_S 0x4
1118 __le32 tc_node_teid[8]; /* Used for response, reserved in command */
1121 /* Rate limiting profile for
1122 * Add RL profile (indirect 0x0410)
1123 * Query RL profile (indirect 0x0411)
1124 * Remove RL profile (indirect 0x0415)
1125 * These indirect commands acts on single or multiple
1126 * RL profiles with specified data.
1128 struct ice_aqc_rl_profile {
1129 __le16 num_profiles;
1130 __le16 num_processed; /* Only for response. Reserved in Command. */
1136 struct ice_aqc_rl_profile_elem {
1139 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0
1140 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
1141 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0
1142 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1
1143 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2
1144 /* The following flag is used for Query RL Profile Data */
1145 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7
1146 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
1149 __le16 max_burst_size;
1151 __le16 wake_up_calc;
1155 struct ice_aqc_rl_profile_generic_elem {
1156 struct ice_aqc_rl_profile_elem generic[1];
1159 /* Configure L2 Node CGD (indirect 0x0414)
1160 * This indirect command allows configuring a congestion domain for given L2
1161 * node TEIDs in the scheduler topology.
1163 struct ice_aqc_cfg_l2_node_cgd {
1164 __le16 num_l2_nodes;
1170 struct ice_aqc_cfg_l2_node_cgd_elem {
1176 struct ice_aqc_cfg_l2_node_cgd_data {
1177 struct ice_aqc_cfg_l2_node_cgd_elem elem[1];
1180 /* Query Scheduler Resource Allocation (indirect 0x0412)
1181 * This indirect command retrieves the scheduler resources allocated by
1182 * EMP Firmware to the given PF.
1184 struct ice_aqc_query_txsched_res {
1190 struct ice_aqc_generic_sched_props {
1192 __le16 logical_levels;
1193 u8 flattening_bitmap;
1201 struct ice_aqc_layer_props {
1204 __le16 max_device_nodes;
1205 __le16 max_pf_nodes;
1207 __le16 max_sibl_grp_sz;
1208 __le16 max_cir_rl_profiles;
1209 __le16 max_eir_rl_profiles;
1210 __le16 max_srl_profiles;
1214 struct ice_aqc_query_txsched_res_resp {
1215 struct ice_aqc_generic_sched_props sched_props;
1216 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1219 /* Query Node to Root Topology (indirect 0x0413)
1220 * This command uses ice_aqc_get_elem as its data buffer.
1222 struct ice_aqc_query_node_to_root {
1224 __le32 num_nodes; /* Response only */
1229 /* Get PHY capabilities (indirect 0x0600) */
1230 struct ice_aqc_get_phy_caps {
1234 /* 18.0 - Report qualified modules */
1235 #define ICE_AQC_GET_PHY_RQM BIT(0)
1236 /* 18.1 - 18.2 : Report mode
1237 * 00b - Report NVM capabilities
1238 * 01b - Report topology capabilities
1239 * 10b - Report SW configured
1241 #define ICE_AQC_REPORT_MODE_S 1
1242 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S)
1243 #define ICE_AQC_REPORT_NVM_CAP 0
1244 #define ICE_AQC_REPORT_TOPO_CAP BIT(1)
1245 #define ICE_AQC_REPORT_SW_CFG BIT(2)
1251 /* This is #define of PHY type (Extended):
1252 * The first set of defines is for phy_type_low.
1254 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
1255 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
1256 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
1257 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
1258 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
1259 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
1260 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
1261 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
1262 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
1263 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
1264 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
1265 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
1266 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
1267 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
1268 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
1269 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
1270 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
1271 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
1272 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
1273 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
1274 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
1275 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
1276 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
1277 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
1278 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
1279 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
1280 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
1281 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
1282 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
1283 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
1284 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
1285 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
1286 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
1287 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
1288 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
1289 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
1290 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
1291 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
1292 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
1293 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
1294 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
1295 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
1296 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
1297 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
1298 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
1299 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
1300 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
1301 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
1302 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
1303 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
1304 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
1305 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
1306 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
1307 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
1308 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
1309 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
1310 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
1311 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
1312 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
1313 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
1314 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
1315 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
1316 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
1317 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
1318 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63
1319 /* The second set of defines is for phy_type_high. */
1320 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
1321 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
1322 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
1323 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
1324 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
1325 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 19
1327 struct ice_aqc_get_phy_caps_data {
1328 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1329 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1331 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
1332 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
1333 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
1334 #define ICE_AQC_PHY_EN_LINK BIT(3)
1335 #define ICE_AQC_PHY_AN_MODE BIT(4)
1336 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5)
1337 #define ICE_AQC_PHY_EN_LESM BIT(6)
1338 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
1339 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0)
1341 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
1343 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
1344 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
1345 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
1346 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
1347 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
1348 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
1349 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
1350 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7)
1351 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8)
1352 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9)
1353 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10)
1355 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
1357 u8 link_fec_options;
1358 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
1359 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
1360 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
1361 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
1362 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
1363 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
1364 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
1365 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0)
1366 u8 rsvd1; /* Byte 35 reserved */
1367 u8 extended_compliance_code;
1368 #define ICE_MODULE_TYPE_TOTAL_BYTE 3
1369 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
1370 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
1371 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
1372 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
1373 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
1374 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
1375 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
1376 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
1377 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
1378 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
1379 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
1380 u8 qualified_module_count;
1381 u8 rsvd2[7]; /* Bytes 47:41 reserved */
1382 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16
1389 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1392 /* Set PHY capabilities (direct 0x0601)
1393 * NOTE: This command must be followed by setup link and restart auto-neg
1395 struct ice_aqc_set_phy_cfg {
1402 /* Set PHY config command data structure */
1403 struct ice_aqc_set_phy_cfg_data {
1404 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1405 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1407 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0)
1408 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
1409 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
1410 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
1411 #define ICE_AQ_PHY_ENA_LINK BIT(3)
1412 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
1413 #define ICE_AQ_PHY_ENA_LESM BIT(6)
1414 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
1416 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1418 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1422 /* Set MAC Config command data structure (direct 0x0603) */
1423 struct ice_aqc_set_mac_cfg {
1424 __le16 max_frame_size;
1426 #define ICE_AQ_SET_MAC_PACE_S 3
1427 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)
1428 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
1429 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0
1430 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M
1432 __le16 tx_tmr_value;
1433 __le16 fc_refresh_threshold;
1435 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
1436 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0
1437 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
1441 /* Restart AN command data structure (direct 0x0605)
1442 * Also used for response, with only the lport_num field present.
1444 struct ice_aqc_restart_an {
1448 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
1449 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
1453 /* Get link status (indirect 0x0607), also used for Link Status Event */
1454 struct ice_aqc_get_link_status {
1458 #define ICE_AQ_LSE_M 0x3
1459 #define ICE_AQ_LSE_NOP 0x0
1460 #define ICE_AQ_LSE_DIS 0x2
1461 #define ICE_AQ_LSE_ENA 0x3
1462 /* only response uses this flag */
1463 #define ICE_AQ_LSE_IS_ENABLED 0x1
1469 /* Get link status response data structure, also used for Link Status Event */
1470 struct ice_aqc_get_link_status_data {
1471 u8 topo_media_conflict;
1472 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
1473 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
1474 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
1475 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4)
1476 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)
1477 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)
1478 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)
1480 #define ICE_AQ_LINK_CFG_ERR BIT(0)
1482 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */
1483 #define ICE_AQ_LINK_FAULT BIT(1)
1484 #define ICE_AQ_LINK_FAULT_TX BIT(2)
1485 #define ICE_AQ_LINK_FAULT_RX BIT(3)
1486 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
1487 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
1488 #define ICE_AQ_MEDIA_AVAILABLE BIT(6)
1489 #define ICE_AQ_SIGNAL_DETECT BIT(7)
1491 #define ICE_AQ_AN_COMPLETED BIT(0)
1492 #define ICE_AQ_LP_AN_ABILITY BIT(1)
1493 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
1494 #define ICE_AQ_FEC_EN BIT(3)
1495 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
1496 #define ICE_AQ_LINK_PAUSE_TX BIT(5)
1497 #define ICE_AQ_LINK_PAUSE_RX BIT(6)
1498 #define ICE_AQ_QUALIFIED_MODULE BIT(7)
1500 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
1501 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
1502 /* Port Tx Suspended */
1503 #define ICE_AQ_LINK_TX_S 2
1504 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
1505 #define ICE_AQ_LINK_TX_ACTIVE 0
1506 #define ICE_AQ_LINK_TX_DRAINED 1
1507 #define ICE_AQ_LINK_TX_FLUSHED 3
1509 #define ICE_AQ_LINK_LB_PHY_LCL BIT(0)
1510 #define ICE_AQ_LINK_LB_PHY_RMT BIT(1)
1511 #define ICE_AQ_LINK_LB_MAC_LCL BIT(2)
1512 #define ICE_AQ_LINK_LB_PHY_IDX_S 3
1513 #define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S)
1514 __le16 max_frame_size;
1516 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
1517 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
1518 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
1519 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0)
1521 #define ICE_AQ_CFG_PACING_S 3
1522 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
1523 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
1524 #define ICE_AQ_CFG_PACING_TYPE_AVG 0
1525 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
1526 /* External Device Power Ability */
1528 #define ICE_AQ_PWR_CLASS_M 0x3
1529 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
1530 #define ICE_AQ_LINK_PWR_BASET_HIGH 1
1531 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
1532 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
1533 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1534 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
1536 #define ICE_AQ_LINK_SPEED_M 0x7FF
1537 #define ICE_AQ_LINK_SPEED_10MB BIT(0)
1538 #define ICE_AQ_LINK_SPEED_100MB BIT(1)
1539 #define ICE_AQ_LINK_SPEED_1000MB BIT(2)
1540 #define ICE_AQ_LINK_SPEED_2500MB BIT(3)
1541 #define ICE_AQ_LINK_SPEED_5GB BIT(4)
1542 #define ICE_AQ_LINK_SPEED_10GB BIT(5)
1543 #define ICE_AQ_LINK_SPEED_20GB BIT(6)
1544 #define ICE_AQ_LINK_SPEED_25GB BIT(7)
1545 #define ICE_AQ_LINK_SPEED_40GB BIT(8)
1546 #define ICE_AQ_LINK_SPEED_50GB BIT(9)
1547 #define ICE_AQ_LINK_SPEED_100GB BIT(10)
1548 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1549 __le32 reserved3; /* Aligns next field to 8-byte boundary */
1550 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1551 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1554 /* Set event mask command (direct 0x0613) */
1555 struct ice_aqc_set_event_mask {
1559 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
1560 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
1561 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
1562 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
1563 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
1564 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
1565 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
1566 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
1567 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
1568 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10)
1569 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11)
1573 /* Set MAC Loopback command (direct 0x0620) */
1574 struct ice_aqc_set_mac_lb {
1576 #define ICE_AQ_MAC_LB_EN BIT(0)
1577 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
1581 struct ice_aqc_link_topo_addr {
1584 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
1586 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0
1587 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
1588 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0
1589 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1
1590 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2
1591 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3
1592 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4
1593 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5
1594 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6
1595 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7
1596 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8
1597 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4
1598 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \
1599 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
1600 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0
1601 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1
1602 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2
1603 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3
1604 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4
1605 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5
1608 #define ICE_AQC_LINK_TOPO_HANDLE_S 0
1609 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
1610 /* Used to decode the handle field */
1611 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)
1612 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)
1613 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0
1614 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0
1615 /* In case of a Mezzanine type */
1616 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \
1617 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1618 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6
1619 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
1620 /* In case of a LOM type */
1621 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \
1622 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1625 /* Get Link Topology Handle (direct, 0x06E0) */
1626 struct ice_aqc_get_link_topo {
1627 struct ice_aqc_link_topo_addr addr;
1632 /* Set Port Identification LED (direct, 0x06E9) */
1633 struct ice_aqc_set_port_id_led {
1636 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0)
1638 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
1639 #define ICE_AQC_PORT_IDENT_LED_ORIG 0
1643 /* Read/Write SFF EEPROM command (indirect 0x06EE) */
1644 struct ice_aqc_sff_eeprom {
1647 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)
1648 __le16 i2c_bus_addr;
1649 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F
1650 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF
1651 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10)
1652 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0
1653 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M
1654 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11
1655 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
1656 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0
1657 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1
1658 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2
1659 #define ICE_AQC_SFF_IS_WRITE BIT(15)
1660 __le16 i2c_mem_addr;
1662 #define ICE_AQC_SFF_EEPROM_BANK_S 0
1663 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
1664 #define ICE_AQC_SFF_EEPROM_PAGE_S 8
1665 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
1670 /* NVM Read command (indirect 0x0701)
1671 * NVM Erase commands (direct 0x0702)
1672 * NVM Write commands (indirect 0x0703)
1673 * NVM Write Activate commands (direct 0x0707)
1674 * NVM Shadow RAM Dump commands (direct 0x0707)
1676 struct ice_aqc_nvm {
1680 #define ICE_AQC_NVM_LAST_CMD BIT(0)
1681 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */
1682 #define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */
1683 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
1684 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
1685 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
1686 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
1687 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
1688 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */
1689 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)
1690 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)
1691 #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3)
1692 #define ICE_AQC_NVM_FLASH_ONLY BIT(7)
1693 __le16 module_typeid;
1695 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF
1700 /* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */
1701 #define ICE_AQC_NVM_SECTOR_UNIT 4096 /* In Bytes */
1702 #define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */
1704 #define ICE_AQC_NVM_START_POINT 0
1705 #define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90
1706 #define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */
1707 #define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0)
1708 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S 15
1709 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15)
1710 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1
1712 #define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46
1713 #define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */
1714 #define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */
1716 #define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129
1717 #define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */
1718 #define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0)
1719 #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */
1720 #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */
1722 /* Used for 0x0704 as well as for 0x0705 commands */
1723 struct ice_aqc_nvm_cfg {
1725 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0)
1726 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1)
1727 #define ICE_AQC_ANVM_NEW_CFG BIT(2)
1736 struct ice_aqc_nvm_cfg_data {
1738 __le16 field_options;
1742 /* NVM Checksum Command (direct, 0x0706) */
1743 struct ice_aqc_nvm_checksum {
1745 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
1746 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
1748 __le16 checksum; /* Used only by response */
1749 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
1753 /* Get LLDP MIB (indirect 0x0A00)
1754 * Note: This is also used by the LLDP MIB Change Event (0x0A01)
1755 * as the format is the same.
1757 struct ice_aqc_lldp_get_mib {
1759 #define ICE_AQ_LLDP_MIB_TYPE_S 0
1760 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
1761 #define ICE_AQ_LLDP_MIB_LOCAL 0
1762 #define ICE_AQ_LLDP_MIB_REMOTE 1
1763 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2
1764 #define ICE_AQ_LLDP_BRID_TYPE_S 2
1765 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
1766 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0
1767 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1
1768 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
1769 #define ICE_AQ_LLDP_TX_S 0x4
1770 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S)
1771 #define ICE_AQ_LLDP_TX_ACTIVE 0
1772 #define ICE_AQ_LLDP_TX_SUSPENDED 1
1773 #define ICE_AQ_LLDP_TX_FLUSHED 3
1774 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
1775 * and in the LLDP MIB Change Event (0x0A01). They are valid for the
1776 * Get LLDP MIB (0x0A00) response only.
1786 /* Configure LLDP MIB Change Event (direct 0x0A01) */
1787 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */
1788 struct ice_aqc_lldp_set_mib_change {
1790 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1791 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1
1795 /* Add LLDP TLV (indirect 0x0A02)
1796 * Delete LLDP TLV (indirect 0x0A04)
1798 struct ice_aqc_lldp_add_delete_tlv {
1799 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1807 /* Update LLDP TLV (indirect 0x0A03) */
1808 struct ice_aqc_lldp_update_tlv {
1809 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1818 /* Stop LLDP (direct 0x0A05) */
1819 struct ice_aqc_lldp_stop {
1821 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)
1822 #define ICE_AQ_LLDP_AGENT_STOP 0x0
1823 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK
1824 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1)
1828 /* Start LLDP (direct 0x0A06) */
1829 struct ice_aqc_lldp_start {
1831 #define ICE_AQ_LLDP_AGENT_START BIT(0)
1832 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1)
1836 /* Get CEE DCBX Oper Config (0x0A07)
1837 * The command uses the generic descriptor struct and
1838 * returns the struct below as an indirect response.
1840 struct ice_aqc_get_cee_dcb_cfg_resp {
1845 __le16 oper_app_prio;
1846 #define ICE_AQC_CEE_APP_FCOE_S 0
1847 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S)
1848 #define ICE_AQC_CEE_APP_ISCSI_S 3
1849 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S)
1850 #define ICE_AQC_CEE_APP_FIP_S 8
1851 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S)
1853 #define ICE_AQC_CEE_PG_STATUS_S 0
1854 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S)
1855 #define ICE_AQC_CEE_PFC_STATUS_S 3
1856 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S)
1857 #define ICE_AQC_CEE_FCOE_STATUS_S 8
1858 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
1859 #define ICE_AQC_CEE_ISCSI_STATUS_S 11
1860 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
1861 #define ICE_AQC_CEE_FIP_STATUS_S 16
1862 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S)
1866 /* Set Local LLDP MIB (indirect 0x0A08)
1867 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX
1869 struct ice_aqc_lldp_set_local_mib {
1871 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)
1872 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0
1873 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1)
1874 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0
1875 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M
1883 struct ice_aqc_lldp_set_local_mib_resp {
1885 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0)
1886 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0
1887 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M
1891 /* Stop/Start LLDP Agent (direct 0x0A09)
1892 * Used for stopping/starting specific LLDP agent. e.g. DCBX.
1893 * The same structure is used for the response, with the command field
1894 * being used as the status field.
1896 struct ice_aqc_lldp_stop_start_specific_agent {
1898 #define ICE_AQC_START_STOP_AGENT_M BIT(0)
1899 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0
1900 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M
1904 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
1905 struct ice_aqc_get_set_rss_key {
1906 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
1907 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0
1908 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
1915 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
1916 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
1917 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
1918 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
1919 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
1922 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer
1923 * @standard_rss_key: 40 most significant bytes of hash key
1924 * @extended_hash_key: 12 least significant bytes of hash key
1926 * Set/Get 40 byte hash key using standard_rss_key field, and set
1927 * extended_hash_key field to zero. Set/Get 52 byte hash key using
1928 * standard_rss_key field for 40 most significant bytes and the
1929 * extended_hash_key field for the 12 least significant bytes of hash key.
1931 struct ice_aqc_get_set_rss_keys {
1932 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
1933 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
1936 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
1937 struct ice_aqc_get_set_rss_lut {
1938 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
1939 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
1940 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
1942 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
1943 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \
1944 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
1946 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0
1947 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1
1948 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2
1950 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2
1951 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \
1952 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
1954 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128
1955 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0
1956 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512
1957 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
1958 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048
1959 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2
1961 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4
1962 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \
1963 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
1971 /* Clear FD Table Command (direct, 0x0B06) */
1972 struct ice_aqc_clear_fd_table {
1974 #define CL_FD_VM_VF_TYPE_VSI_IDX 1
1975 #define CL_FD_VM_VF_TYPE_PF_IDX 2
1981 /* Add Tx LAN Queues (indirect 0x0C30) */
1982 struct ice_aqc_add_txqs {
1990 /* This is the descriptor of each queue entry for the Add Tx LAN Queues
1991 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
1993 struct ice_aqc_add_txqs_perq {
1999 struct ice_aqc_txsched_elem info;
2002 /* The format of the command buffer for Add Tx LAN Queues (0x0C30)
2003 * is an array of the following structs. Please note that the length of
2004 * each struct ice_aqc_add_tx_qgrp is variable due
2005 * to the variable number of queues in each group!
2007 struct ice_aqc_add_tx_qgrp {
2011 struct ice_aqc_add_txqs_perq txqs[1];
2014 /* Disable Tx LAN Queues (indirect 0x0C31) */
2015 struct ice_aqc_dis_txqs {
2017 #define ICE_AQC_Q_DIS_CMD_S 0
2018 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
2019 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
2020 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
2021 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
2022 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)
2023 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
2024 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
2026 __le16 vmvf_and_timeout;
2027 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0
2028 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
2029 #define ICE_AQC_Q_DIS_TIMEOUT_S 10
2030 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
2031 __le32 blocked_cgds;
2036 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
2037 * contains the following structures, arrayed one after the
2039 * Note: Since the q_id is 16 bits wide, if the
2040 * number of queues is even, then 2 bytes of alignment MUST be
2041 * added before the start of the next group, to allow correct
2042 * alignment of the parent_teid field.
2044 struct ice_aqc_dis_txq_item {
2048 /* The length of the q_id array varies according to num_qs */
2050 /* This only applies from F8 onward */
2051 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
2052 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
2053 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
2054 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
2055 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
2058 struct ice_aqc_dis_txq {
2059 struct ice_aqc_dis_txq_item qgrps[1];
2062 /* Tx LAN Queues Cleanup Event (0x0C31) */
2063 struct ice_aqc_txqs_cleanup {
2069 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */
2070 struct ice_aqc_move_txqs {
2072 #define ICE_AQC_Q_CMD_TYPE_S 0
2073 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S)
2074 #define ICE_AQC_Q_CMD_TYPE_MOVE 1
2075 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2
2076 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3
2077 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2)
2078 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3)
2082 #define ICE_AQC_Q_CMD_TIMEOUT_S 2
2083 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S)
2084 __le32 blocked_cgds;
2089 /* This is the descriptor of each queue entry for the move Tx LAN Queues
2092 struct ice_aqc_move_txqs_elem {
2099 struct ice_aqc_move_txqs_data {
2102 struct ice_aqc_move_txqs_elem txqs[1];
2105 /* Download Package (indirect 0x0C40) */
2106 /* Also used for Update Package (indirect 0x0C42) */
2107 struct ice_aqc_download_pkg {
2109 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01
2116 struct ice_aqc_download_pkg_resp {
2117 __le32 error_offset;
2123 /* Get Package Info List (indirect 0x0C43) */
2124 struct ice_aqc_get_pkg_info_list {
2131 /* Version format for packages */
2132 struct ice_pkg_ver {
2139 #define ICE_PKG_NAME_SIZE 32
2141 struct ice_aqc_get_pkg_info {
2142 struct ice_pkg_ver ver;
2143 char name[ICE_PKG_NAME_SIZE];
2146 u8 is_active_at_boot;
2150 /* Get Package Info List response buffer format (0x0C43) */
2151 struct ice_aqc_get_pkg_info_resp {
2153 struct ice_aqc_get_pkg_info pkg_info[1];
2156 /* Lan Queue Overflow Event (direct, 0x1001) */
2157 struct ice_aqc_event_lan_overflow {
2158 __le32 prtdcb_ruptq;
2164 * struct ice_aq_desc - Admin Queue (AQ) descriptor
2165 * @flags: ICE_AQ_FLAG_* flags
2166 * @opcode: AQ command opcode
2167 * @datalen: length in bytes of indirect/external data buffer
2168 * @retval: return value from firmware
2169 * @cookie_h: opaque data high-half
2170 * @cookie_l: opaque data low-half
2171 * @params: command-specific parameters
2173 * Descriptor format for commands the driver posts on the Admin Transmit Queue
2174 * (ATQ). The firmware writes back onto the command descriptor and returns
2175 * the result of the command. Asynchronous events that are not an immediate
2176 * result of the command are written to the Admin Receive Queue (ARQ) using
2177 * the same descriptor format. Descriptors are in little-endian notation with
2180 struct ice_aq_desc {
2189 struct ice_aqc_generic generic;
2190 struct ice_aqc_get_ver get_ver;
2191 struct ice_aqc_driver_ver driver_ver;
2192 struct ice_aqc_q_shutdown q_shutdown;
2193 struct ice_aqc_req_res res_owner;
2194 struct ice_aqc_manage_mac_read mac_read;
2195 struct ice_aqc_manage_mac_write mac_write;
2196 struct ice_aqc_clear_pxe clear_pxe;
2197 struct ice_aqc_config_no_drop_policy no_drop;
2198 struct ice_aqc_add_update_mir_rule add_update_rule;
2199 struct ice_aqc_delete_mir_rule del_rule;
2200 struct ice_aqc_list_caps get_cap;
2201 struct ice_aqc_get_phy_caps get_phy;
2202 struct ice_aqc_set_phy_cfg set_phy;
2203 struct ice_aqc_restart_an restart_an;
2204 struct ice_aqc_sff_eeprom read_write_sff_param;
2205 struct ice_aqc_set_port_id_led set_port_id_led;
2206 struct ice_aqc_get_sw_cfg get_sw_conf;
2207 struct ice_aqc_sw_rules sw_rules;
2208 struct ice_aqc_storm_cfg storm_conf;
2209 struct ice_aqc_add_get_recipe add_get_recipe;
2210 struct ice_aqc_recipe_to_profile recipe_to_profile;
2211 struct ice_aqc_get_topo get_topo;
2212 struct ice_aqc_sched_elem_cmd sched_elem_cmd;
2213 struct ice_aqc_query_txsched_res query_sched_res;
2214 struct ice_aqc_query_node_to_root query_node_to_root;
2215 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd;
2216 struct ice_aqc_query_port_ets port_ets;
2217 struct ice_aqc_rl_profile rl_profile;
2218 struct ice_aqc_nvm nvm;
2219 struct ice_aqc_nvm_cfg nvm_cfg;
2220 struct ice_aqc_nvm_checksum nvm_checksum;
2221 struct ice_aqc_pfc_ignore pfc_ignore;
2222 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode;
2223 struct ice_aqc_set_dcb_params set_dcb_params;
2224 struct ice_aqc_lldp_get_mib lldp_get_mib;
2225 struct ice_aqc_lldp_set_mib_change lldp_set_event;
2226 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv;
2227 struct ice_aqc_lldp_update_tlv lldp_update_tlv;
2228 struct ice_aqc_lldp_stop lldp_stop;
2229 struct ice_aqc_lldp_start lldp_start;
2230 struct ice_aqc_lldp_set_local_mib lldp_set_mib;
2231 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
2232 struct ice_aqc_get_set_rss_lut get_set_rss_lut;
2233 struct ice_aqc_get_set_rss_key get_set_rss_key;
2234 struct ice_aqc_clear_fd_table clear_fd_table;
2235 struct ice_aqc_add_txqs add_txqs;
2236 struct ice_aqc_dis_txqs dis_txqs;
2237 struct ice_aqc_move_txqs move_txqs;
2238 struct ice_aqc_txqs_cleanup txqs_cleanup;
2239 struct ice_aqc_add_get_update_free_vsi vsi_cmd;
2240 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
2241 struct ice_aqc_get_vsi_resp get_vsi_resp;
2242 struct ice_aqc_download_pkg download_pkg;
2243 struct ice_aqc_get_pkg_info_list get_pkg_info_list;
2244 struct ice_aqc_set_mac_lb set_mac_lb;
2245 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
2246 struct ice_aqc_get_res_alloc get_res;
2247 struct ice_aqc_get_allocd_res_desc get_res_desc;
2248 struct ice_aqc_set_mac_cfg set_mac_cfg;
2249 struct ice_aqc_set_event_mask set_event_mask;
2250 struct ice_aqc_get_link_status get_link_status;
2251 struct ice_aqc_event_lan_overflow lan_overflow;
2252 struct ice_aqc_get_link_topo get_link_topo;
2256 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
2257 #define ICE_AQ_LG_BUF 512
2259 /* Flags sub-structure
2260 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
2261 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
2264 /* command flags and offsets */
2265 #define ICE_AQ_FLAG_DD_S 0
2266 #define ICE_AQ_FLAG_CMP_S 1
2267 #define ICE_AQ_FLAG_ERR_S 2
2268 #define ICE_AQ_FLAG_VFE_S 3
2269 #define ICE_AQ_FLAG_LB_S 9
2270 #define ICE_AQ_FLAG_RD_S 10
2271 #define ICE_AQ_FLAG_VFC_S 11
2272 #define ICE_AQ_FLAG_BUF_S 12
2273 #define ICE_AQ_FLAG_SI_S 13
2274 #define ICE_AQ_FLAG_EI_S 14
2275 #define ICE_AQ_FLAG_FE_S 15
2277 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */
2278 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */
2279 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
2280 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */
2281 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
2282 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
2283 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */
2284 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
2285 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
2286 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */
2287 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */
2291 ICE_AQ_RC_OK = 0, /* Success */
2292 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */
2293 ICE_AQ_RC_ENOENT = 2, /* No such element */
2294 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */
2295 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */
2296 ICE_AQ_RC_EIO = 5, /* I/O error */
2297 ICE_AQ_RC_ENXIO = 6, /* No such resource */
2298 ICE_AQ_RC_E2BIG = 7, /* Arg too long */
2299 ICE_AQ_RC_EAGAIN = 8, /* Try again */
2300 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
2301 ICE_AQ_RC_EACCES = 10, /* Permission denied */
2302 ICE_AQ_RC_EFAULT = 11, /* Bad address */
2303 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
2304 ICE_AQ_RC_EEXIST = 13, /* Object already exists */
2305 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */
2306 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */
2307 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
2308 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */
2309 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */
2310 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
2311 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
2312 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
2313 ICE_AQ_RC_EFBIG = 22, /* File too big */
2314 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */
2315 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
2316 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
2317 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
2318 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
2319 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
2320 ICE_AQ_RC_EACCES_BMCU = 29, /* BMC Update in progress */
2323 /* Admin Queue command opcodes */
2324 enum ice_adminq_opc {
2326 ice_aqc_opc_get_ver = 0x0001,
2327 ice_aqc_opc_driver_ver = 0x0002,
2328 ice_aqc_opc_q_shutdown = 0x0003,
2329 ice_aqc_opc_get_exp_err = 0x0005,
2331 /* resource ownership */
2332 ice_aqc_opc_req_res = 0x0008,
2333 ice_aqc_opc_release_res = 0x0009,
2335 /* device/function capabilities */
2336 ice_aqc_opc_list_func_caps = 0x000A,
2337 ice_aqc_opc_list_dev_caps = 0x000B,
2339 /* manage MAC address */
2340 ice_aqc_opc_manage_mac_read = 0x0107,
2341 ice_aqc_opc_manage_mac_write = 0x0108,
2344 ice_aqc_opc_clear_pxe_mode = 0x0110,
2346 ice_aqc_opc_config_no_drop_policy = 0x0112,
2348 /* internal switch commands */
2349 ice_aqc_opc_get_sw_cfg = 0x0200,
2351 /* Alloc/Free/Get Resources */
2352 ice_aqc_opc_get_res_alloc = 0x0204,
2353 ice_aqc_opc_alloc_res = 0x0208,
2354 ice_aqc_opc_free_res = 0x0209,
2355 ice_aqc_opc_get_allocd_res_desc = 0x020A,
2358 ice_aqc_opc_add_vsi = 0x0210,
2359 ice_aqc_opc_update_vsi = 0x0211,
2360 ice_aqc_opc_get_vsi_params = 0x0212,
2361 ice_aqc_opc_free_vsi = 0x0213,
2363 /* Mirroring rules - add/update, delete */
2364 ice_aqc_opc_add_update_mir_rule = 0x0260,
2365 ice_aqc_opc_del_mir_rule = 0x0261,
2367 /* storm configuration */
2368 ice_aqc_opc_set_storm_cfg = 0x0280,
2369 ice_aqc_opc_get_storm_cfg = 0x0281,
2371 /* recipe commands */
2372 ice_aqc_opc_add_recipe = 0x0290,
2373 ice_aqc_opc_recipe_to_profile = 0x0291,
2374 ice_aqc_opc_get_recipe = 0x0292,
2375 ice_aqc_opc_get_recipe_to_profile = 0x0293,
2377 /* switch rules population commands */
2378 ice_aqc_opc_add_sw_rules = 0x02A0,
2379 ice_aqc_opc_update_sw_rules = 0x02A1,
2380 ice_aqc_opc_remove_sw_rules = 0x02A2,
2381 ice_aqc_opc_get_sw_rules = 0x02A3,
2382 ice_aqc_opc_clear_pf_cfg = 0x02A4,
2385 ice_aqc_opc_pfc_ignore = 0x0301,
2386 ice_aqc_opc_query_pfc_mode = 0x0302,
2387 ice_aqc_opc_set_pfc_mode = 0x0303,
2388 ice_aqc_opc_set_dcb_params = 0x0306,
2390 /* transmit scheduler commands */
2391 ice_aqc_opc_get_dflt_topo = 0x0400,
2392 ice_aqc_opc_add_sched_elems = 0x0401,
2393 ice_aqc_opc_cfg_sched_elems = 0x0403,
2394 ice_aqc_opc_get_sched_elems = 0x0404,
2395 ice_aqc_opc_move_sched_elems = 0x0408,
2396 ice_aqc_opc_suspend_sched_elems = 0x0409,
2397 ice_aqc_opc_resume_sched_elems = 0x040A,
2398 ice_aqc_opc_query_port_ets = 0x040E,
2399 ice_aqc_opc_delete_sched_elems = 0x040F,
2400 ice_aqc_opc_add_rl_profiles = 0x0410,
2401 ice_aqc_opc_query_rl_profiles = 0x0411,
2402 ice_aqc_opc_query_sched_res = 0x0412,
2403 ice_aqc_opc_query_node_to_root = 0x0413,
2404 ice_aqc_opc_cfg_l2_node_cgd = 0x0414,
2405 ice_aqc_opc_remove_rl_profiles = 0x0415,
2408 ice_aqc_opc_get_phy_caps = 0x0600,
2409 ice_aqc_opc_set_phy_cfg = 0x0601,
2410 ice_aqc_opc_set_mac_cfg = 0x0603,
2411 ice_aqc_opc_restart_an = 0x0605,
2412 ice_aqc_opc_get_link_status = 0x0607,
2413 ice_aqc_opc_set_event_mask = 0x0613,
2414 ice_aqc_opc_set_mac_lb = 0x0620,
2415 ice_aqc_opc_get_link_topo = 0x06E0,
2416 ice_aqc_opc_set_port_id_led = 0x06E9,
2417 ice_aqc_opc_get_port_options = 0x06EA,
2418 ice_aqc_opc_set_port_option = 0x06EB,
2419 ice_aqc_opc_set_gpio = 0x06EC,
2420 ice_aqc_opc_get_gpio = 0x06ED,
2421 ice_aqc_opc_sff_eeprom = 0x06EE,
2424 ice_aqc_opc_nvm_read = 0x0701,
2425 ice_aqc_opc_nvm_erase = 0x0702,
2426 ice_aqc_opc_nvm_write = 0x0703,
2427 ice_aqc_opc_nvm_cfg_read = 0x0704,
2428 ice_aqc_opc_nvm_cfg_write = 0x0705,
2429 ice_aqc_opc_nvm_checksum = 0x0706,
2430 ice_aqc_opc_nvm_write_activate = 0x0707,
2431 ice_aqc_opc_nvm_sr_dump = 0x0707,
2432 ice_aqc_opc_nvm_save_factory_settings = 0x0708,
2433 ice_aqc_opc_nvm_update_empr = 0x0709,
2436 ice_aqc_opc_lldp_get_mib = 0x0A00,
2437 ice_aqc_opc_lldp_set_mib_change = 0x0A01,
2438 ice_aqc_opc_lldp_add_tlv = 0x0A02,
2439 ice_aqc_opc_lldp_update_tlv = 0x0A03,
2440 ice_aqc_opc_lldp_delete_tlv = 0x0A04,
2441 ice_aqc_opc_lldp_stop = 0x0A05,
2442 ice_aqc_opc_lldp_start = 0x0A06,
2443 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07,
2444 ice_aqc_opc_lldp_set_local_mib = 0x0A08,
2445 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,
2448 ice_aqc_opc_set_rss_key = 0x0B02,
2449 ice_aqc_opc_set_rss_lut = 0x0B03,
2450 ice_aqc_opc_get_rss_key = 0x0B04,
2451 ice_aqc_opc_get_rss_lut = 0x0B05,
2452 ice_aqc_opc_clear_fd_table = 0x0B06,
2454 /* Tx queue handling commands/events */
2455 ice_aqc_opc_add_txqs = 0x0C30,
2456 ice_aqc_opc_dis_txqs = 0x0C31,
2457 ice_aqc_opc_txqs_cleanup = 0x0C31,
2458 ice_aqc_opc_move_recfg_txqs = 0x0C32,
2460 /* package commands */
2461 ice_aqc_opc_download_pkg = 0x0C40,
2462 ice_aqc_opc_upload_section = 0x0C41,
2463 ice_aqc_opc_update_pkg = 0x0C42,
2464 ice_aqc_opc_get_pkg_info_list = 0x0C43,
2466 /* Standalone Commands/Events */
2467 ice_aqc_opc_event_lan_overflow = 0x1001,
2470 #endif /* _ICE_ADMINQ_CMD_H_ */