1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
10 #include "ice_flex_pipe.h"
11 #include "ice_switch.h"
21 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw);
22 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw);
23 enum ice_status ice_init_hw(struct ice_hw *hw);
24 void ice_deinit_hw(struct ice_hw *hw);
25 enum ice_status ice_check_reset(struct ice_hw *hw);
26 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req);
28 enum ice_status ice_create_all_ctrlq(struct ice_hw *hw);
29 enum ice_status ice_init_all_ctrlq(struct ice_hw *hw);
30 void ice_shutdown_all_ctrlq(struct ice_hw *hw);
31 void ice_destroy_all_ctrlq(struct ice_hw *hw);
33 ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
34 struct ice_rq_event_info *e, u16 *pending);
36 ice_get_link_status(struct ice_port_info *pi, bool *link_up);
37 enum ice_status ice_update_link_info(struct ice_port_info *pi);
39 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
40 enum ice_aq_res_access_type access, u32 timeout);
41 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res);
43 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res);
45 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res);
47 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
48 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
49 enum ice_adminq_opc opc, struct ice_sq_cd *cd);
51 ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
52 struct ice_aq_desc *desc, void *buf, u16 buf_size,
53 struct ice_sq_cd *cd);
54 void ice_clear_pxe_mode(struct ice_hw *hw);
56 enum ice_status ice_get_caps(struct ice_hw *hw);
58 void ice_set_safe_mode_caps(struct ice_hw *hw);
60 /* Define a macro that will align a pointer to point to the next memory address
61 * that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For
62 * example, given the variable pointer = 0x1006, then after the following call:
64 * pointer = ICE_ALIGN(pointer, 4)
66 * ... the value of pointer would equal 0x1008, since 0x1008 is the next
67 * address after 0x1006 which is divisible by 4.
69 #define ICE_ALIGN(ptr, align) (((ptr) + ((align) - 1)) & ~((align) - 1))
72 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
74 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index);
76 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index);
78 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
79 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
80 u32 tx_cmpltnq_index);
82 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index);
84 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
85 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
86 u32 tx_drbell_q_index);
89 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params);
91 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params);
93 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
94 struct ice_aqc_get_set_rss_keys *keys);
96 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
97 struct ice_aqc_get_set_rss_keys *keys);
99 ice_aq_add_lan_txq(struct ice_hw *hw, u8 count,
100 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
101 struct ice_sq_cd *cd);
103 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
104 bool is_tc_change, bool subseq_call, bool flush_pipe,
105 u8 timeout, u32 *blocked_cgds,
106 struct ice_aqc_move_txqs_data *buf, u16 buf_size,
107 u8 *txqs_moved, struct ice_sq_cd *cd);
109 bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);
110 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);
111 void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);
112 extern const struct ice_ctx_ele ice_tlan_ctx_info[];
114 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
115 const struct ice_ctx_ele *ce_info);
118 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,
119 void *buf, u16 buf_size, struct ice_sq_cd *cd);
120 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd);
123 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
124 struct ice_sq_cd *cd);
126 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
127 struct ice_aqc_get_phy_caps_data *caps,
128 struct ice_sq_cd *cd);
130 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
131 u16 link_speeds_bitmap);
133 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
134 struct ice_sq_cd *cd);
136 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw);
138 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
139 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);
140 bool ice_fw_supports_link_override(struct ice_hw *hw);
142 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
143 struct ice_port_info *pi);
144 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps);
146 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps);
147 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options);
149 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,
150 bool ena_auto_link_update);
152 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps,
153 struct ice_aqc_set_phy_cfg_data *cfg);
155 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
156 struct ice_aqc_get_phy_caps_data *caps,
157 struct ice_aqc_set_phy_cfg_data *cfg);
159 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
160 enum ice_fec_mode fec);
162 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
163 struct ice_sq_cd *cd);
165 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd);
167 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
168 struct ice_link_status *link, struct ice_sq_cd *cd);
170 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
171 struct ice_sq_cd *cd);
173 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd);
176 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
177 struct ice_sq_cd *cd);
179 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
180 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
181 bool write, struct ice_sq_cd *cd);
184 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info);
186 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
187 u16 *q_handle, u16 *q_ids, u32 *q_teids,
188 enum ice_disq_rst_src rst_src, u16 vmvf_num,
189 struct ice_sq_cd *cd);
191 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
194 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
195 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
196 struct ice_sq_cd *cd);
197 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle);
198 void ice_replay_post(struct ice_hw *hw);
200 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle);
202 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
203 u64 *prev_stat, u64 *cur_stat);
205 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
206 u64 *prev_stat, u64 *cur_stat);
208 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
209 struct ice_eth_stats *cur_stats);
210 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw);
211 void ice_print_rollback_msg(struct ice_hw *hw);
213 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
214 struct ice_aqc_txsched_elem_data *buf);
216 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
217 struct ice_sq_cd *cd);
218 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw);
220 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add);
221 #endif /* _ICE_COMMON_H_ */